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git01.mediatek.com / filogic / uboot / a45e6db3485eabbe3cb92baa5d87c19fa777e06f / . / arch / arm / dts / k3-j7200-mcu-wakeup.dtsi
blob: 1faffe62fe8084a4e0da9328fff32c7dd037c6ee [file] [log] [blame]
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
4 *
5 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8&cbass_mcu_wakeup {
9 dmsc: dmsc@44083000 {
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
12
13 mbox-names = "rx", "tx";
14
15 mboxes= <&secure_proxy_main 11>,
16 <&secure_proxy_main 13>;
17
18 reg-names = "debug_messages";
19 reg = <0x00 0x44083000 0x0 0x1000>;
20
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
24 };
25
26 k3_clks: clocks {
27 compatible = "ti,k2g-sci-clk";
28 #clock-cells = <2>;
29 };
30
31 k3_reset: reset-controller {
32 compatible = "ti,sci-reset";
33 #reset-cells = <2>;
34 };
35 };
36
37 chipid: chipid@43000014 {
38 compatible = "ti,am654-chipid";
39 reg = <0x0 0x43000014 0x0 0x4>;
40 };
41
42 wkup_pmx0: pinmux@4301c000 {
43 compatible = "pinctrl-single";
44 /* Proxy 0 addressing */
45 reg = <0x00 0x4301c000 0x00 0x178>;
46 #pinctrl-cells = <1>;
47 pinctrl-single,register-width = <32>;
48 pinctrl-single,function-mask = <0xffffffff>;
49 };
50
51 mcu_ram: sram@41c00000 {
52 compatible = "mmio-sram";
53 reg = <0x00 0x41c00000 0x00 0x100000>;
54 ranges = <0x0 0x00 0x41c00000 0x100000>;
55 #address-cells = <1>;
56 #size-cells = <1>;
57 };
58
59 wkup_uart0: serial@42300000 {
60 compatible = "ti,j721e-uart", "ti,am654-uart";
61 reg = <0x00 0x42300000 0x00 0x100>;
62 reg-shift = <2>;
63 reg-io-width = <4>;
64 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
65 clock-frequency = <48000000>;
66 current-speed = <115200>;
67 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
68 clocks = <&k3_clks 287 2>;
69 clock-names = "fclk";
70 };
71
72 wkup_i2c0: i2c@42120000 {
73 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
74 reg = <0x0 0x42120000 0x0 0x100>;
75 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
76 #address-cells = <1>;
77 #size-cells = <0>;
78 clock-names = "fck";
79 clocks = <&k3_clks 197 1>;
80 power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
81 };
82
83 mcu_uart0: serial@40a00000 {
84 compatible = "ti,j721e-uart", "ti,am654-uart";
85 reg = <0x00 0x40a00000 0x00 0x100>;
86 reg-shift = <2>;
87 reg-io-width = <4>;
88 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
89 clock-frequency = <96000000>;
90 current-speed = <115200>;
91 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
92 clocks = <&k3_clks 149 2>;
93 clock-names = "fclk";
94 };
95
Vignesh Raghavendraa7010092020-08-07 00:26:59 +0530[diff] [blame]96 fss: system-controller@47000000 {
97 compatible = "syscon", "simple-mfd";
98 reg = <0x0 0x47000000 0x0 0x100>;
99 #address-cells = <2>;
100 #size-cells = <2>;
101 ranges;
102
103 hbmc_mux: hbmc-mux {
104 compatible = "mmio-mux";
105 #mux-control-cells = <1>;
106 mux-reg-masks = <0x4 0x2>; /* HBMC select */
107 };
108
109 hbmc: hyperbus@47034000 {
110 compatible = "ti,am654-hbmc";
111 reg = <0x0 0x47034000 0x0 0x100>,
112 <0x5 0x00000000 0x1 0x0000000>;
113 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
114 #address-cells = <2>;
115 #size-cells = <1>;
116 mux-controls = <&hbmc_mux 0>;
117 clocks = <&k3_clks 102 5>;
118 assigned-clocks = <&k3_clks 102 5>;
119 assigned-clock-rates = <333333333>;
120 };
121 };
122
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]123 mcu_i2c0: i2c@40b00000 {
124 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
125 reg = <0x0 0x40b00000 0x0 0x100>;
126 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
127 #address-cells = <1>;
128 #size-cells = <0>;
129 clock-names = "fck";
130 clocks = <&k3_clks 194 1>;
131 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
132 };
133
134 mcu_i2c1: i2c@40b10000 {
135 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
136 reg = <0x0 0x40b10000 0x0 0x100>;
137 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
138 #address-cells = <1>;
139 #size-cells = <0>;
140 clock-names = "fck";
141 clocks = <&k3_clks 195 1>;
142 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
143 };
Vignesh Raghavendra2fae7222020-08-07 00:26:58 +0530[diff] [blame]144
Vignesh Raghavendrabae65802020-08-07 00:27:00 +0530[diff] [blame]145 cbass_mcu_navss: mcu-navss {
146 compatible = "simple-mfd";
147 #address-cells = <2>;
148 #size-cells = <2>;
149 ranges;
150 dma-coherent;
151 dma-ranges;
152
153 ti,sci-dev-id = <232>;
154
155 mcu_ringacc: ringacc@2b800000 {
156 compatible = "ti,am654-navss-ringacc";
157 reg = <0x0 0x2b800000 0x0 0x400000>,
158 <0x0 0x2b000000 0x0 0x400000>,
159 <0x0 0x28590000 0x0 0x100>,
160 <0x0 0x2a500000 0x0 0x40000>;
161 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
162 ti,num-rings = <286>;
163 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
164 ti,sci = <&dmsc>;
165 ti,sci-dev-id = <235>;
166 };
167
168 mcu_udmap: dma-controller@285c0000 {
169 compatible = "ti,j721e-navss-mcu-udmap";
170 reg = <0x0 0x285c0000 0x0 0x100>,
171 <0x0 0x2a800000 0x0 0x40000>,
172 <0x0 0x2aa00000 0x0 0x40000>;
173 reg-names = "gcfg", "rchanrt", "tchanrt";
174 #dma-cells = <1>;
175
176 ti,sci = <&dmsc>;
177 ti,sci-dev-id = <236>;
178 ti,ringacc = <&mcu_ringacc>;
179
180 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
181 <0x0f>; /* TX_HCHAN */
182 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
183 <0x0b>; /* RX_HCHAN */
184 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
185 };
186 };
187
Vignesh Raghavendra2fae7222020-08-07 00:26:58 +0530[diff] [blame]188 wkup_gpio0: gpio@42110000 {
189 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
190 reg = <0x0 0x42110000 0x0 0x100>;
191 gpio-controller;
192 #gpio-cells = <2>;
193 ti,ngpio = <84>;
194 ti,davinci-gpio-unbanked = <0>;
195 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
196 clocks = <&k3_clks 113 0>;
197 clock-names = "gpio";
198 };
Vignesh Raghavendrabae65802020-08-07 00:27:00 +0530[diff] [blame]199
200 mcu_conf: scm_conf@40f00000 {
201 compatible = "syscon", "simple-mfd";
202 reg = <0x0 0x40f00000 0x0 0x20000>;
203 #address-cells = <1>;
204 #size-cells = <1>;
205 ranges = <0x0 0x0 0x40f00000 0x20000>;
206
207 phy_gmii_sel: phy@4040 {
208 compatible = "ti,am654-cpsw-phy-sel";
209 reg = <0x4040 0x4>;
210 reg-names = "gmii-sel";
211 #phy-cells = <1>;
212 };
213 };
214
215 mcu_cpsw: ethernet@46000000 {
216 compatible = "ti,j721e-cpsw-nuss";
217 #address-cells = <2>;
218 #size-cells = <2>;
219 reg = <0x0 0x46000000 0x0 0x200000>;
220 reg-names = "cpsw_nuss";
221 ranges;
222 dma-coherent;
223 clocks = <&k3_clks 18 21>;
224 clock-names = "fck";
225 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
226
227 dmas = <&mcu_udmap 0xf000>,
228 <&mcu_udmap 0xf001>,
229 <&mcu_udmap 0xf002>,
230 <&mcu_udmap 0xf003>,
231 <&mcu_udmap 0xf004>,
232 <&mcu_udmap 0xf005>,
233 <&mcu_udmap 0xf006>,
234 <&mcu_udmap 0xf007>,
235 <&mcu_udmap 0x7000>;
236 dma-names = "tx0", "tx1", "tx2", "tx3",
237 "tx4", "tx5", "tx6", "tx7",
238 "rx";
239
240 ethernet-ports {
241 #address-cells = <1>;
242 #size-cells = <0>;
243
244 cpsw_port1: port@1 {
245 reg = <1>;
246 ti,mac-only;
247 ti,label = "port1";
248 ti,syscon-efuse = <&mcu_conf 0x200>;
249 phys = <&phy_gmii_sel 1>;
250 };
251 };
252
253 davinci_mdio: mdio@f00 {
254 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
255 reg = <0x0 0xf00 0x0 0x100>;
256 #address-cells = <1>;
257 #size-cells = <0>;
258 clocks = <&k3_clks 18 21>;
259 clock-names = "fck";
260 bus_freq = <1000000>;
261 };
262
263 cpts {
264 clocks = <&k3_clks 18 2>;
265 clock-names = "cpts";
266 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
267 interrupt-names = "cpts";
268 ti,cpts-ext-ts-inputs = <4>;
269 ti,cpts-periodic-outputs = <2>;
270 };
271 };
Suman Annae6833162020-08-17 18:15:10 -0500[diff] [blame]272
273 mcu_r5fss0: r5fss@41000000 {
274 compatible = "ti,j7200-r5fss";
Suman Annaa45e6db2021-01-26 18:20:56 -0600[diff] [blame^]275 ti,cluster-mode = <1>;
Suman Annae6833162020-08-17 18:15:10 -0500[diff] [blame]276 #address-cells = <1>;
277 #size-cells = <1>;
278 ranges = <0x41000000 0x00 0x41000000 0x20000>,
279 <0x41400000 0x00 0x41400000 0x20000>;
280 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
281
282 mcu_r5fss0_core0: r5f@41000000 {
283 compatible = "ti,j7200-r5f";
284 reg = <0x41000000 0x00010000>,
285 <0x41010000 0x00010000>;
286 reg-names = "atcm", "btcm";
287 ti,sci = <&dmsc>;
288 ti,sci-dev-id = <250>;
289 ti,sci-proc-ids = <0x01 0xff>;
290 resets = <&k3_reset 250 1>;
291 firmware-name = "j7200-mcu-r5f0_0-fw";
Suman Annaa45e6db2021-01-26 18:20:56 -0600[diff] [blame^]292 ti,atcm-enable = <1>;
293 ti,btcm-enable = <1>;
294 ti,loczrama = <1>;
Suman Annae6833162020-08-17 18:15:10 -0500[diff] [blame]295 };
296
297 mcu_r5fss0_core1: r5f@41400000 {
298 compatible = "ti,j7200-r5f";
299 reg = <0x41400000 0x00008000>,
300 <0x41410000 0x00008000>;
301 reg-names = "atcm", "btcm";
302 ti,sci = <&dmsc>;
303 ti,sci-dev-id = <251>;
304 ti,sci-proc-ids = <0x02 0xff>;
305 resets = <&k3_reset 251 1>;
306 firmware-name = "j7200-mcu-r5f0_1-fw";
Suman Annaa45e6db2021-01-26 18:20:56 -0600[diff] [blame^]307 ti,atcm-enable = <1>;
308 ti,btcm-enable = <1>;
309 ti,loczrama = <1>;
Suman Annae6833162020-08-17 18:15:10 -0500[diff] [blame]310 };
311 };
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]312};