blob: bd27e503cad1c2abf6015badffbc2e0dea2571d0 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Albert ARIBAUDf02c2542015-10-23 18:06:43 +02002/*
3 * (C) Copyright 2009
4 * Net Insight <www.netinsight.net>
5 * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
6 *
7 * Based on sheevaplug.h:
8 * (C) Copyright 2009
9 * Marvell Semiconductor <www.marvell.com>
10 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
Albert ARIBAUDf02c2542015-10-23 18:06:43 +020011 */
12
13#ifndef _CONFIG_OPENRD_H
14#define _CONFIG_OPENRD_H
15
16/*
Albert ARIBAUDf02c2542015-10-23 18:06:43 +020017 * High Level Configuration Options (easy to change)
18 */
19#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
20#define CONFIG_KW88F6281 1 /* SOC Name */
Albert ARIBAUDf02c2542015-10-23 18:06:43 +020021
Albert ARIBAUDf02c2542015-10-23 18:06:43 +020022#include "mv-common.h"
23
24/*
25 * Environment variables configurations
26 */
Albert ARIBAUDf02c2542015-10-23 18:06:43 +020027/*
28 * max 4k env size is enough, but in case of nand
29 * it has to be rounded to sector size
30 */
Albert ARIBAUDf02c2542015-10-23 18:06:43 +020031/*
32 * Environment is right behind U-Boot in flash. Make sure U-Boot
33 * doesn't grow into the environment area.
34 */
35#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET
36
37/*
38 * Default environment variables
39 */
Albert ARIBAUDf02c2542015-10-23 18:06:43 +020040
Tom Rini5ad8e112017-10-22 17:55:07 -040041#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console=ttyS0,115200 " \
42 CONFIG_MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \
Albert ARIBAUDf02c2542015-10-23 18:06:43 +020043 "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \
44 "x_bootcmd_usb=usb start\0" \
Tom Rini56ac8332018-07-27 07:56:59 -040045 "x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0"
Albert ARIBAUDf02c2542015-10-23 18:06:43 +020046
47/*
48 * Ethernet Driver configuration
49 */
50#ifdef CONFIG_CMD_NET
51# ifdef CONFIG_BOARD_IS_OPENRD_BASE
52# define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
53# else
54# define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
55# endif
56# ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE
57# define CONFIG_PHY_BASE_ADR 0x0
58# define PHY_NO "88E1121"
59# else
60# define CONFIG_PHY_BASE_ADR 0x8
61# define PHY_NO "88E1116"
62# endif
63#endif /* CONFIG_CMD_NET */
64
65/*
66 * SATA Driver configuration
67 */
68#ifdef CONFIG_MVSATA_IDE
69#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
70#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
71#endif /*CONFIG_MVSATA_IDE*/
72
Albert ARIBAUDf02c2542015-10-23 18:06:43 +020073#endif /* _CONFIG_OPENRD_BASE_H */