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git01.mediatek.com / filogic / uboot / a44cb16a32f901705e925ff4bd2521e878c1319f / . / include / configs / sama5d2_ptc_ek.h
blob: bf3c92bdf396a51518562c2c0b096c89e42a8fb8 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Ludovic Desroches1240d882017-11-17 14:57:12 +0800[diff] [blame]2/*
3 * Configuration file for the SAMA5D2 PTC EK Board.
4 *
5 * Copyright (C) 2017 Microchip Technology Inc.
6 * Wenyou Yang <wenyou.yang@microchip.com>
7 * Ludovic Desroches <ludovic.desroches@microchip.com>
Ludovic Desroches1240d882017-11-17 14:57:12 +0800[diff] [blame]8 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#include "at91-sama5_common.h"
14
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]15#undef CFG_SYS_AT91_MAIN_CLOCK
16#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
Ludovic Desroches1240d882017-11-17 14:57:12 +0800[diff] [blame]17
Ludovic Desroches1240d882017-11-17 14:57:12 +0800[diff] [blame]18/* SDRAM */
Tom Rinibb4dd962022-11-16 13:10:37 -0500[diff] [blame]19#define CFG_SYS_SDRAM_BASE 0x20000000
20#define CFG_SYS_SDRAM_SIZE 0x20000000
Ludovic Desroches1240d882017-11-17 14:57:12 +0800[diff] [blame]21
Ludovic Desroches1240d882017-11-17 14:57:12 +0800[diff] [blame]22/* NAND Flash */
23#ifdef CONFIG_CMD_NAND
Tom Rinib4213492022-11-12 17:36:51 -0500[diff] [blame]24#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
Ludovic Desroches1240d882017-11-17 14:57:12 +0800[diff] [blame]25/* our ALE is AD21 */
Tom Rinib4213492022-11-12 17:36:51 -0500[diff] [blame]26#define CFG_SYS_NAND_MASK_ALE BIT(21)
Ludovic Desroches1240d882017-11-17 14:57:12 +0800[diff] [blame]27/* our CLE is AD22 */
Tom Rinib4213492022-11-12 17:36:51 -0500[diff] [blame]28#define CFG_SYS_NAND_MASK_CLE BIT(22)
Ludovic Desroches1240d882017-11-17 14:57:12 +0800[diff] [blame]29#endif
30
31#endif /* __CONFIG_H */