Manivannan Sadhasivam | 474a5df | 2018-06-14 23:38:31 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
Amit Singh Tomar | ddc4c8e | 2020-04-19 19:28:26 +0530 | [diff] [blame] | 3 | * Memory map for Actions Semi Owl series SoCs. |
Manivannan Sadhasivam | 474a5df | 2018-06-14 23:38:31 +0530 | [diff] [blame] | 4 | * |
| 5 | * Copyright (C) 2015 Actions Semi Co., Ltd. |
| 6 | * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |
| 7 | */ |
| 8 | |
Manivannan Sadhasivam | 474a5df | 2018-06-14 23:38:31 +0530 | [diff] [blame] | 9 | #include <asm/armv8/mmu.h> |
| 10 | |
Amit Singh Tomar | ddc4c8e | 2020-04-19 19:28:26 +0530 | [diff] [blame] | 11 | static struct mm_region owl_mem_map[] = { |
Manivannan Sadhasivam | 474a5df | 2018-06-14 23:38:31 +0530 | [diff] [blame] | 12 | { |
| 13 | .virt = 0x0UL, /* DDR */ |
| 14 | .phys = 0x0UL, /* DDR */ |
| 15 | .size = 0x80000000UL, |
| 16 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 17 | PTE_BLOCK_INNER_SHARE |
| 18 | }, { |
| 19 | .virt = 0xE0000000UL, /* Peripheral block */ |
| 20 | .phys = 0xE0000000UL, /* Peripheral block */ |
| 21 | .size = 0x08000000UL, |
| 22 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 23 | PTE_BLOCK_NON_SHARE | |
| 24 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 25 | }, { |
| 26 | /* List terminator */ |
| 27 | 0, |
| 28 | } |
| 29 | }; |
| 30 | |
Amit Singh Tomar | ddc4c8e | 2020-04-19 19:28:26 +0530 | [diff] [blame] | 31 | struct mm_region *mem_map = owl_mem_map; |