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Manivannan Sadhasivam604ecc82018-06-14 23:38:32 +05301// SPDX-License-Identifier: GPL-2.0+
2/*
Amit Singh Tomarcae81932020-04-19 19:28:25 +05303 * Actions Semi Owl SoCs platform support.
Manivannan Sadhasivam604ecc82018-06-14 23:38:32 +05304 *
5 * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
6 */
7
Tom Rini4b9b5062024-04-30 07:35:37 -06008#include <config.h>
Simon Glassafb02152019-12-28 10:45:01 -07009#include <cpu_func.h>
Simon Glass97589732020-05-10 11:40:02 -060010#include <init.h>
Simon Glass274e0b02020-05-10 11:39:56 -060011#include <asm/cache.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060012#include <asm/global_data.h>
Tom Rini4b9b5062024-04-30 07:35:37 -060013#include <asm/u-boot.h>
Manivannan Sadhasivam604ecc82018-06-14 23:38:32 +053014#include <linux/arm-smccc.h>
15#include <linux/psci.h>
Manivannan Sadhasivam604ecc82018-06-14 23:38:32 +053016#include <asm/io.h>
17#include <asm/mach-types.h>
18#include <asm/psci.h>
19
Amit Singh Tomar66d495a2020-05-09 13:45:07 +053020#define DMM_INTERLEAVE_PER_CH_CFG 0xe0290028
21
Manivannan Sadhasivam604ecc82018-06-14 23:38:32 +053022DECLARE_GLOBAL_DATA_PTR;
23
Amit Singh Tomar66d495a2020-05-09 13:45:07 +053024unsigned int owl_get_ddrcap(void)
25{
26 unsigned int val, cap;
27
28 /* ddr capacity register initialized by ddr driver
29 * in early bootloader
30 */
31#if defined(CONFIG_MACH_S700)
32 val = (readl(DMM_INTERLEAVE_PER_CH_CFG) >> 8) & 0x7;
33 cap = (val + 1) * 256;
34#elif defined(CONFIG_MACH_S900)
35 val = (readl(DMM_INTERLEAVE_PER_CH_CFG) >> 8) & 0xf;
36 cap = 64 * (1 << val);
37#endif
38
39 return cap;
40}
41
Manivannan Sadhasivam604ecc82018-06-14 23:38:32 +053042/*
43 * dram_init - sets uboots idea of sdram size
44 */
45int dram_init(void)
46{
Amit Singh Tomar66d495a2020-05-09 13:45:07 +053047 gd->ram_size = owl_get_ddrcap() * 1024 * 1024;
Manivannan Sadhasivam604ecc82018-06-14 23:38:32 +053048 return 0;
49}
50
51/* This is called after dram_init() so use get_ram_size result */
52int dram_init_banksize(void)
53{
Tom Rinibb4dd962022-11-16 13:10:37 -050054 gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
Manivannan Sadhasivam604ecc82018-06-14 23:38:32 +053055 gd->bd->bi_dram[0].size = gd->ram_size;
56
57 return 0;
58}
59
60static void show_psci_version(void)
61{
62 struct arm_smccc_res res;
63
64 arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
65
66 printf("PSCI: v%ld.%ld\n",
Amit Singh Tomarcae81932020-04-19 19:28:25 +053067 PSCI_VERSION_MAJOR(res.a0),
Manivannan Sadhasivam604ecc82018-06-14 23:38:32 +053068 PSCI_VERSION_MINOR(res.a0));
69}
70
71int board_init(void)
72{
73 show_psci_version();
74
75 return 0;
76}
77
Harald Seiler6f14d5f2020-12-15 16:47:52 +010078void reset_cpu(void)
Manivannan Sadhasivam604ecc82018-06-14 23:38:32 +053079{
80 psci_system_reset();
81}