Manivannan Sadhasivam | 604ecc8 | 2018-06-14 23:38:32 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
Amit Singh Tomar | cae8193 | 2020-04-19 19:28:25 +0530 | [diff] [blame] | 3 | * Actions Semi Owl SoCs platform support. |
Manivannan Sadhasivam | 604ecc8 | 2018-06-14 23:38:32 +0530 | [diff] [blame] | 4 | * |
| 5 | * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |
| 6 | */ |
| 7 | |
Tom Rini | 4b9b506 | 2024-04-30 07:35:37 -0600 | [diff] [blame] | 8 | #include <config.h> |
Simon Glass | afb0215 | 2019-12-28 10:45:01 -0700 | [diff] [blame] | 9 | #include <cpu_func.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 10 | #include <init.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 11 | #include <asm/cache.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 12 | #include <asm/global_data.h> |
Tom Rini | 4b9b506 | 2024-04-30 07:35:37 -0600 | [diff] [blame] | 13 | #include <asm/u-boot.h> |
Manivannan Sadhasivam | 604ecc8 | 2018-06-14 23:38:32 +0530 | [diff] [blame] | 14 | #include <linux/arm-smccc.h> |
| 15 | #include <linux/psci.h> |
Manivannan Sadhasivam | 604ecc8 | 2018-06-14 23:38:32 +0530 | [diff] [blame] | 16 | #include <asm/io.h> |
| 17 | #include <asm/mach-types.h> |
| 18 | #include <asm/psci.h> |
| 19 | |
Amit Singh Tomar | 66d495a | 2020-05-09 13:45:07 +0530 | [diff] [blame] | 20 | #define DMM_INTERLEAVE_PER_CH_CFG 0xe0290028 |
| 21 | |
Manivannan Sadhasivam | 604ecc8 | 2018-06-14 23:38:32 +0530 | [diff] [blame] | 22 | DECLARE_GLOBAL_DATA_PTR; |
| 23 | |
Amit Singh Tomar | 66d495a | 2020-05-09 13:45:07 +0530 | [diff] [blame] | 24 | unsigned int owl_get_ddrcap(void) |
| 25 | { |
| 26 | unsigned int val, cap; |
| 27 | |
| 28 | /* ddr capacity register initialized by ddr driver |
| 29 | * in early bootloader |
| 30 | */ |
| 31 | #if defined(CONFIG_MACH_S700) |
| 32 | val = (readl(DMM_INTERLEAVE_PER_CH_CFG) >> 8) & 0x7; |
| 33 | cap = (val + 1) * 256; |
| 34 | #elif defined(CONFIG_MACH_S900) |
| 35 | val = (readl(DMM_INTERLEAVE_PER_CH_CFG) >> 8) & 0xf; |
| 36 | cap = 64 * (1 << val); |
| 37 | #endif |
| 38 | |
| 39 | return cap; |
| 40 | } |
| 41 | |
Manivannan Sadhasivam | 604ecc8 | 2018-06-14 23:38:32 +0530 | [diff] [blame] | 42 | /* |
| 43 | * dram_init - sets uboots idea of sdram size |
| 44 | */ |
| 45 | int dram_init(void) |
| 46 | { |
Amit Singh Tomar | 66d495a | 2020-05-09 13:45:07 +0530 | [diff] [blame] | 47 | gd->ram_size = owl_get_ddrcap() * 1024 * 1024; |
Manivannan Sadhasivam | 604ecc8 | 2018-06-14 23:38:32 +0530 | [diff] [blame] | 48 | return 0; |
| 49 | } |
| 50 | |
| 51 | /* This is called after dram_init() so use get_ram_size result */ |
| 52 | int dram_init_banksize(void) |
| 53 | { |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 54 | gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; |
Manivannan Sadhasivam | 604ecc8 | 2018-06-14 23:38:32 +0530 | [diff] [blame] | 55 | gd->bd->bi_dram[0].size = gd->ram_size; |
| 56 | |
| 57 | return 0; |
| 58 | } |
| 59 | |
| 60 | static void show_psci_version(void) |
| 61 | { |
| 62 | struct arm_smccc_res res; |
| 63 | |
| 64 | arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res); |
| 65 | |
| 66 | printf("PSCI: v%ld.%ld\n", |
Amit Singh Tomar | cae8193 | 2020-04-19 19:28:25 +0530 | [diff] [blame] | 67 | PSCI_VERSION_MAJOR(res.a0), |
Manivannan Sadhasivam | 604ecc8 | 2018-06-14 23:38:32 +0530 | [diff] [blame] | 68 | PSCI_VERSION_MINOR(res.a0)); |
| 69 | } |
| 70 | |
| 71 | int board_init(void) |
| 72 | { |
| 73 | show_psci_version(); |
| 74 | |
| 75 | return 0; |
| 76 | } |
| 77 | |
Harald Seiler | 6f14d5f | 2020-12-15 16:47:52 +0100 | [diff] [blame] | 78 | void reset_cpu(void) |
Manivannan Sadhasivam | 604ecc8 | 2018-06-14 23:38:32 +0530 | [diff] [blame] | 79 | { |
| 80 | psci_system_reset(); |
| 81 | } |