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Guennadi Liakhovetski3b26c6b2008-04-14 10:53:12 +02001/*
2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
3 *
4 * Configuration settings for the MX31ADS Freescale board.
5 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02006 * SPDX-License-Identifier: GPL-2.0+
Guennadi Liakhovetski3b26c6b2008-04-14 10:53:12 +02007 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
Stefano Babic78129d92011-03-14 15:43:56 +010012#include <asm/arch/imx-regs.h>
Guennadi Liakhovetski3b26c6b2008-04-14 10:53:12 +020013
14 /* High Level Configuration Options */
Masahiro Yamadaa8b4c8c2014-11-06 14:59:37 +090015#define CONFIG_MX31 1 /* This is a mx31 */
Guennadi Liakhovetski3b26c6b2008-04-14 10:53:12 +020016
Fabio Estevama5a2a562011-09-22 08:07:16 +000017#define CONFIG_MACH_TYPE MACH_TYPE_MX31ADS
18
Guennadi Liakhovetski3b26c6b2008-04-14 10:53:12 +020019#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
20#define CONFIG_SETUP_MEMORY_TAGS 1
21#define CONFIG_INITRD_TAG 1
22
23/*
24 * Size of malloc() pool
25 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020026#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
Guennadi Liakhovetski3b26c6b2008-04-14 10:53:12 +020027
28/*
29 * Hardware drivers
30 */
31
Stefano Babic1ca47d92011-11-22 15:22:39 +010032#define CONFIG_MXC_UART
33#define CONFIG_MXC_UART_BASE UART1_BASE
Guennadi Liakhovetski3b26c6b2008-04-14 10:53:12 +020034
Guennadi Liakhovetski1116a392008-04-15 13:33:11 +020035#define CONFIG_HARD_SPI 1
Haavard Skinnemoend74084a2008-05-16 11:10:31 +020036#define CONFIG_DEFAULT_SPI_BUS 1
Stefano Babic4c596992010-08-23 20:41:19 +020037#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
Guennadi Liakhovetski1116a392008-04-15 13:33:11 +020038
Stefano Babic0c56af62011-10-08 11:02:53 +020039/* PMIC Controller */
Ɓukasz Majewski1b6d9ed2012-11-13 03:22:14 +000040#define CONFIG_POWER
41#define CONFIG_POWER_SPI
42#define CONFIG_POWER_FSL
Stefano Babice0432032010-04-16 17:11:19 +020043#define CONFIG_FSL_PMIC_BUS 1
44#define CONFIG_FSL_PMIC_CS 0
45#define CONFIG_FSL_PMIC_CLK 1000000
Stefano Babic4c596992010-08-23 20:41:19 +020046#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
Stefano Babic0c56af62011-10-08 11:02:53 +020047#define CONFIG_FSL_PMIC_BITLEN 32
Fabio Estevam3f8d1782011-10-24 06:44:15 +000048#define CONFIG_RTC_MC13XXX
Guennadi Liakhovetski1116a392008-04-15 13:33:11 +020049
Guennadi Liakhovetski3b26c6b2008-04-14 10:53:12 +020050/* allow to overwrite serial and ethaddr */
51#define CONFIG_ENV_OVERWRITE
Guennadi Liakhovetski3b26c6b2008-04-14 10:53:12 +020052
Guennadi Liakhovetskicd28dab2008-04-28 00:25:32 +020053#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
Guennadi Liakhovetski3b26c6b2008-04-14 10:53:12 +020054
Guennadi Liakhovetski1116a392008-04-15 13:33:11 +020055#define CONFIG_EXTRA_ENV_SETTINGS \
56 "netdev=eth0\0" \
57 "uboot_addr=0xa0000000\0" \
58 "uboot=mx31ads/u-boot.bin\0" \
59 "kernel=mx31ads/uImage\0" \
60 "nfsroot=/opt/eldk/arm\0" \
61 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
62 "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \
63 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
64 "bootcmd=run bootcmd_net\0" \
65 "bootcmd_net=run bootargs_base bootargs_nfs; " \
66 "tftpboot ${loadaddr} ${kernel}; bootm\0" \
67 "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \
68 "protect off ${uboot_addr} 0xa003ffff; " \
69 "erase ${uboot_addr} 0xa003ffff; " \
70 "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \
71 "setenv filesize; saveenv\0"
Guennadi Liakhovetski3b26c6b2008-04-14 10:53:12 +020072
Ben Warren3bf5d832009-08-25 13:09:37 -070073#define CONFIG_CS8900
74#define CONFIG_CS8900_BASE 0xb4020300
75#define CONFIG_CS8900_BUS16 1 /* follow the Linux driver */
Guennadi Liakhovetski3b26c6b2008-04-14 10:53:12 +020076
77/*
Guennadi Liakhovetski0c8382b2008-04-03 17:04:22 +020078 * The MX31ADS board seems to have a hardware "peculiarity" confirmed under
79 * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
80 * controller inverted. The controller is capable of detecting and correcting
81 * this, but it needs 4 network packets for that. Which means, at startup, you
82 * will not receive answers to the first 4 packest, unless there have been some
83 * broadcasts on the network, or your board is on a hub. Reducing the ARP
84 * timeout from default 5 seconds to 200ms we speed up the initial TFTP
85 * transfer, should the user wish one, significantly.
86 */
87#define CONFIG_ARP_TIMEOUT 200UL
88
89/*
Guennadi Liakhovetski3b26c6b2008-04-14 10:53:12 +020090 * Miscellaneous configurable options
91 */
Guennadi Liakhovetski3b26c6b2008-04-14 10:53:12 +020092
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020093#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
94#define CONFIG_SYS_MEMTEST_END 0x10000
Guennadi Liakhovetski3b26c6b2008-04-14 10:53:12 +020095
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020096#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
Guennadi Liakhovetski3b26c6b2008-04-14 10:53:12 +020097
Guennadi Liakhovetski3b26c6b2008-04-14 10:53:12 +020098/*-----------------------------------------------------------------------
Guennadi Liakhovetski3b26c6b2008-04-14 10:53:12 +020099 * Physical Memory Map
100 */
101#define CONFIG_NR_DRAM_BANKS 1
102#define PHYS_SDRAM_1 CSD0_BASE
103#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
Fabio Estevam574cff72011-06-05 06:26:49 +0000104
105#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
106#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
107#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
108#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
109 GENERATED_GBL_DATA_SIZE)
110#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
111 CONFIG_SYS_GBL_DATA_OFFSET)
Guennadi Liakhovetski3b26c6b2008-04-14 10:53:12 +0200112
113/*-----------------------------------------------------------------------
114 * FLASH and environment organization
115 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200116#define CONFIG_SYS_FLASH_BASE CS0_BASE
117#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
118#define CONFIG_SYS_MAX_FLASH_SECT 262 /* max number of sectors on one chip */
119#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
120#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256KiB */
Guennadi Liakhovetski3b26c6b2008-04-14 10:53:12 +0200121
Felix Radensky1c34eed2011-06-06 05:06:07 +0000122#define CONFIG_ENV_SECT_SIZE (128 * 1024)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200123#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
Felix Radensky1c34eed2011-06-06 05:06:07 +0000124#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Guennadi Liakhovetski0c8382b2008-04-03 17:04:22 +0200125
126/* Address and size of Redundant Environment Sector */
Felix Radensky1c34eed2011-06-06 05:06:07 +0000127#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200128#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
Guennadi Liakhovetski0c8382b2008-04-03 17:04:22 +0200129
Guennadi Liakhovetski3b26c6b2008-04-14 10:53:12 +0200130/*-----------------------------------------------------------------------
131 * CFI FLASH driver setup
132 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200133#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200134#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
Guennadi Liakhovetski0c8382b2008-04-03 17:04:22 +0200135#define CONFIG_FLASH_SPANSION_S29WS_N 1 /* A non-standard buffered write algorithm */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200136#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
137#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
Guennadi Liakhovetski3b26c6b2008-04-14 10:53:12 +0200138
139/*
140 * JFFS2 partitions
141 */
Guennadi Liakhovetski3b26c6b2008-04-14 10:53:12 +0200142#define CONFIG_JFFS2_DEV "nor0"
143
144#endif /* __CONFIG_H */