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Enric Balletbò i Serra9d89b082015-09-07 07:43:20 +02001/*
2 * am335x_sl50.h
3 *
4 * Copyright (C) 2015 Toby Churchill Ltd - http://www.toby-churchill.com/
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef __CONFIG_AM335X_EVM_H
10#define __CONFIG_AM335X_EVM_H
11
12#include <configs/ti_am335x_common.h>
Enric Balletbò i Serra9d89b082015-09-07 07:43:20 +020013
14#ifndef CONFIG_SPL_BUILD
Enric Balletbò i Serra9d89b082015-09-07 07:43:20 +020015# define CONFIG_TIMESTAMP
Enric Balletbò i Serra9d89b082015-09-07 07:43:20 +020016#endif
17
18#define CONFIG_SYS_BOOTM_LEN (16 << 20)
19
20/*#define CONFIG_MACH_TYPE 3589 Until the next sync */
Enric Balletbò i Serra9d89b082015-09-07 07:43:20 +020021
22/* Clock Defines */
23#define V_OSCK 24000000 /* Clock output from T2 */
24#define V_SCLK (V_OSCK)
25
26/* Always 128 KiB env size */
27#define CONFIG_ENV_SIZE (128 << 10)
28
Enric Balletbò i Serra9d89b082015-09-07 07:43:20 +020029#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
30
31#ifndef CONFIG_SPL_BUILD
32
Enric Balletbò i Serra9d89b082015-09-07 07:43:20 +020033#define MEM_LAYOUT_ENV_SETTINGS \
34 "scriptaddr=0x80000000\0" \
35 "pxefile_addr_r=0x80100000\0" \
36 "kernel_addr_r=0x82000000\0" \
37 "fdt_addr_r=0x88000000\0" \
38 "ramdisk_addr_r=0x88080000\0" \
39
40#define BOOT_TARGET_DEVICES(func) \
41 func(MMC, mmc, 0) \
42 func(MMC, mmc, 1)
43
44#define AM335XX_BOARD_FDTFILE \
45 "fdtfile=am335x-sl50.dtb\0" \
46
47#include <config_distro_bootcmd.h>
48
49#define CONFIG_EXTRA_ENV_SETTINGS \
50 AM335XX_BOARD_FDTFILE \
51 MEM_LAYOUT_ENV_SETTINGS \
52 BOOTENV
53
54#endif
55
56/* NS16550 Configuration */
57#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
58#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
59#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
60#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
61#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
62#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
Enric Balletbò i Serra9d89b082015-09-07 07:43:20 +020063
Enric Balletbò i Serra9d89b082015-09-07 07:43:20 +020064#define CONFIG_ENV_EEPROM_IS_ON_I2C
65#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
66#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
Enric Balletbò i Serra9d89b082015-09-07 07:43:20 +020067
68/* PMIC support */
69#define CONFIG_POWER_TPS65217
70#define CONFIG_POWER_TPS65910
71
72/* SPL */
Enric Balletbò i Serra9d89b082015-09-07 07:43:20 +020073
74/* Bootcount using the RTC block */
Enric Balletbò i Serra9d89b082015-09-07 07:43:20 +020075#define CONFIG_SYS_BOOTCOUNT_BE
76
Faiz Abbasc01553b2018-02-16 21:17:44 +053077#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USB_ETHER)
Enric Balletbò i Serra9d89b082015-09-07 07:43:20 +020078/* Remove other SPL modes. */
Enric Balletbò i Serra9d89b082015-09-07 07:43:20 +020079/* disable host part of MUSB in SPL */
80#undef CONFIG_MUSB_HOST
81/* disable EFI partitions and partition UUID support */
Enric Balletbò i Serra9d89b082015-09-07 07:43:20 +020082#endif
83
84#if defined(CONFIG_EMMC_BOOT)
Enric Balletbò i Serra9d89b082015-09-07 07:43:20 +020085#define CONFIG_SYS_MMC_ENV_DEV 1
86#define CONFIG_SYS_MMC_ENV_PART 2
87#define CONFIG_ENV_OFFSET 0x0
88#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
89#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
90#endif
91
92/* Network. */
Enric Balletbò i Serra9d89b082015-09-07 07:43:20 +020093#define CONFIG_PHY_SMSC
94
95#endif /* ! __CONFIG_AM335X_SL50_H */