| Michal Simek | 52cc06a | 2019-04-11 10:35:37 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * dts file for Xilinx Versal a2197 RevA System Controller |
| 4 | * |
| 5 | * (C) Copyright 2019, Xilinx, Inc. |
| 6 | * |
| Michal Simek | a8c9436 | 2023-07-10 14:35:49 +0200 | [diff] [blame] | 7 | * Michal Simek <michal.simek@amd.com> |
| Michal Simek | 52cc06a | 2019-04-11 10:35:37 +0200 | [diff] [blame] | 8 | */ |
| 9 | /dts-v1/; |
| 10 | |
| 11 | #include "zynqmp.dtsi" |
| 12 | #include "zynqmp-clk-ccf.dtsi" |
| 13 | #include <dt-bindings/gpio/gpio.h> |
| 14 | |
| 15 | / { |
| 16 | model = "Versal System Controller on a2197 board RevA"; |
| 17 | compatible = "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; |
| 18 | |
| 19 | aliases { |
| 20 | i2c0 = &i2c0; |
| Michal Simek | 53b145d | 2021-06-03 11:46:50 +0200 | [diff] [blame] | 21 | nvmem0 = &eeprom1; |
| 22 | nvmem1 = &eeprom0; |
| Michal Simek | 52cc06a | 2019-04-11 10:35:37 +0200 | [diff] [blame] | 23 | serial0 = &uart0; |
| 24 | }; |
| 25 | |
| 26 | chosen { |
| 27 | bootargs = "earlycon"; |
| 28 | stdout-path = "serial0:115200n8"; |
| Michal Simek | 52cc06a | 2019-04-11 10:35:37 +0200 | [diff] [blame] | 29 | }; |
| 30 | |
| 31 | memory@0 { |
| 32 | device_type = "memory"; |
| 33 | reg = <0x0 0x0 0x0 0x80000000>; |
| 34 | }; |
| 35 | }; |
| 36 | |
| 37 | &uart0 { /* uart0 MIO38-39 */ |
| 38 | status = "okay"; |
| Michal Simek | 52cc06a | 2019-04-11 10:35:37 +0200 | [diff] [blame] | 39 | }; |
| 40 | |
| 41 | &i2c0 { |
| 42 | status = "okay"; |
| Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 43 | bootph-all; |
| Michal Simek | 52cc06a | 2019-04-11 10:35:37 +0200 | [diff] [blame] | 44 | clock-frequency = <400000>; |
| 45 | i2c-mux@74 { /* this cover MGT board */ |
| 46 | compatible = "nxp,pca9548"; |
| 47 | #address-cells = <1>; |
| 48 | #size-cells = <0>; |
| 49 | reg = <0x74>; |
| Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 50 | bootph-all; |
| Michal Simek | 52cc06a | 2019-04-11 10:35:37 +0200 | [diff] [blame] | 51 | /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ |
| 52 | i2c@0 { |
| 53 | #address-cells = <1>; |
| 54 | #size-cells = <0>; |
| 55 | reg = <0>; |
| 56 | /* Use for storing information about SC board */ |
| 57 | eeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */ |
| 58 | compatible = "atmel,24c32"; |
| Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 59 | bootph-all; |
| Michal Simek | 52cc06a | 2019-04-11 10:35:37 +0200 | [diff] [blame] | 60 | reg = <0x50>; |
| 61 | }; |
| 62 | }; |
| 63 | }; |
| 64 | }; |
| 65 | |
| 66 | &i2c1 { |
| 67 | status = "okay"; |
| Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 68 | bootph-all; |
| Michal Simek | 52cc06a | 2019-04-11 10:35:37 +0200 | [diff] [blame] | 69 | clock-frequency = <400000>; |
| 70 | i2c-mux@74 { /* This cover processor board */ |
| 71 | compatible = "nxp,pca9548"; |
| 72 | #address-cells = <1>; |
| 73 | #size-cells = <0>; |
| 74 | reg = <0x74>; |
| Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 75 | bootph-all; |
| Michal Simek | 52cc06a | 2019-04-11 10:35:37 +0200 | [diff] [blame] | 76 | /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ |
| 77 | i2c@0 { |
| 78 | #address-cells = <1>; |
| 79 | #size-cells = <0>; |
| 80 | reg = <0>; |
| 81 | /* Use for storing information about SC board */ |
| 82 | eeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */ |
| 83 | compatible = "atmel,24c32"; |
| Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 84 | bootph-all; |
| Michal Simek | 52cc06a | 2019-04-11 10:35:37 +0200 | [diff] [blame] | 85 | reg = <0x50>; |
| 86 | }; |
| 87 | }; |
| 88 | }; |
| 89 | }; |