| Tom Rini | e33af1c | 2015-07-31 19:55:12 -0400 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_OMAP54XX=y | ||||
| Tom Rini | 44ccfe6 | 2015-09-17 16:47:05 -0400 | [diff] [blame] | 3 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
| Tom Rini | e33af1c | 2015-07-31 19:55:12 -0400 | [diff] [blame] | 4 | CONFIG_TARGET_DRA7XX_EVM=y |
| Tom Rini | 44ccfe6 | 2015-09-17 16:47:05 -0400 | [diff] [blame] | 5 | CONFIG_DM_SERIAL=y |
| Bin Meng | 63c1098 | 2015-09-28 05:14:15 -0700 | [diff] [blame] | 6 | CONFIG_DM_GPIO=y |
| Tom Rini | 44ccfe6 | 2015-09-17 16:47:05 -0400 | [diff] [blame] | 7 | CONFIG_SPL_STACK_R_ADDR=0x82000000 |
| Tom Rini | e33af1c | 2015-07-31 19:55:12 -0400 | [diff] [blame] | 8 | CONFIG_DEFAULT_DEVICE_TREE="dra72-evm" |
| 9 | CONFIG_SPL=y | ||||
| 10 | CONFIG_SPL_STACK_R=y | ||||
| Tom Rini | e33af1c | 2015-07-31 19:55:12 -0400 | [diff] [blame] | 11 | # CONFIG_CMD_IMLS is not set |
| 12 | # CONFIG_CMD_FLASH is not set | ||||
| Thomas Chou | 3a077cd | 2015-11-11 21:39:33 +0800 | [diff] [blame] | 13 | CONFIG_CMD_GPIO=y |
| Tom Rini | e33af1c | 2015-07-31 19:55:12 -0400 | [diff] [blame] | 14 | # CONFIG_CMD_SETEXPR is not set |
| 15 | # CONFIG_CMD_NFS is not set | ||||
| 16 | CONFIG_OF_CONTROL=y | ||||
| Tom Rini | e33af1c | 2015-07-31 19:55:12 -0400 | [diff] [blame] | 17 | CONFIG_DM=y |
| 18 | CONFIG_SPI_FLASH=y | ||||
| 19 | CONFIG_SPI_FLASH_BAR=y | ||||
| Bin Meng | 27f5b19 | 2015-11-25 05:34:54 -0800 | [diff] [blame] | 20 | CONFIG_SPI_FLASH_SPANSION=y |
| Thomas Chou | a6cec01 | 2015-11-19 21:48:14 +0800 | [diff] [blame] | 21 | CONFIG_SYS_NS16550=y |
| Bin Meng | 72a049d | 2015-11-25 05:34:53 -0800 | [diff] [blame] | 22 | CONFIG_TI_QSPI=y |
| Mugunthan V N | b2b71b8 | 2015-12-23 20:39:45 +0530 | [diff] [blame] | 23 | CONFIG_DM_SPI=y |
| 24 | CONFIG_DM_SPI_FLASH=y | ||||
| Mugunthan V N | 1612111 | 2015-12-24 16:08:20 +0530 | [diff] [blame] | 25 | CONFIG_TIMER=y |
| 26 | CONFIG_OMAP_TIMER=y | ||||