Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / a40f7825e10cf7bc40153dce2d468a091e5ae871 / . / arch / riscv / dts / fu740-c000-u-boot.dtsi
blob: 706224b384d22c1d74643e3cf73184df54e43cb5 [file] [log] [blame]
Green Wan06a3e402021-05-27 06:52:11 -0700[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * (C) Copyright 2020-2021 SiFive, Inc
4 */
5
6#include <dt-bindings/reset/sifive-fu740-prci.h>
7
8/ {
9 cpus {
Icenowy Zheng13d71702022-08-25 16:11:18 +0800[diff] [blame]10 assigned-clocks = <&prci FU740_PRCI_CLK_COREPLL>;
Green Wan06a3e402021-05-27 06:52:11 -0700[diff] [blame]11 assigned-clock-rates = <1200000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]12 bootph-pre-ram;
Green Wan06a3e402021-05-27 06:52:11 -0700[diff] [blame]13 cpu0: cpu@0 {
Icenowy Zheng13d71702022-08-25 16:11:18 +0800[diff] [blame]14 clocks = <&prci FU740_PRCI_CLK_COREPLL>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]15 bootph-pre-ram;
Green Wan06a3e402021-05-27 06:52:11 -0700[diff] [blame]16 status = "okay";
17 cpu0_intc: interrupt-controller {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]18 bootph-pre-ram;
Green Wan06a3e402021-05-27 06:52:11 -0700[diff] [blame]19 };
20 };
21 cpu1: cpu@1 {
Icenowy Zheng13d71702022-08-25 16:11:18 +0800[diff] [blame]22 clocks = <&prci FU740_PRCI_CLK_COREPLL>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]23 bootph-pre-ram;
Green Wan06a3e402021-05-27 06:52:11 -0700[diff] [blame]24 cpu1_intc: interrupt-controller {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]25 bootph-pre-ram;
Green Wan06a3e402021-05-27 06:52:11 -0700[diff] [blame]26 };
27 };
28 cpu2: cpu@2 {
Icenowy Zheng13d71702022-08-25 16:11:18 +0800[diff] [blame]29 clocks = <&prci FU740_PRCI_CLK_COREPLL>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]30 bootph-pre-ram;
Green Wan06a3e402021-05-27 06:52:11 -0700[diff] [blame]31 cpu2_intc: interrupt-controller {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]32 bootph-pre-ram;
Green Wan06a3e402021-05-27 06:52:11 -0700[diff] [blame]33 };
34 };
35 cpu3: cpu@3 {
Icenowy Zheng13d71702022-08-25 16:11:18 +0800[diff] [blame]36 clocks = <&prci FU740_PRCI_CLK_COREPLL>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]37 bootph-pre-ram;
Green Wan06a3e402021-05-27 06:52:11 -0700[diff] [blame]38 cpu3_intc: interrupt-controller {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]39 bootph-pre-ram;
Green Wan06a3e402021-05-27 06:52:11 -0700[diff] [blame]40 };
41 };
42 cpu4: cpu@4 {
Icenowy Zheng13d71702022-08-25 16:11:18 +0800[diff] [blame]43 clocks = <&prci FU740_PRCI_CLK_COREPLL>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]44 bootph-pre-ram;
Green Wan06a3e402021-05-27 06:52:11 -0700[diff] [blame]45 cpu4_intc: interrupt-controller {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]46 bootph-pre-ram;
Green Wan06a3e402021-05-27 06:52:11 -0700[diff] [blame]47 };
48 };
49 };
50
51 soc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]52 bootph-pre-ram;
Green Wan06a3e402021-05-27 06:52:11 -0700[diff] [blame]53 clint: clint@2000000 {
54 compatible = "riscv,clint0";
55 interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
56 &cpu1_intc 3 &cpu1_intc 7
57 &cpu2_intc 3 &cpu2_intc 7
58 &cpu3_intc 3 &cpu3_intc 7
59 &cpu4_intc 3 &cpu4_intc 7>;
60 reg = <0x0 0x2000000 0x0 0x10000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]61 bootph-pre-ram;
Green Wan06a3e402021-05-27 06:52:11 -0700[diff] [blame]62 };
63 prci: clock-controller@10000000 {
64 #reset-cells = <1>;
65 resets = <&prci PRCI_RST_DDR_CTRL_N>,
66 <&prci PRCI_RST_DDR_AXI_N>,
67 <&prci PRCI_RST_DDR_AHB_N>,
68 <&prci PRCI_RST_DDR_PHY_N>,
69 <&prci PRCI_RST_GEMGXL_N>,
70 <&prci PRCI_RST_CLTX_N>;
71 reset-names = "ddr_ctrl", "ddr_axi", "ddr_ahb",
72 "ddr_phy", "gemgxl_reset", "cltx_reset";
73 };
74 dmc: dmc@100b0000 {
75 compatible = "sifive,fu740-c000-ddr";
76 reg = <0x0 0x100b0000 0x0 0x0800
77 0x0 0x100b2000 0x0 0x2000
78 0x0 0x100b8000 0x0 0x1000>;
Icenowy Zheng13d71702022-08-25 16:11:18 +0800[diff] [blame]79 clocks = <&prci FU740_PRCI_CLK_DDRPLL>;
Green Wan06a3e402021-05-27 06:52:11 -0700[diff] [blame]80 clock-frequency = <933333324>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]81 bootph-pre-ram;
Green Wan06a3e402021-05-27 06:52:11 -0700[diff] [blame]82 };
83 };
84};
85
86&prci {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]87 bootph-pre-ram;
Green Wan06a3e402021-05-27 06:52:11 -0700[diff] [blame]88};
89
90&uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]91 bootph-pre-ram;
Green Wan06a3e402021-05-27 06:52:11 -0700[diff] [blame]92};
93
94&spi0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]95 bootph-pre-ram;
Green Wan06a3e402021-05-27 06:52:11 -0700[diff] [blame]96};
97
Zong Li9627a8e2021-06-30 23:23:47 +0800[diff] [blame]98&i2c0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]99 bootph-pre-ram;
Zong Li9627a8e2021-06-30 23:23:47 +0800[diff] [blame]100};
101
Green Wan06a3e402021-05-27 06:52:11 -0700[diff] [blame]102&eth0 {
Icenowy Zheng13d71702022-08-25 16:11:18 +0800[diff] [blame]103 assigned-clocks = <&prci FU740_PRCI_CLK_GEMGXLPLL>;
Green Wan06a3e402021-05-27 06:52:11 -0700[diff] [blame]104 assigned-clock-rates = <125125000>;
105};
106
107&ccache {
108 status = "okay";
109};