blob: 100191c6453ba3b6f69762654e7ef421bf87cd30 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -05001// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ben Ho <ben.ho@mediatek.com>
5 * Erin Lo <erin.lo@mediatek.com>
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/input.h>
10#include "mt8183.dtsi"
11#include "mt6358.dtsi"
12
13/ {
14 aliases {
15 serial0 = &uart0;
16 mmc0 = &mmc0;
17 mmc1 = &mmc1;
18 };
19
20 chosen {
21 stdout-path = "serial0:115200n8";
22 };
23
24 backlight_lcd0: backlight_lcd0 {
25 compatible = "pwm-backlight";
26 pwms = <&pwm0 0 500000>;
27 power-supply = <&bl_pp5000>;
28 enable-gpios = <&pio 176 0>;
29 brightness-levels = <0 1023>;
30 num-interpolated-steps = <1023>;
31 default-brightness-level = <576>;
32 status = "okay";
33 };
34
35 memory@40000000 {
36 device_type = "memory";
37 reg = <0 0x40000000 0 0x80000000>;
38 };
39
40 clk32k: oscillator1 {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <32768>;
44 clock-output-names = "clk32k";
45 };
46
47 it6505_pp18_reg: regulator0 {
48 compatible = "regulator-fixed";
49 regulator-name = "it6505_pp18";
50 regulator-min-microvolt = <1800000>;
51 regulator-max-microvolt = <1800000>;
52 gpio = <&pio 178 0>;
53 enable-active-high;
54 };
55
56 lcd_pp3300: regulator1 {
57 compatible = "regulator-fixed";
58 regulator-name = "lcd_pp3300";
59 regulator-min-microvolt = <3300000>;
60 regulator-max-microvolt = <3300000>;
61 regulator-always-on;
62 regulator-boot-on;
63 };
64
65 bl_pp5000: regulator2 {
66 compatible = "regulator-fixed";
67 regulator-name = "bl_pp5000";
68 regulator-min-microvolt = <5000000>;
69 regulator-max-microvolt = <5000000>;
70 regulator-always-on;
71 regulator-boot-on;
72 };
73
74 mmc1_fixed_power: regulator3 {
75 compatible = "regulator-fixed";
76 regulator-name = "mmc1_power";
77 regulator-min-microvolt = <3300000>;
78 regulator-max-microvolt = <3300000>;
79 };
80
81 mmc1_fixed_io: regulator4 {
82 compatible = "regulator-fixed";
83 regulator-name = "mmc1_io";
84 regulator-min-microvolt = <1800000>;
85 regulator-max-microvolt = <1800000>;
86 };
87
88 pp1800_alw: regulator5 {
89 compatible = "regulator-fixed";
90 regulator-name = "pp1800_alw";
91 regulator-always-on;
92 regulator-boot-on;
93 regulator-min-microvolt = <1800000>;
94 regulator-max-microvolt = <1800000>;
95 };
96
97 pp3300_alw: regulator6 {
98 compatible = "regulator-fixed";
99 regulator-name = "pp3300_alw";
100 regulator-always-on;
101 regulator-boot-on;
102 regulator-min-microvolt = <3300000>;
103 regulator-max-microvolt = <3300000>;
104 };
105
106 /* system wide semi-regulated power rail from charger */
107 reg_vsys: regulator-vsys {
108 compatible = "regulator-fixed";
109 regulator-name = "vsys";
110 regulator-always-on;
111 regulator-boot-on;
112 };
113
114 reserved_memory: reserved-memory {
115 #address-cells = <2>;
116 #size-cells = <2>;
117 ranges;
118
119 scp_mem_reserved: memory@50000000 {
120 compatible = "shared-dma-pool";
121 reg = <0 0x50000000 0 0x2900000>;
122 no-map;
123 };
124 };
125
126 sound: mt8183-sound {
127 mediatek,platform = <&afe>;
128 pinctrl-names = "default",
129 "aud_tdm_out_on",
130 "aud_tdm_out_off";
131 pinctrl-0 = <&aud_pins_default>;
132 pinctrl-1 = <&aud_pins_tdm_out_on>;
133 pinctrl-2 = <&aud_pins_tdm_out_off>;
134 status = "okay";
135 };
136
137 btsco: bt-sco {
138 compatible = "linux,bt-sco";
139 };
140
141 wifi_pwrseq: wifi-pwrseq {
142 compatible = "mmc-pwrseq-simple";
143 pinctrl-names = "default";
144 pinctrl-0 = <&wifi_pins_pwrseq>;
145
146 /* Toggle WIFI_ENABLE to reset the chip. */
147 reset-gpios = <&pio 119 1>;
148 };
149
150 wifi_wakeup: wifi-wakeup {
151 compatible = "gpio-keys";
152 pinctrl-names = "default";
153 pinctrl-0 = <&wifi_pins_wakeup>;
154
155 button-wowlan {
156 label = "Wake on WiFi";
157 gpios = <&pio 113 GPIO_ACTIVE_HIGH>;
158 linux,code = <KEY_WAKEUP>;
159 wakeup-source;
160 };
161 };
162
163 tboard_thermistor1: thermal-sensor1 {
164 compatible = "generic-adc-thermal";
165 #thermal-sensor-cells = <0>;
166 io-channels = <&auxadc 0>;
167 io-channel-names = "sensor-channel";
168 temperature-lookup-table = < (-5000) 1553
169 0 1488
170 5000 1412
171 10000 1326
172 15000 1232
173 20000 1132
174 25000 1029
175 30000 925
176 35000 823
177 40000 726
178 45000 635
179 50000 552
180 55000 478
181 60000 411
182 65000 353
183 70000 303
184 75000 260
185 80000 222
186 85000 190
187 90000 163
188 95000 140
189 100000 121
190 105000 104
191 110000 90
192 115000 78
193 120000 67
194 125000 59>;
195 };
196
197 tboard_thermistor2: thermal-sensor2 {
198 compatible = "generic-adc-thermal";
199 #thermal-sensor-cells = <0>;
200 io-channels = <&auxadc 1>;
201 io-channel-names = "sensor-channel";
202 temperature-lookup-table = < (-5000) 1553
203 0 1488
204 5000 1412
205 10000 1326
206 15000 1232
207 20000 1132
208 25000 1029
209 30000 925
210 35000 823
211 40000 726
212 45000 635
213 50000 552
214 55000 478
215 60000 411
216 65000 353
217 70000 303
218 75000 260
219 80000 222
220 85000 190
221 90000 163
222 95000 140
223 100000 121
224 105000 104
225 110000 90
226 115000 78
227 120000 67
228 125000 59>;
229 };
230};
231
232&auxadc {
233 status = "okay";
234};
235
236&cci {
237 proc-supply = <&mt6358_vproc12_reg>;
238};
239
240&cpu0 {
241 proc-supply = <&mt6358_vproc12_reg>;
242};
243
244&cpu1 {
245 proc-supply = <&mt6358_vproc12_reg>;
246};
247
248&cpu2 {
249 proc-supply = <&mt6358_vproc12_reg>;
250};
251
252&cpu3 {
253 proc-supply = <&mt6358_vproc12_reg>;
254};
255
256&cpu4 {
257 proc-supply = <&mt6358_vproc11_reg>;
258};
259
260&cpu5 {
261 proc-supply = <&mt6358_vproc11_reg>;
262};
263
264&cpu6 {
265 proc-supply = <&mt6358_vproc11_reg>;
266};
267
268&cpu7 {
269 proc-supply = <&mt6358_vproc11_reg>;
270};
271
272&dsi0 {
273 status = "okay";
274 #address-cells = <1>;
275 #size-cells = <0>;
276 panel: panel@0 {
277 /* compatible will be set in board dts */
278 reg = <0>;
279 enable-gpios = <&pio 45 0>;
280 pinctrl-names = "default";
281 pinctrl-0 = <&panel_pins_default>;
282 avdd-supply = <&ppvarn_lcd>;
283 avee-supply = <&ppvarp_lcd>;
284 pp1800-supply = <&pp1800_lcd>;
285 backlight = <&backlight_lcd0>;
286 rotation = <270>;
287 port {
288 panel_in: endpoint {
289 remote-endpoint = <&dsi_out>;
290 };
291 };
292 };
293
294 ports {
295 port {
296 dsi_out: endpoint {
297 remote-endpoint = <&panel_in>;
298 };
299 };
300 };
301};
302
303&gic {
304 mediatek,broken-save-restore-fw;
305};
306
307&gpu {
308 mali-supply = <&mt6358_vgpu_reg>;
309};
310
311&i2c0 {
312 pinctrl-names = "default";
313 pinctrl-0 = <&i2c0_pins>;
314 status = "okay";
315 clock-frequency = <400000>;
316 #address-cells = <1>;
317 #size-cells = <0>;
318};
319
320&i2c1 {
321 pinctrl-names = "default";
322 pinctrl-0 = <&i2c1_pins>;
323 status = "okay";
324 clock-frequency = <100000>;
325};
326
327&i2c3 {
328 pinctrl-names = "default";
329 pinctrl-0 = <&i2c3_pins>;
330 status = "okay";
331 clock-frequency = <100000>;
332 #address-cells = <1>;
333 #size-cells = <0>;
334};
335
336&i2c5 {
337 pinctrl-names = "default";
338 pinctrl-0 = <&i2c5_pins>;
339 status = "okay";
340 clock-frequency = <100000>;
341 #address-cells = <1>;
342 #size-cells = <0>;
343};
344
345&i2c6 {
346 pinctrl-names = "default";
347 pinctrl-0 = <&i2c6_pins>;
348 status = "okay";
349 clock-frequency = <100000>;
350};
351
352&mipi_tx0 {
353 status = "okay";
354};
355
356&mmc0 {
357 status = "okay";
358 pinctrl-names = "default", "state_uhs";
359 pinctrl-0 = <&mmc0_pins_default>;
360 pinctrl-1 = <&mmc0_pins_uhs>;
361 bus-width = <8>;
362 max-frequency = <200000000>;
363 cap-mmc-highspeed;
364 mmc-hs200-1_8v;
365 mmc-hs400-1_8v;
366 cap-mmc-hw-reset;
367 no-sdio;
368 no-sd;
369 hs400-ds-delay = <0x12814>;
370 vmmc-supply = <&mt6358_vemc_reg>;
371 vqmmc-supply = <&mt6358_vio18_reg>;
372 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
373 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>;
374 non-removable;
375};
376
377&mmc1 {
378 status = "okay";
379 pinctrl-names = "default", "state_uhs";
380 pinctrl-0 = <&mmc1_pins_default>;
381 pinctrl-1 = <&mmc1_pins_uhs>;
382 vmmc-supply = <&mmc1_fixed_power>;
383 vqmmc-supply = <&mmc1_fixed_io>;
384 mmc-pwrseq = <&wifi_pwrseq>;
385 bus-width = <4>;
386 max-frequency = <200000000>;
387 cap-sd-highspeed;
388 sd-uhs-sdr50;
389 sd-uhs-sdr104;
390 keep-power-in-suspend;
391 wakeup-source;
392 cap-sdio-irq;
393 non-removable;
394 no-mmc;
395 no-sd;
396 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>;
397 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
398 #address-cells = <1>;
399 #size-cells = <0>;
400
401 qca_wifi: qca-wifi@1 {
402 compatible = "qcom,ath10k";
403 reg = <1>;
404 };
405};
406
407&mt6358_vdram2_reg {
408 regulator-always-on;
409};
410
411&mt6358codec {
412 Avdd-supply = <&mt6358_vaud28_reg>;
413};
414
415&mt6358regulator {
416 vsys-ldo1-supply = <&reg_vsys>;
417 vsys-ldo2-supply = <&reg_vsys>;
418 vsys-ldo3-supply = <&reg_vsys>;
419 vsys-vcore-supply = <&reg_vsys>;
420 vsys-vdram1-supply = <&reg_vsys>;
421 vsys-vgpu-supply = <&reg_vsys>;
422 vsys-vmodem-supply = <&reg_vsys>;
423 vsys-vpa-supply = <&reg_vsys>;
424 vsys-vproc11-supply = <&reg_vsys>;
425 vsys-vproc12-supply = <&reg_vsys>;
426 vsys-vs1-supply = <&reg_vsys>;
427 vsys-vs2-supply = <&reg_vsys>;
428 vs1-ldo1-supply = <&mt6358_vs1_reg>;
429 vs2-ldo1-supply = <&mt6358_vdram1_reg>;
430 vs2-ldo2-supply = <&mt6358_vs2_reg>;
431 vs2-ldo3-supply = <&mt6358_vs2_reg>;
432 vs2-ldo4-supply = <&mt6358_vs2_reg>;
433};
434
435&mt6358_vgpu_reg {
Tom Rini53633a82024-02-29 12:33:36 -0500436 regulator-max-microvolt = <900000>;
437
438 regulator-coupled-with = <&mt6358_vsram_gpu_reg>;
439 regulator-coupled-max-spread = <100000>;
440};
441
442&mt6358_vsim1_reg {
443 regulator-min-microvolt = <2700000>;
444 regulator-max-microvolt = <2700000>;
445};
446
447&mt6358_vsim2_reg {
448 regulator-min-microvolt = <2700000>;
449 regulator-max-microvolt = <2700000>;
450};
451
452&mt6358_vsram_gpu_reg {
453 regulator-min-microvolt = <850000>;
454 regulator-max-microvolt = <1000000>;
455
456 regulator-coupled-with = <&mt6358_vgpu_reg>;
457 regulator-coupled-max-spread = <100000>;
458};
459
460&pio {
461 aud_pins_default: audiopins {
462 pins-bus {
463 pinmux = <PINMUX_GPIO97__FUNC_I2S2_MCK>,
464 <PINMUX_GPIO98__FUNC_I2S2_BCK>,
465 <PINMUX_GPIO101__FUNC_I2S2_LRCK>,
466 <PINMUX_GPIO102__FUNC_I2S2_DI>,
467 <PINMUX_GPIO3__FUNC_I2S3_DO>, /*i2s to da7219/max98357*/
468 <PINMUX_GPIO89__FUNC_I2S5_BCK>,
469 <PINMUX_GPIO90__FUNC_I2S5_LRCK>,
470 <PINMUX_GPIO91__FUNC_I2S5_DO>,
471 <PINMUX_GPIO174__FUNC_I2S0_DI>, /*i2s to wifi/bt*/
472 <PINMUX_GPIO136__FUNC_AUD_CLK_MOSI>,
473 <PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI>,
474 <PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0>,
475 <PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1>,
476 <PINMUX_GPIO140__FUNC_AUD_CLK_MISO>,
477 <PINMUX_GPIO141__FUNC_AUD_SYNC_MISO>,
478 <PINMUX_GPIO142__FUNC_AUD_DAT_MISO0>,
479 <PINMUX_GPIO143__FUNC_AUD_DAT_MISO1>; /*mtkaif3.0*/
480 };
481 };
482
483 aud_pins_tdm_out_on: audiotdmouton {
484 pins-bus {
485 pinmux = <PINMUX_GPIO169__FUNC_TDM_BCK_2ND>,
486 <PINMUX_GPIO170__FUNC_TDM_LRCK_2ND>,
487 <PINMUX_GPIO171__FUNC_TDM_DATA0_2ND>,
488 <PINMUX_GPIO172__FUNC_TDM_DATA1_2ND>,
489 <PINMUX_GPIO173__FUNC_TDM_DATA2_2ND>,
490 <PINMUX_GPIO10__FUNC_TDM_DATA3>; /*8ch-i2s to it6505*/
491 drive-strength = <MTK_DRIVE_6mA>;
492 };
493 };
494
495 aud_pins_tdm_out_off: audiotdmoutoff {
496 pins-bus {
497 pinmux = <PINMUX_GPIO169__FUNC_GPIO169>,
498 <PINMUX_GPIO170__FUNC_GPIO170>,
499 <PINMUX_GPIO171__FUNC_GPIO171>,
500 <PINMUX_GPIO172__FUNC_GPIO172>,
501 <PINMUX_GPIO173__FUNC_GPIO173>,
502 <PINMUX_GPIO10__FUNC_GPIO10>;
503 input-enable;
504 bias-pull-down;
505 drive-strength = <MTK_DRIVE_2mA>;
506 };
507 };
508
509 bt_pins: bt-pins {
510 pins-bt-en {
511 pinmux = <PINMUX_GPIO120__FUNC_GPIO120>;
512 output-low;
513 };
514 };
515
516 ec_ap_int_odl: ec-ap-int-odl {
517 pins1 {
518 pinmux = <PINMUX_GPIO151__FUNC_GPIO151>;
519 input-enable;
520 bias-pull-up;
521 };
522 };
523
524 h1_int_od_l: h1-int-od-l {
525 pins1 {
526 pinmux = <PINMUX_GPIO153__FUNC_GPIO153>;
527 input-enable;
528 };
529 };
530
531 i2c0_pins: i2c0 {
532 pins-bus {
533 pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
534 <PINMUX_GPIO83__FUNC_SCL0>;
535 mediatek,pull-up-adv = <3>;
536 mediatek,drive-strength-adv = <00>;
537 };
538 };
539
540 i2c1_pins: i2c1 {
541 pins-bus {
542 pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
543 <PINMUX_GPIO84__FUNC_SCL1>;
544 mediatek,pull-up-adv = <3>;
545 mediatek,drive-strength-adv = <00>;
546 };
547 };
548
549 i2c2_pins: i2c2 {
550 pins-bus {
551 pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
552 <PINMUX_GPIO104__FUNC_SDA2>;
553 bias-disable;
554 mediatek,drive-strength-adv = <00>;
555 };
556 };
557
558 i2c3_pins: i2c3 {
559 pins-bus {
560 pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
561 <PINMUX_GPIO51__FUNC_SDA3>;
562 mediatek,pull-up-adv = <3>;
563 mediatek,drive-strength-adv = <00>;
564 };
565 };
566
567 i2c4_pins: i2c4 {
568 pins-bus {
569 pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
570 <PINMUX_GPIO106__FUNC_SDA4>;
571 bias-disable;
572 mediatek,drive-strength-adv = <00>;
573 };
574 };
575
576 i2c5_pins: i2c5 {
577 pins-bus {
578 pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
579 <PINMUX_GPIO49__FUNC_SDA5>;
580 mediatek,pull-up-adv = <3>;
581 mediatek,drive-strength-adv = <00>;
582 };
583 };
584
585 i2c6_pins: i2c6 {
586 pins-bus {
587 pinmux = <PINMUX_GPIO11__FUNC_SCL6>,
588 <PINMUX_GPIO12__FUNC_SDA6>;
589 bias-disable;
590 };
591 };
592
593 mmc0_pins_default: mmc0-pins-default {
594 pins-cmd-dat {
595 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
596 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
597 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
598 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
599 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
600 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
601 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
602 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
603 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
604 input-enable;
605 drive-strength = <MTK_DRIVE_14mA>;
606 mediatek,pull-up-adv = <01>;
607 };
608
609 pins-clk {
610 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
611 drive-strength = <MTK_DRIVE_14mA>;
612 mediatek,pull-down-adv = <10>;
613 };
614
615 pins-rst {
616 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
617 drive-strength = <MTK_DRIVE_14mA>;
618 mediatek,pull-down-adv = <01>;
619 };
620 };
621
622 mmc0_pins_uhs: mmc0-pins-uhs {
623 pins-cmd-dat {
624 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
625 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
626 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
627 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
628 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
629 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
630 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
631 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
632 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
633 input-enable;
634 drive-strength = <MTK_DRIVE_14mA>;
635 mediatek,pull-up-adv = <01>;
636 };
637
638 pins-clk {
639 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
640 drive-strength = <MTK_DRIVE_14mA>;
641 mediatek,pull-down-adv = <10>;
642 };
643
644 pins-ds {
645 pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
646 drive-strength = <MTK_DRIVE_14mA>;
647 mediatek,pull-down-adv = <10>;
648 };
649
650 pins-rst {
651 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
652 drive-strength = <MTK_DRIVE_14mA>;
653 mediatek,pull-up-adv = <01>;
654 };
655 };
656
657 mmc1_pins_default: mmc1-pins-default {
658 pins-cmd-dat {
659 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
660 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
661 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
662 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
663 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
664 input-enable;
665 mediatek,pull-up-adv = <10>;
666 };
667
668 pins-clk {
669 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
670 input-enable;
671 mediatek,pull-down-adv = <10>;
672 };
673 };
674
675 mmc1_pins_uhs: mmc1-pins-uhs {
676 pins-cmd-dat {
677 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
678 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
679 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
680 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
681 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
682 drive-strength = <MTK_DRIVE_6mA>;
683 input-enable;
684 mediatek,pull-up-adv = <10>;
685 };
686
687 pins-clk {
688 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
689 drive-strength = <MTK_DRIVE_8mA>;
690 mediatek,pull-down-adv = <10>;
691 input-enable;
692 };
693 };
694
695 panel_pins_default: panel-pins-default {
696 panel-reset {
697 pinmux = <PINMUX_GPIO45__FUNC_GPIO45>;
698 output-low;
699 bias-pull-up;
700 };
701 };
702
703 pwm0_pin_default: pwm0-pin-default {
704 pins1 {
705 pinmux = <PINMUX_GPIO176__FUNC_GPIO176>;
706 output-high;
707 bias-pull-up;
708 };
709 pins2 {
710 pinmux = <PINMUX_GPIO43__FUNC_DISP_PWM>;
711 };
712 };
713
714 scp_pins: scp {
715 pins-scp-uart {
716 pinmux = <PINMUX_GPIO110__FUNC_TP_URXD1_AO>,
717 <PINMUX_GPIO112__FUNC_TP_UTXD1_AO>;
718 };
719 };
720
721 spi0_pins: spi0 {
722 pins-spi {
723 pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
724 <PINMUX_GPIO86__FUNC_GPIO86>,
725 <PINMUX_GPIO87__FUNC_SPI0_MO>,
726 <PINMUX_GPIO88__FUNC_SPI0_CLK>;
727 bias-disable;
728 };
729 };
730
731 spi1_pins: spi1 {
732 pins-spi {
733 pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
734 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
735 <PINMUX_GPIO163__FUNC_SPI1_A_MO>,
736 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>;
737 bias-disable;
738 };
739 };
740
741 spi2_pins: spi2 {
742 pins-spi {
743 pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
744 <PINMUX_GPIO1__FUNC_SPI2_MO>,
745 <PINMUX_GPIO2__FUNC_SPI2_CLK>;
746 bias-disable;
747 };
748 pins-spi-mi {
749 pinmux = <PINMUX_GPIO94__FUNC_SPI2_MI>;
750 mediatek,pull-down-adv = <00>;
751 };
752 };
753
754 spi3_pins: spi3 {
755 pins-spi {
756 pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
757 <PINMUX_GPIO22__FUNC_SPI3_CSB>,
758 <PINMUX_GPIO23__FUNC_SPI3_MO>,
759 <PINMUX_GPIO24__FUNC_SPI3_CLK>;
760 bias-disable;
761 };
762 };
763
764 spi4_pins: spi4 {
765 pins-spi {
766 pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
767 <PINMUX_GPIO18__FUNC_SPI4_CSB>,
768 <PINMUX_GPIO19__FUNC_SPI4_MO>,
769 <PINMUX_GPIO20__FUNC_SPI4_CLK>;
770 bias-disable;
771 };
772 };
773
774 spi5_pins: spi5 {
775 pins-spi {
776 pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
777 <PINMUX_GPIO14__FUNC_SPI5_CSB>,
778 <PINMUX_GPIO15__FUNC_SPI5_MO>,
779 <PINMUX_GPIO16__FUNC_SPI5_CLK>;
780 bias-disable;
781 };
782 };
783
784 uart0_pins_default: uart0-pins-default {
785 pins-rx {
786 pinmux = <PINMUX_GPIO95__FUNC_URXD0>;
787 input-enable;
788 bias-pull-up;
789 };
790 pins-tx {
791 pinmux = <PINMUX_GPIO96__FUNC_UTXD0>;
792 };
793 };
794
795 uart1_pins_default: uart1-pins-default {
796 pins-rx {
797 pinmux = <PINMUX_GPIO121__FUNC_URXD1>;
798 input-enable;
799 bias-pull-up;
800 };
801 pins-tx {
802 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>;
803 };
804 pins-rts {
805 pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
806 output-enable;
807 };
808 pins-cts {
809 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
810 input-enable;
811 };
812 };
813
814 uart1_pins_sleep: uart1-pins-sleep {
815 pins-rx {
816 pinmux = <PINMUX_GPIO121__FUNC_GPIO121>;
817 input-enable;
818 bias-pull-up;
819 };
820 pins-tx {
821 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>;
822 };
823 pins-rts {
824 pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
825 output-enable;
826 };
827 pins-cts {
828 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
829 input-enable;
830 };
831 };
832
833 wifi_pins_pwrseq: wifi-pins-pwrseq {
834 pins-wifi-enable {
835 pinmux = <PINMUX_GPIO119__FUNC_GPIO119>;
836 output-low;
837 };
838 };
839
840 wifi_pins_wakeup: wifi-pins-wakeup {
841 pins-wifi-wakeup {
842 pinmux = <PINMUX_GPIO113__FUNC_GPIO113>;
843 input-enable;
844 };
845 };
846};
847
Tom Rini93743d22024-04-01 09:08:13 -0400848&pmic {
849 interrupts-extended = <&pio 182 IRQ_TYPE_LEVEL_HIGH>;
850};
851
Tom Rini53633a82024-02-29 12:33:36 -0500852&pwm0 {
853 status = "okay";
854 pinctrl-names = "default";
855 pinctrl-0 = <&pwm0_pin_default>;
856};
857
858&scp {
859 status = "okay";
860
861 firmware-name = "mediatek/mt8183/scp.img";
862 pinctrl-names = "default";
863 pinctrl-0 = <&scp_pins>;
864
865 cros-ec-rpmsg {
866 compatible = "google,cros-ec-rpmsg";
867 mediatek,rpmsg-name = "cros-ec-rpmsg";
868 };
869};
870
871&mfg_async {
872 domain-supply = <&mt6358_vsram_gpu_reg>;
873};
874
875&mfg {
876 domain-supply = <&mt6358_vgpu_reg>;
877};
878
879&soc_data {
880 status = "okay";
881};
882
883&spi0 {
884 pinctrl-names = "default";
885 pinctrl-0 = <&spi0_pins>;
886 mediatek,pad-select = <0>;
887 status = "okay";
888 cs-gpios = <&pio 86 GPIO_ACTIVE_LOW>;
889
Tom Rini93743d22024-04-01 09:08:13 -0400890 tpm@0 {
Tom Rini53633a82024-02-29 12:33:36 -0500891 compatible = "google,cr50";
892 reg = <0>;
893 spi-max-frequency = <1000000>;
894 pinctrl-names = "default";
895 pinctrl-0 = <&h1_int_od_l>;
Tom Rini93743d22024-04-01 09:08:13 -0400896 interrupts-extended = <&pio 153 IRQ_TYPE_EDGE_RISING>;
Tom Rini53633a82024-02-29 12:33:36 -0500897 };
898};
899
900&spi1 {
901 pinctrl-names = "default";
902 pinctrl-0 = <&spi1_pins>;
903 mediatek,pad-select = <0>;
904 status = "okay";
905
906 w25q64dw: flash@0 {
907 compatible = "winbond,w25q64dw", "jedec,spi-nor";
908 reg = <0>;
909 spi-max-frequency = <25000000>;
910 };
911};
912
913&spi2 {
914 pinctrl-names = "default";
915 pinctrl-0 = <&spi2_pins>;
916 mediatek,pad-select = <0>;
917 status = "okay";
918
919 cros_ec: cros-ec@0 {
920 compatible = "google,cros-ec-spi";
921 reg = <0>;
922 spi-max-frequency = <3000000>;
Tom Rini93743d22024-04-01 09:08:13 -0400923 interrupts-extended = <&pio 151 IRQ_TYPE_LEVEL_LOW>;
Tom Rini53633a82024-02-29 12:33:36 -0500924 pinctrl-names = "default";
925 pinctrl-0 = <&ec_ap_int_odl>;
Tom Rini6bb92fc2024-05-20 09:54:58 -0600926 wakeup-source;
Tom Rini53633a82024-02-29 12:33:36 -0500927
928 i2c_tunnel: i2c-tunnel {
929 compatible = "google,cros-ec-i2c-tunnel";
930 google,remote-bus = <1>;
931 #address-cells = <1>;
932 #size-cells = <0>;
933 };
934
935 usbc_extcon: extcon0 {
936 compatible = "google,extcon-usbc-cros-ec";
937 google,usb-port-id = <0>;
938 };
939
Tom Rini53633a82024-02-29 12:33:36 -0500940 typec {
941 compatible = "google,cros-ec-typec";
942 #address-cells = <1>;
943 #size-cells = <0>;
944
945 usb_c0: connector@0 {
946 compatible = "usb-c-connector";
947 reg = <0>;
948 power-role = "dual";
949 data-role = "host";
950 try-power-role = "sink";
951 };
952 };
953 };
954};
955
956&spi3 {
957 pinctrl-names = "default";
958 pinctrl-0 = <&spi3_pins>;
959 mediatek,pad-select = <0>;
960 status = "disabled";
961};
962
963&spi4 {
964 pinctrl-names = "default";
965 pinctrl-0 = <&spi4_pins>;
966 mediatek,pad-select = <0>;
967 status = "disabled";
968};
969
970&spi5 {
971 pinctrl-names = "default";
972 pinctrl-0 = <&spi5_pins>;
973 mediatek,pad-select = <0>;
974 status = "disabled";
975};
976
977&ssusb {
978 dr_mode = "host";
979 wakeup-source;
980 vusb33-supply = <&mt6358_vusb_reg>;
981 status = "okay";
982};
983
984&thermal_zones {
985 tboard1 {
986 polling-delay = <1000>; /* milliseconds */
987 polling-delay-passive = <0>; /* milliseconds */
988 thermal-sensors = <&tboard_thermistor1>;
989 };
990
991 tboard2 {
992 polling-delay = <1000>; /* milliseconds */
993 polling-delay-passive = <0>; /* milliseconds */
994 thermal-sensors = <&tboard_thermistor2>;
995 };
996};
997
998&u3phy {
999 status = "okay";
1000};
1001
1002&uart0 {
1003 pinctrl-names = "default";
1004 pinctrl-0 = <&uart0_pins_default>;
1005 status = "okay";
1006};
1007
1008&uart1 {
1009 pinctrl-names = "default", "sleep";
1010 pinctrl-0 = <&uart1_pins_default>;
1011 pinctrl-1 = <&uart1_pins_sleep>;
1012 status = "okay";
1013 /delete-property/ interrupts;
1014 interrupts-extended = <&sysirq GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>,
1015 <&pio 121 IRQ_TYPE_EDGE_FALLING>;
1016
1017 bluetooth: bluetooth {
1018 pinctrl-names = "default";
1019 pinctrl-0 = <&bt_pins>;
1020 status = "okay";
1021 compatible = "qcom,qca6174-bt";
1022 enable-gpios = <&pio 120 0>;
1023 clocks = <&clk32k>;
1024 firmware-name = "nvm_00440302_i2s.bin";
1025 };
1026};
1027
1028&usb_host {
1029 #address-cells = <1>;
1030 #size-cells = <0>;
1031 vusb33-supply = <&mt6358_vusb_reg>;
1032 status = "okay";
1033
1034 hub@1 {
1035 compatible = "usb5e3,610";
1036 reg = <1>;
1037 };
1038};
1039
1040#include <arm/cros-ec-sbs.dtsi>