| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /dts-v1/; |
| 3 | |
| 4 | #include <dt-bindings/input/gpio-keys.h> |
| 5 | #include <dt-bindings/input/input.h> |
| 6 | #include <dt-bindings/thermal/thermal.h> |
| 7 | |
| 8 | #include "tegra30.dtsi" |
| 9 | #include "tegra30-cpu-opp.dtsi" |
| 10 | #include "tegra30-cpu-opp-microvolt.dtsi" |
| 11 | #include "tegra30-asus-lvds-display.dtsi" |
| 12 | |
| 13 | / { |
| 14 | model = "Pegatron Chagall"; |
| 15 | compatible = "pegatron,chagall", "nvidia,tegra30"; |
| 16 | chassis-type = "tablet"; |
| 17 | |
| 18 | aliases { |
| 19 | mmc0 = &sdmmc4; /* eMMC */ |
| 20 | mmc1 = &sdmmc1; /* uSD slot */ |
| 21 | mmc2 = &sdmmc3; /* WiFi */ |
| 22 | |
| 23 | rtc0 = &pmic; |
| 24 | rtc1 = "/rtc@7000e000"; |
| 25 | |
| 26 | display0 = &lcd; |
| 27 | display1 = &hdmi; |
| 28 | |
| 29 | serial1 = &uartc; /* Bluetooth */ |
| 30 | serial2 = &uartb; /* GPS */ |
| 31 | }; |
| 32 | |
| 33 | /* |
| 34 | * The decompressor and also some bootloaders rely on a |
| 35 | * pre-existing /chosen node to be available to insert the |
| 36 | * command line and merge other ATAGS info. |
| 37 | */ |
| 38 | chosen {}; |
| 39 | |
| 40 | firmware { |
| 41 | trusted-foundations { |
| 42 | compatible = "tlm,trusted-foundations"; |
| 43 | tlm,version-major = <2>; |
| 44 | tlm,version-minor = <8>; |
| 45 | }; |
| 46 | }; |
| 47 | |
| 48 | memory@80000000 { |
| 49 | reg = <0x80000000 0x40000000>; |
| 50 | }; |
| 51 | |
| 52 | reserved-memory { |
| 53 | #address-cells = <1>; |
| 54 | #size-cells = <1>; |
| 55 | ranges; |
| 56 | |
| 57 | linux,cma@80000000 { |
| 58 | compatible = "shared-dma-pool"; |
| 59 | alloc-ranges = <0x80000000 0x30000000>; |
| 60 | size = <0x10000000>; /* 256MiB */ |
| 61 | linux,cma-default; |
| 62 | reusable; |
| 63 | }; |
| 64 | |
| 65 | ramoops@beb00000 { |
| 66 | compatible = "ramoops"; |
| 67 | reg = <0xbeb00000 0x10000>; /* 64kB */ |
| 68 | console-size = <0x8000>; /* 32kB */ |
| 69 | record-size = <0x400>; /* 1kB */ |
| 70 | ecc-size = <16>; |
| 71 | }; |
| 72 | |
| 73 | trustzone@bfe00000 { |
| 74 | reg = <0xbfe00000 0x200000>; /* 2MB */ |
| 75 | no-map; |
| 76 | }; |
| 77 | }; |
| 78 | |
| 79 | host1x@50000000 { |
| 80 | hdmi: hdmi@54280000 { |
| 81 | status = "okay"; |
| 82 | |
| 83 | hdmi-supply = <&hdmi_5v0_sys>; |
| 84 | pll-supply = <&vdd_1v8_vio>; |
| 85 | vdd-supply = <&vdd_3v3_sys>; |
| 86 | |
| 87 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; |
| 88 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; |
| 89 | }; |
| 90 | }; |
| 91 | |
| 92 | vde@6001a000 { |
| 93 | assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>; |
| 94 | assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>; |
| 95 | assigned-clock-rates = <408000000>; |
| 96 | }; |
| 97 | |
| 98 | pinmux@70000868 { |
| 99 | pinctrl-names = "default"; |
| 100 | pinctrl-0 = <&state_default>; |
| 101 | |
| 102 | state_default: pinmux { |
| 103 | /* SDMMC1 pinmux */ |
| 104 | sdmmc1_clk_pz0 { |
| 105 | nvidia,pins = "sdmmc1_clk_pz0"; |
| 106 | nvidia,function = "sdmmc1"; |
| 107 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 108 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 109 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 110 | }; |
| 111 | |
| 112 | sdmmc1_dat3_py4 { |
| 113 | nvidia,pins = "sdmmc1_dat3_py4", |
| 114 | "sdmmc1_dat2_py5", |
| 115 | "sdmmc1_dat1_py6", |
| 116 | "sdmmc1_dat0_py7", |
| 117 | "sdmmc1_cmd_pz1"; |
| 118 | nvidia,function = "sdmmc1"; |
| 119 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 120 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 121 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 122 | }; |
| 123 | |
| 124 | /* SDMMC2 pinmux */ |
| 125 | vi_d1_pd5 { |
| 126 | nvidia,pins = "vi_d1_pd5", |
| 127 | "vi_d2_pl0", |
| 128 | "vi_d3_pl1", |
| 129 | "vi_d5_pl3", |
| 130 | "vi_d7_pl5"; |
| 131 | nvidia,function = "sdmmc2"; |
| 132 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 133 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 134 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 135 | }; |
| 136 | |
| 137 | vi_d8_pl6 { |
| 138 | nvidia,pins = "vi_d8_pl6", |
| 139 | "vi_d9_pl7"; |
| 140 | nvidia,function = "sdmmc2"; |
| 141 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 142 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 143 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 144 | nvidia,lock = <0>; |
| 145 | nvidia,io-reset = <0>; |
| 146 | }; |
| 147 | |
| 148 | /* SDMMC3 pinmux */ |
| 149 | sdmmc3_clk_pa6 { |
| 150 | nvidia,pins = "sdmmc3_clk_pa6"; |
| 151 | nvidia,function = "sdmmc3"; |
| 152 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 153 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 154 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 155 | }; |
| 156 | |
| 157 | sdmmc3_cmd_pa7 { |
| 158 | nvidia,pins = "sdmmc3_cmd_pa7", |
| 159 | "sdmmc3_dat3_pb4", |
| 160 | "sdmmc3_dat2_pb5", |
| 161 | "sdmmc3_dat1_pb6", |
| 162 | "sdmmc3_dat0_pb7", |
| 163 | "sdmmc3_dat5_pd0", |
| 164 | "sdmmc3_dat4_pd1", |
| 165 | "sdmmc3_dat6_pd3", |
| 166 | "sdmmc3_dat7_pd4"; |
| 167 | nvidia,function = "sdmmc3"; |
| 168 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 169 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 170 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 171 | }; |
| 172 | |
| 173 | /* SDMMC4 pinmux */ |
| 174 | sdmmc4_clk_pcc4 { |
| 175 | nvidia,pins = "sdmmc4_clk_pcc4"; |
| 176 | nvidia,function = "sdmmc4"; |
| 177 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 178 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 179 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 180 | }; |
| 181 | |
| 182 | sdmmc4_cmd_pt7 { |
| 183 | nvidia,pins = "sdmmc4_cmd_pt7", |
| 184 | "sdmmc4_dat0_paa0", |
| 185 | "sdmmc4_dat1_paa1", |
| 186 | "sdmmc4_dat2_paa2", |
| 187 | "sdmmc4_dat3_paa3", |
| 188 | "sdmmc4_dat4_paa4", |
| 189 | "sdmmc4_dat5_paa5", |
| 190 | "sdmmc4_dat6_paa6", |
| 191 | "sdmmc4_dat7_paa7"; |
| 192 | nvidia,function = "sdmmc4"; |
| 193 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 194 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 195 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 196 | }; |
| 197 | |
| 198 | /* I2C pinmux */ |
| 199 | gen1_i2c_scl_pc4 { |
| 200 | nvidia,pins = "gen1_i2c_scl_pc4", |
| 201 | "gen1_i2c_sda_pc5"; |
| 202 | nvidia,function = "i2c1"; |
| 203 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 204 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 205 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 206 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 207 | nvidia,lock = <0>; |
| 208 | }; |
| 209 | |
| 210 | gen2_i2c_scl_pt5 { |
| 211 | nvidia,pins = "gen2_i2c_scl_pt5", |
| 212 | "gen2_i2c_sda_pt6"; |
| 213 | nvidia,function = "i2c2"; |
| 214 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 215 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 216 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 217 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 218 | nvidia,lock = <0>; |
| 219 | }; |
| 220 | |
| 221 | cam_i2c_scl_pbb1 { |
| 222 | nvidia,pins = "cam_i2c_scl_pbb1", |
| 223 | "cam_i2c_sda_pbb2"; |
| 224 | nvidia,function = "i2c3"; |
| 225 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 226 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 227 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 228 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 229 | nvidia,lock = <0>; |
| 230 | }; |
| 231 | |
| 232 | ddc_scl_pv4 { |
| 233 | nvidia,pins = "ddc_scl_pv4", |
| 234 | "ddc_sda_pv5"; |
| 235 | nvidia,function = "i2c4"; |
| 236 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 237 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 238 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 239 | nvidia,lock = <0>; |
| 240 | }; |
| 241 | |
| 242 | pwr_i2c_scl_pz6 { |
| 243 | nvidia,pins = "pwr_i2c_scl_pz6", |
| 244 | "pwr_i2c_sda_pz7"; |
| 245 | nvidia,function = "i2cpwr"; |
| 246 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 247 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 248 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 249 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 250 | nvidia,lock = <0>; |
| 251 | }; |
| 252 | |
| 253 | /* HDMI-CEC pinmux */ |
| 254 | hdmi_cec_pee3 { |
| 255 | nvidia,pins = "hdmi_cec_pee3"; |
| 256 | nvidia,function = "cec"; |
| 257 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 258 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 259 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 260 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 261 | nvidia,lock = <0>; |
| 262 | }; |
| 263 | |
| 264 | /* UART-A */ |
| 265 | ulpi_data0_po1 { |
| 266 | nvidia,pins = "ulpi_data0_po1"; |
| 267 | nvidia,function = "uarta"; |
| 268 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 269 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 270 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 271 | }; |
| 272 | |
| 273 | ulpi_data1_po2 { |
| 274 | nvidia,pins = "ulpi_data1_po2", |
| 275 | "ulpi_data2_po3", |
| 276 | "ulpi_data3_po4", |
| 277 | "ulpi_data4_po5", |
| 278 | "ulpi_data5_po6", |
| 279 | "ulpi_data6_po7"; |
| 280 | nvidia,function = "uarta"; |
| 281 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 282 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 283 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 284 | }; |
| 285 | |
| 286 | ulpi_data7_po0 { |
| 287 | nvidia,pins = "ulpi_data7_po0"; |
| 288 | nvidia,function = "uarta"; |
| 289 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 290 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 291 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 292 | }; |
| 293 | |
| 294 | /* UART-B */ |
| 295 | uart2_txd_pc2 { |
| 296 | nvidia,pins = "uart2_txd_pc2", |
| 297 | "uart2_rts_n_pj6"; |
| 298 | nvidia,function = "uartb"; |
| 299 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 300 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 301 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 302 | }; |
| 303 | |
| 304 | uart2_rxd_pc3 { |
| 305 | nvidia,pins = "uart2_rxd_pc3", |
| 306 | "uart2_cts_n_pj5"; |
| 307 | nvidia,function = "uartb"; |
| 308 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 309 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 310 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 311 | }; |
| 312 | |
| 313 | /* UART-C */ |
| 314 | uart3_cts_n_pa1 { |
| 315 | nvidia,pins = "uart3_cts_n_pa1", |
| 316 | "uart3_rxd_pw7"; |
| 317 | nvidia,function = "uartc"; |
| 318 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 319 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 320 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 321 | }; |
| 322 | |
| 323 | uart3_rts_n_pc0 { |
| 324 | nvidia,pins = "uart3_rts_n_pc0", |
| 325 | "uart3_txd_pw6"; |
| 326 | nvidia,function = "uartc"; |
| 327 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 328 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 329 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 330 | }; |
| 331 | |
| 332 | /* UART-D */ |
| 333 | ulpi_clk_py0 { |
| 334 | nvidia,pins = "ulpi_clk_py0", |
| 335 | "ulpi_stp_py3"; |
| 336 | nvidia,function = "uartd"; |
| 337 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 338 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 339 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 340 | }; |
| 341 | |
| 342 | ulpi_dir_py1 { |
| 343 | nvidia,pins = "ulpi_dir_py1", |
| 344 | "ulpi_nxt_py2"; |
| 345 | nvidia,function = "uartd"; |
| 346 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 347 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 348 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 349 | }; |
| 350 | |
| 351 | /* I2S pinmux */ |
| 352 | dap1_fs_pn0 { |
| 353 | nvidia,pins = "dap1_fs_pn0", |
| 354 | "dap1_din_pn1", |
| 355 | "dap1_dout_pn2", |
| 356 | "dap1_sclk_pn3"; |
| 357 | nvidia,function = "i2s0"; |
| 358 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 359 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 360 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 361 | }; |
| 362 | |
| 363 | dap2_fs_pa2 { |
| 364 | nvidia,pins = "dap2_fs_pa2", |
| 365 | "dap2_sclk_pa3", |
| 366 | "dap2_din_pa4", |
| 367 | "dap2_dout_pa5"; |
| 368 | nvidia,function = "i2s1"; |
| 369 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 370 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 371 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 372 | }; |
| 373 | |
| 374 | dap3_fs_pp0 { |
| 375 | nvidia,pins = "dap3_fs_pp0", |
| 376 | "dap3_din_pp1", |
| 377 | "dap3_dout_pp2", |
| 378 | "dap3_sclk_pp3"; |
| 379 | nvidia,function = "i2s2"; |
| 380 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 381 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 382 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 383 | }; |
| 384 | |
| 385 | dap4_fs_pp4 { |
| 386 | nvidia,pins = "dap4_fs_pp4", |
| 387 | "dap4_din_pp5", |
| 388 | "dap4_dout_pp6", |
| 389 | "dap4_sclk_pp7"; |
| 390 | nvidia,function = "i2s3"; |
| 391 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 392 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 393 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 394 | }; |
| 395 | |
| 396 | pcc2 { |
| 397 | nvidia,pins = "pcc2"; |
| 398 | nvidia,function = "i2s4"; |
| 399 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 400 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 401 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 402 | }; |
| 403 | |
| 404 | /* PCI-e pinmux */ |
| 405 | pex_l2_rst_n_pcc6 { |
| 406 | nvidia,pins = "pex_l2_rst_n_pcc6", |
| 407 | "pex_l0_rst_n_pdd1", |
| 408 | "pex_l1_rst_n_pdd5"; |
| 409 | nvidia,function = "pcie"; |
| 410 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 411 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 412 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 413 | }; |
| 414 | |
| 415 | pex_l2_clkreq_n_pcc7 { |
| 416 | nvidia,pins = "pex_l2_clkreq_n_pcc7", |
| 417 | "pex_l0_prsnt_n_pdd0", |
| 418 | "pex_l0_clkreq_n_pdd2", |
| 419 | "pex_l2_prsnt_n_pdd7"; |
| 420 | nvidia,function = "pcie"; |
| 421 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 422 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 423 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 424 | }; |
| 425 | |
| 426 | pex_wake_n_pdd3 { |
| 427 | nvidia,pins = "pex_wake_n_pdd3"; |
| 428 | nvidia,function = "pcie"; |
| 429 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 430 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 431 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 432 | }; |
| 433 | |
| 434 | /* SPI pinmux */ |
| 435 | spi1_mosi_px4 { |
| 436 | nvidia,pins = "spi1_mosi_px4", |
| 437 | "spi1_sck_px5", |
| 438 | "spi1_cs0_n_px6", |
| 439 | "spi1_miso_px7"; |
| 440 | nvidia,function = "spi1"; |
| 441 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 442 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 443 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 444 | }; |
| 445 | |
| 446 | spi2_cs1_n_pw2 { |
| 447 | nvidia,pins = "spi2_cs1_n_pw2", |
| 448 | "spi2_cs2_n_pw3"; |
| 449 | nvidia,function = "spi2"; |
| 450 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 451 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 452 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 453 | }; |
| 454 | |
| 455 | spi2_sck_px2 { |
| 456 | nvidia,pins = "spi2_sck_px2"; |
| 457 | nvidia,function = "gmi"; |
| 458 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 459 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 460 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 461 | }; |
| 462 | |
| 463 | gmi_a16_pj7 { |
| 464 | nvidia,pins = "gmi_a16_pj7", |
| 465 | "gmi_a19_pk7"; |
| 466 | nvidia,function = "spi4"; |
| 467 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 468 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 469 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 470 | }; |
| 471 | |
| 472 | gmi_a17_pb0 { |
| 473 | nvidia,pins = "gmi_a17_pb0", |
| 474 | "gmi_a18_pb1"; |
| 475 | nvidia,function = "spi4"; |
| 476 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 477 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 478 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 479 | }; |
| 480 | |
| 481 | spi2_mosi_px0 { |
| 482 | nvidia,pins = "spi2_mosi_px0"; |
| 483 | nvidia,function = "spi6"; |
| 484 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 485 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 486 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 487 | }; |
| 488 | |
| 489 | spdif_out_pk5 { |
| 490 | nvidia,pins = "spdif_out_pk5"; |
| 491 | nvidia,function = "spdif"; |
| 492 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 493 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 494 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 495 | }; |
| 496 | |
| 497 | spdif_in_pk6 { |
| 498 | nvidia,pins = "spdif_in_pk6"; |
| 499 | nvidia,function = "spdif"; |
| 500 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 501 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 502 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 503 | }; |
| 504 | |
| 505 | /* Display A pinmux */ |
| 506 | lcd_pwr0_pb2 { |
| 507 | nvidia,pins = "lcd_pwr0_pb2", |
| 508 | "lcd_pclk_pb3", |
| 509 | "lcd_pwr1_pc1", |
| 510 | "lcd_pwr2_pc6", |
| 511 | "lcd_d0_pe0", |
| 512 | "lcd_d1_pe1", |
| 513 | "lcd_d2_pe2", |
| 514 | "lcd_d3_pe3", |
| 515 | "lcd_d4_pe4", |
| 516 | "lcd_d5_pe5", |
| 517 | "lcd_d6_pe6", |
| 518 | "lcd_d7_pe7", |
| 519 | "lcd_d8_pf0", |
| 520 | "lcd_d9_pf1", |
| 521 | "lcd_d10_pf2", |
| 522 | "lcd_d11_pf3", |
| 523 | "lcd_d12_pf4", |
| 524 | "lcd_d13_pf5", |
| 525 | "lcd_d14_pf6", |
| 526 | "lcd_d15_pf7", |
| 527 | "lcd_de_pj1", |
| 528 | "lcd_hsync_pj3", |
| 529 | "lcd_vsync_pj4", |
| 530 | "lcd_d16_pm0", |
| 531 | "lcd_d17_pm1", |
| 532 | "lcd_d18_pm2", |
| 533 | "lcd_d19_pm3", |
| 534 | "lcd_d20_pm4", |
| 535 | "lcd_d21_pm5", |
| 536 | "lcd_d22_pm6", |
| 537 | "lcd_d23_pm7", |
| 538 | "lcd_cs0_n_pn4", |
| 539 | "lcd_sdout_pn5", |
| 540 | "lcd_dc0_pn6", |
| 541 | "lcd_sdin_pz2", |
| 542 | "lcd_wr_n_pz3", |
| 543 | "lcd_sck_pz4", |
| 544 | "lcd_cs1_n_pw0", |
| 545 | "lcd_m1_pw1"; |
| 546 | nvidia,function = "displaya"; |
| 547 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 548 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 549 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 550 | }; |
| 551 | |
| 552 | lcd_dc1_pd2 { |
| 553 | nvidia,pins = "lcd_dc1_pd2"; |
| 554 | nvidia,function = "displaya"; |
| 555 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 556 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 557 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 558 | }; |
| 559 | |
| 560 | clk_32k_out_pa0 { |
| 561 | nvidia,pins = "clk_32k_out_pa0"; |
| 562 | nvidia,function = "blink"; |
| 563 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 564 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 565 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 566 | }; |
| 567 | |
| 568 | /* KBC keys */ |
| 569 | kb_row0_pr0 { |
| 570 | nvidia,pins = "kb_row0_pr0", |
| 571 | "kb_row1_pr1", |
| 572 | "kb_row2_pr2", |
| 573 | "kb_row3_pr3", |
| 574 | "kb_row8_ps0", |
| 575 | "kb_col0_pq0", |
| 576 | "kb_col1_pq1", |
| 577 | "kb_col2_pq2", |
| 578 | "kb_col3_pq3", |
| 579 | "kb_col4_pq4", |
| 580 | "kb_col5_pq5", |
| 581 | "kb_col7_pq7"; |
| 582 | nvidia,function = "kbc"; |
| 583 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 584 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 585 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 586 | }; |
| 587 | |
| 588 | kb_row4_pr4 { |
| 589 | nvidia,pins = "kb_row4_pr4", |
| 590 | "kb_row7_pr7", |
| 591 | "kb_row10_ps2", |
| 592 | "kb_row13_ps5"; |
| 593 | nvidia,function = "kbc"; |
| 594 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 595 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 596 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 597 | }; |
| 598 | |
| 599 | kb_row11_ps3 { |
| 600 | nvidia,pins = "kb_row11_ps3", |
| 601 | "kb_row12_ps4", |
| 602 | "kb_row15_ps7"; |
| 603 | nvidia,function = "kbc"; |
| 604 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 605 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 606 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 607 | }; |
| 608 | |
| 609 | kb_row14_ps6 { |
| 610 | nvidia,pins = "kb_row14_ps6"; |
| 611 | nvidia,function = "kbc"; |
| 612 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 613 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 614 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 615 | }; |
| 616 | |
| 617 | gmi_iordy_pi5 { |
| 618 | nvidia,pins = "gmi_iordy_pi5"; |
| 619 | nvidia,function = "rsvd1"; |
| 620 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 621 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 622 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 623 | }; |
| 624 | |
| 625 | vi_pclk_pt0 { |
| 626 | nvidia,pins = "vi_pclk_pt0"; |
| 627 | nvidia,function = "rsvd1"; |
| 628 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 629 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 630 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 631 | nvidia,lock = <0>; |
| 632 | nvidia,io-reset = <0>; |
| 633 | }; |
| 634 | |
| 635 | pu1 { |
| 636 | nvidia,pins = "pu1"; |
| 637 | nvidia,function = "rsvd1"; |
| 638 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 639 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 640 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 641 | }; |
| 642 | |
| 643 | pu2 { |
| 644 | nvidia,pins = "pu2"; |
| 645 | nvidia,function = "rsvd1"; |
| 646 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 647 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 648 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 649 | }; |
| 650 | |
| 651 | pv0 { |
| 652 | nvidia,pins = "pv0"; |
| 653 | nvidia,function = "rsvd1"; |
| 654 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 655 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 656 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 657 | }; |
| 658 | |
| 659 | pv1 { |
| 660 | nvidia,pins = "pv1"; |
| 661 | nvidia,function = "rsvd1"; |
| 662 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 663 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 664 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 665 | }; |
| 666 | |
| 667 | pcc1 { |
| 668 | nvidia,pins = "pcc1"; |
| 669 | nvidia,function = "rsvd2"; |
| 670 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 671 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 672 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 673 | }; |
| 674 | |
| 675 | sdmmc4_rst_n_pcc3 { |
| 676 | nvidia,pins = "sdmmc4_rst_n_pcc3"; |
| 677 | nvidia,function = "rsvd2"; |
| 678 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 679 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 680 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 681 | }; |
| 682 | |
| 683 | pv3 { |
| 684 | nvidia,pins = "pv3"; |
| 685 | nvidia,function = "rsvd2"; |
| 686 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 687 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 688 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 689 | }; |
| 690 | |
| 691 | vi_vsync_pd6 { |
| 692 | nvidia,pins = "vi_vsync_pd6", |
| 693 | "vi_hsync_pd7"; |
| 694 | nvidia,function = "rsvd2"; |
| 695 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 696 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 697 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 698 | nvidia,lock = <0>; |
| 699 | nvidia,io-reset = <0>; |
| 700 | }; |
| 701 | |
| 702 | vi_d10_pt2 { |
| 703 | nvidia,pins = "vi_d10_pt2", |
| 704 | "vi_d0_pt4", "pbb0"; |
| 705 | nvidia,function = "rsvd2"; |
| 706 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 707 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 708 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 709 | }; |
| 710 | |
| 711 | vi_d11_pt3 { |
| 712 | nvidia,pins = "vi_d11_pt3"; |
| 713 | nvidia,function = "rsvd2"; |
| 714 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 715 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 716 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 717 | }; |
| 718 | |
| 719 | pu0 { |
| 720 | nvidia,pins = "pu0"; |
| 721 | nvidia,function = "rsvd4"; |
| 722 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 723 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 724 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 725 | }; |
| 726 | |
| 727 | pu3 { |
| 728 | nvidia,pins = "pu3"; |
| 729 | nvidia,function = "rsvd4"; |
| 730 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 731 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 732 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 733 | }; |
| 734 | |
| 735 | pu6 { |
| 736 | nvidia,pins = "pu6"; |
| 737 | nvidia,function = "rsvd4"; |
| 738 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 739 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 740 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 741 | }; |
| 742 | |
| 743 | pex_l1_prsnt_n_pdd4 { |
| 744 | nvidia,pins = "pex_l1_prsnt_n_pdd4", |
| 745 | "pex_l1_clkreq_n_pdd6"; |
| 746 | nvidia,function = "rsvd4"; |
| 747 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 748 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 749 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 750 | }; |
| 751 | |
| 752 | gmi_wait_pi7 { |
| 753 | nvidia,pins = "gmi_wait_pi7", |
| 754 | "gmi_cs0_n_pj0", |
| 755 | "gmi_cs1_n_pj2", |
| 756 | "gmi_cs4_n_pk2"; |
| 757 | nvidia,function = "nand"; |
| 758 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 759 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 760 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 761 | }; |
| 762 | |
| 763 | gmi_ad0_pg0 { |
| 764 | nvidia,pins = "gmi_ad0_pg0", |
| 765 | "gmi_ad1_pg1", |
| 766 | "gmi_ad2_pg2", |
| 767 | "gmi_ad3_pg3", |
| 768 | "gmi_ad4_pg4", |
| 769 | "gmi_ad5_pg5", |
| 770 | "gmi_ad6_pg6", |
| 771 | "gmi_ad7_pg7", |
| 772 | "gmi_wr_n_pi0", |
| 773 | "gmi_oe_n_pi1", |
| 774 | "gmi_dqs_pi2", |
| 775 | "gmi_adv_n_pk0", |
| 776 | "gmi_clk_pk1"; |
| 777 | nvidia,function = "nand"; |
| 778 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 779 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 780 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 781 | }; |
| 782 | |
| 783 | gmi_cs2_n_pk3 { |
| 784 | nvidia,pins = "gmi_cs2_n_pk3"; |
| 785 | nvidia,function = "rsvd1"; |
| 786 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 787 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 788 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 789 | }; |
| 790 | |
| 791 | gmi_cs3_n_pk4 { |
| 792 | nvidia,pins = "gmi_cs3_n_pk4"; |
| 793 | nvidia,function = "nand"; |
| 794 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 795 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 796 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 797 | }; |
| 798 | |
| 799 | gmi_ad10_ph2 { |
| 800 | nvidia,pins = "gmi_ad10_ph2", |
| 801 | "gmi_ad11_ph3", |
| 802 | "gmi_ad14_ph6"; |
| 803 | nvidia,function = "nand"; |
| 804 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 805 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 806 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 807 | }; |
| 808 | |
| 809 | gmi_ad13_ph5 { |
| 810 | nvidia,pins = "gmi_ad13_ph5", |
| 811 | "gmi_ad12_ph4", |
| 812 | "gmi_cs7_n_pi6"; |
| 813 | nvidia,function = "nand"; |
| 814 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 815 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 816 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 817 | }; |
| 818 | |
| 819 | gmi_rst_n_pi4 { |
| 820 | nvidia,pins = "gmi_rst_n_pi4"; |
| 821 | nvidia,function = "gmi"; |
| 822 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 823 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 824 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 825 | }; |
| 826 | |
| 827 | gmi_ad8_ph0 { |
| 828 | nvidia,pins = "gmi_ad8_ph0"; |
| 829 | nvidia,function = "pwm0"; |
| 830 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 831 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 832 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 833 | }; |
| 834 | |
| 835 | gmi_ad9_ph1 { |
| 836 | nvidia,pins = "gmi_ad9_ph1"; |
| 837 | nvidia,function = "pwm1"; |
| 838 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 839 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 840 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 841 | }; |
| 842 | |
| 843 | gmi_wp_n_pc7 { |
| 844 | nvidia,pins = "gmi_wp_n_pc7"; |
| 845 | nvidia,function = "gmi"; |
| 846 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 847 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 848 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 849 | }; |
| 850 | |
| 851 | gmi_cs6_n_pi3 { |
| 852 | nvidia,pins = "gmi_cs6_n_pi3"; |
| 853 | nvidia,function = "sata"; |
| 854 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 855 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 856 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 857 | }; |
| 858 | |
| 859 | vi_d4_pl2 { |
| 860 | nvidia,pins = "vi_d4_pl2"; |
| 861 | nvidia,function = "vi"; |
| 862 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 863 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 864 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 865 | }; |
| 866 | |
| 867 | vi_d6_pl4 { |
| 868 | nvidia,pins = "vi_d6_pl4"; |
| 869 | nvidia,function = "vi"; |
| 870 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 871 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 872 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 873 | nvidia,lock = <0>; |
| 874 | nvidia,io-reset = <0>; |
| 875 | }; |
| 876 | |
| 877 | vi_mclk_pt1 { |
| 878 | nvidia,pins = "vi_mclk_pt1"; |
| 879 | nvidia,function = "vi"; |
| 880 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 881 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 882 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 883 | }; |
| 884 | |
| 885 | /* HDMI hot-plug-detect */ |
| 886 | hdmi_int_pn7 { |
| 887 | nvidia,pins = "hdmi_int_pn7"; |
| 888 | nvidia,function = "hdmi"; |
| 889 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 890 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 891 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 892 | }; |
| 893 | |
| 894 | pu4 { |
| 895 | nvidia,pins = "pu4"; |
| 896 | nvidia,function = "pwm1"; |
| 897 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 898 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 899 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 900 | }; |
| 901 | |
| 902 | pu5 { |
| 903 | nvidia,pins = "pu5"; |
| 904 | nvidia,function = "pwm2"; |
| 905 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 906 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 907 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 908 | }; |
| 909 | |
| 910 | jtag_rtck_pu7 { |
| 911 | nvidia,pins = "jtag_rtck_pu7"; |
| 912 | nvidia,function = "rtck"; |
| 913 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 914 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 915 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 916 | }; |
| 917 | |
| 918 | crt_hsync_pv6 { |
| 919 | nvidia,pins = "crt_hsync_pv6", |
| 920 | "crt_vsync_pv7"; |
| 921 | nvidia,function = "crt"; |
| 922 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 923 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 924 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 925 | }; |
| 926 | |
| 927 | clk1_out_pw4 { |
| 928 | nvidia,pins = "clk1_out_pw4"; |
| 929 | nvidia,function = "extperiph1"; |
| 930 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 931 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 932 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 933 | }; |
| 934 | |
| 935 | clk2_out_pw5 { |
| 936 | nvidia,pins = "clk2_out_pw5"; |
| 937 | nvidia,function = "extperiph2"; |
| 938 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 939 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 940 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 941 | }; |
| 942 | |
| 943 | clk3_out_pee0 { |
| 944 | nvidia,pins = "clk3_out_pee0"; |
| 945 | nvidia,function = "extperiph3"; |
| 946 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 947 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 948 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 949 | }; |
| 950 | |
| 951 | sys_clk_req_pz5 { |
| 952 | nvidia,pins = "sys_clk_req_pz5"; |
| 953 | nvidia,function = "sysclk"; |
| 954 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 955 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 956 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 957 | }; |
| 958 | |
| 959 | pbb4 { |
| 960 | nvidia,pins = "pbb4"; |
| 961 | nvidia,function = "vgp4"; |
| 962 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 963 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 964 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 965 | }; |
| 966 | |
| 967 | pbb5 { |
| 968 | nvidia,pins = "pbb5"; |
| 969 | nvidia,function = "vgp5"; |
| 970 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 971 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 972 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 973 | }; |
| 974 | |
| 975 | pbb6 { |
| 976 | nvidia,pins = "pbb6"; |
| 977 | nvidia,function = "vgp6"; |
| 978 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 979 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 980 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 981 | }; |
| 982 | |
| 983 | clk1_req_pee2 { |
| 984 | nvidia,pins = "clk1_req_pee2"; |
| 985 | nvidia,function = "dap"; |
| 986 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 987 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 988 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 989 | }; |
| 990 | |
| 991 | clk2_req_pcc5 { |
| 992 | nvidia,pins = "clk2_req_pcc5"; |
| 993 | nvidia,function = "dap"; |
| 994 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 995 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 996 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 997 | }; |
| 998 | |
| 999 | clk3_req_pee1 { |
| 1000 | nvidia,pins = "clk3_req_pee1"; |
| 1001 | nvidia,function = "dev3"; |
| 1002 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1003 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1004 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1005 | }; |
| 1006 | |
| 1007 | owr { |
| 1008 | nvidia,pins = "owr"; |
| 1009 | nvidia,function = "owr"; |
| 1010 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1011 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1012 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1013 | }; |
| 1014 | |
| 1015 | pv2 { |
| 1016 | nvidia,pins = "pv2", |
| 1017 | "kb_row5_pr5"; |
| 1018 | nvidia,function = "owr"; |
| 1019 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1020 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1021 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 1022 | }; |
| 1023 | |
| 1024 | pbb3 { |
| 1025 | nvidia,pins = "pbb3"; |
| 1026 | nvidia,function = "vgp3"; |
| 1027 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1028 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1029 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1030 | }; |
| 1031 | |
| 1032 | pbb7 { |
| 1033 | nvidia,pins = "pbb7"; |
| 1034 | nvidia,function = "i2s4"; |
| 1035 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 1036 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1037 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1038 | }; |
| 1039 | |
| 1040 | cam_mclk_pcc0 { |
| 1041 | nvidia,pins = "cam_mclk_pcc0"; |
| 1042 | nvidia,function = "vi_alt3"; |
| 1043 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 1044 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 1045 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 1046 | }; |
| 1047 | |
| 1048 | /* GPIO power/drive control */ |
| 1049 | drive_dap1 { |
| 1050 | nvidia,pins = "drive_dap1", |
| 1051 | "drive_dap2", |
| 1052 | "drive_dbg", |
| 1053 | "drive_at5", |
| 1054 | "drive_gme", |
| 1055 | "drive_ddc", |
| 1056 | "drive_ao1", |
| 1057 | "drive_uart3"; |
| 1058 | nvidia,high-speed-mode = <0>; |
| 1059 | nvidia,schmitt = <TEGRA_PIN_ENABLE>; |
| 1060 | nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; |
| 1061 | nvidia,pull-down-strength = <31>; |
| 1062 | nvidia,pull-up-strength = <31>; |
| 1063 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| 1064 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| 1065 | }; |
| 1066 | |
| 1067 | drive_sdio1 { |
| 1068 | nvidia,pins = "drive_sdio1"; |
| 1069 | nvidia,high-speed-mode = <0>; |
| 1070 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; |
| 1071 | nvidia,pull-down-strength = <5>; |
| 1072 | nvidia,pull-up-strength = <5>; |
| 1073 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; |
| 1074 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; |
| 1075 | }; |
| 1076 | |
| 1077 | drive_sdio3 { |
| 1078 | nvidia,pins = "drive_sdio3"; |
| 1079 | nvidia,high-speed-mode = <0>; |
| 1080 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; |
| 1081 | nvidia,pull-down-strength = <46>; |
| 1082 | nvidia,pull-up-strength = <42>; |
| 1083 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; |
| 1084 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; |
| 1085 | }; |
| 1086 | |
| 1087 | drive_gma { |
| 1088 | nvidia,pins = "drive_gma", |
| 1089 | "drive_gmb", |
| 1090 | "drive_gmc", |
| 1091 | "drive_gmd"; |
| 1092 | nvidia,pull-down-strength = <9>; |
| 1093 | nvidia,pull-up-strength = <9>; |
| 1094 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; |
| 1095 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; |
| 1096 | }; |
| 1097 | |
| 1098 | drive_lcd2 { |
| 1099 | nvidia,pins = "drive_lcd2"; |
| 1100 | nvidia,high-speed-mode = <0>; |
| 1101 | nvidia,schmitt = <TEGRA_PIN_ENABLE>; |
| 1102 | nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_4>; |
| 1103 | nvidia,pull-down-strength = <20>; |
| 1104 | nvidia,pull-up-strength = <20>; |
| 1105 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| 1106 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| 1107 | }; |
| 1108 | }; |
| 1109 | }; |
| 1110 | |
| 1111 | uartb: serial@70006040 { |
| 1112 | compatible = "nvidia,tegra30-hsuart"; |
| 1113 | reset-names = "serial"; |
| 1114 | /delete-property/ reg-shift; |
| 1115 | status = "okay"; |
| 1116 | |
| 1117 | /* Broadcom GPS BCM47511 */ |
| 1118 | }; |
| 1119 | |
| 1120 | uartc: serial@70006200 { |
| 1121 | compatible = "nvidia,tegra30-hsuart"; |
| 1122 | reset-names = "serial"; |
| 1123 | /delete-property/ reg-shift; |
| 1124 | status = "okay"; |
| 1125 | |
| 1126 | nvidia,adjust-baud-rates = <0 9600 100>, |
| 1127 | <9600 115200 200>, |
| 1128 | <1000000 4000000 136>; |
| 1129 | |
| 1130 | /* Azurewave AW-AH663 BCM4330B1 */ |
| 1131 | bluetooth { |
| 1132 | compatible = "brcm,bcm4330-bt"; |
| 1133 | max-speed = <4000000>; |
| 1134 | |
| 1135 | clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; |
| 1136 | clock-names = "txco"; |
| 1137 | |
| 1138 | interrupt-parent = <&gpio>; |
| 1139 | interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>; |
| 1140 | interrupt-names = "host-wakeup"; |
| 1141 | |
| 1142 | device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; |
| 1143 | shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; |
| 1144 | |
| 1145 | vbat-supply = <&vdd_3v3_sys>; |
| 1146 | vddio-supply = <&vdd_1v8_vio>; |
| 1147 | }; |
| 1148 | }; |
| 1149 | |
| 1150 | pwm: pwm@7000a000 { |
| 1151 | status = "okay"; |
| 1152 | }; |
| 1153 | |
| 1154 | lcd_ddc: i2c@7000c000 { |
| 1155 | status = "okay"; |
| 1156 | clock-frequency = <400000>; |
| 1157 | |
| 1158 | /* Wolfson Microelectronics WM8903 audio codec */ |
| 1159 | wm8903: audio-codec@1a { |
| 1160 | compatible = "wlf,wm8903"; |
| 1161 | reg = <0x1a>; |
| 1162 | |
| 1163 | interrupt-parent = <&gpio>; |
| 1164 | interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_BOTH>; |
| 1165 | |
| 1166 | gpio-controller; |
| 1167 | #gpio-cells = <2>; |
| 1168 | |
| 1169 | micdet-cfg = <0>; |
| 1170 | micdet-delay = <100>; |
| 1171 | |
| 1172 | gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; |
| 1173 | |
| 1174 | AVDD-supply = <&vdd_1v8_vio>; |
| 1175 | CPVDD-supply = <&vdd_1v8_vio>; |
| 1176 | DBVDD-supply = <&vdd_1v8_vio>; |
| 1177 | DCVDD-supply = <&vdd_1v8_vio>; |
| 1178 | }; |
| 1179 | }; |
| 1180 | |
| 1181 | i2c2: i2c@7000c400 { |
| 1182 | status = "okay"; |
| 1183 | clock-frequency = <400000>; |
| 1184 | |
| 1185 | /* Atmel touchscreen */ |
| 1186 | touchscreen@4d { |
| 1187 | compatible = "atmel,maxtouch"; |
| 1188 | reg = <0x4d>; |
| 1189 | |
| 1190 | interrupt-parent = <&gpio>; |
| 1191 | interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_FALLING>; |
| 1192 | reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; |
| 1193 | |
| 1194 | vdda-supply = <&vdd_3v3_sys>; |
| 1195 | vdd-supply = <&vdd_3v3_sys>; |
| 1196 | }; |
| 1197 | }; |
| 1198 | |
| 1199 | i2c3: i2c@7000c500 { |
| 1200 | status = "okay"; |
| 1201 | clock-frequency = <400000>; |
| 1202 | |
| 1203 | /* AsahiKASEI AK8975 magnetometer sensor */ |
| 1204 | magnetometer@c { |
| 1205 | compatible = "asahi-kasei,ak8975"; |
| 1206 | reg = <0x0c>; |
| 1207 | |
| 1208 | vdd-supply = <&vdd_3v3_sen>; |
| 1209 | vid-supply = <&vdd_1v8_vio>; |
| 1210 | |
| 1211 | mount-matrix = "0", "1", "0", |
| 1212 | "1", "0", "0", |
| 1213 | "0", "0", "-1"; |
| 1214 | }; |
| 1215 | |
| 1216 | light-sensor@44 { |
| 1217 | compatible = "isil,isl29023"; |
| 1218 | reg = <0x44>; |
| 1219 | |
| 1220 | interrupt-parent = <&gpio>; |
| 1221 | interrupts = <TEGRA_GPIO(Q, 3) IRQ_TYPE_LEVEL_HIGH>; |
| 1222 | |
| 1223 | vcc-supply = <&vdd_3v3_sen>; |
| 1224 | }; |
| 1225 | |
| 1226 | gyroscope@68 { |
| 1227 | compatible = "invensense,mpu3050"; |
| 1228 | reg = <0x68>; |
| 1229 | |
| 1230 | interrupt-parent = <&gpio>; |
| 1231 | interrupts = <TEGRA_GPIO(X, 1) IRQ_TYPE_EDGE_RISING>; |
| 1232 | |
| 1233 | vdd-supply = <&vdd_3v3_sen>; |
| 1234 | vlogic-supply = <&vdd_1v8_vio>; |
| 1235 | |
| 1236 | mount-matrix = "0", "1", "0", |
| 1237 | "1", "0", "0", |
| 1238 | "0", "0", "-1"; |
| 1239 | |
| 1240 | /* External I2C interface */ |
| 1241 | i2c-gate { |
| 1242 | #address-cells = <1>; |
| 1243 | #size-cells = <0>; |
| 1244 | |
| 1245 | accelerometer@f { |
| 1246 | compatible = "kionix,kxtf9"; |
| 1247 | reg = <0x0f>; |
| 1248 | |
| 1249 | interrupt-parent = <&gpio>; |
| 1250 | interrupts = <TEGRA_GPIO(L, 1) IRQ_TYPE_EDGE_RISING>; |
| 1251 | |
| 1252 | vdd-supply = <&vdd_1v8_vio>; |
| 1253 | vddio-supply = <&vdd_1v8_vio>; |
| 1254 | |
| 1255 | mount-matrix = "-1", "0", "0", |
| 1256 | "0", "1", "0", |
| 1257 | "0", "0", "1"; |
| 1258 | }; |
| 1259 | }; |
| 1260 | }; |
| 1261 | }; |
| 1262 | |
| 1263 | hdmi_ddc: i2c@7000c700 { |
| 1264 | status = "okay"; |
| 1265 | clock-frequency = <93750>; |
| 1266 | }; |
| 1267 | |
| 1268 | i2c5: i2c@7000d000 { |
| 1269 | status = "okay"; |
| 1270 | clock-frequency = <400000>; |
| 1271 | |
| 1272 | /* Texas Instruments TPS659110 PMIC */ |
| 1273 | pmic: pmic@2d { |
| 1274 | compatible = "ti,tps65911"; |
| 1275 | reg = <0x2d>; |
| 1276 | |
| 1277 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| 1278 | #interrupt-cells = <2>; |
| 1279 | interrupt-controller; |
| 1280 | wakeup-source; |
| 1281 | |
| 1282 | ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>; |
| 1283 | ti,system-power-controller; |
| 1284 | ti,sleep-keep-ck32k; |
| 1285 | ti,sleep-enable; |
| 1286 | |
| 1287 | #gpio-cells = <2>; |
| 1288 | gpio-controller; |
| 1289 | |
| 1290 | vcc1-supply = <&vdd_5v0_sys>; |
| 1291 | vcc2-supply = <&vdd_5v0_sys>; |
| 1292 | vcc3-supply = <&vdd_1v8_vio>; |
| 1293 | vcc4-supply = <&vdd_1v8_vio>; |
| 1294 | vcc5-supply = <&vdd_5v0_sys>; |
| 1295 | vcc6-supply = <&vddio_1v2_ddr>; |
| 1296 | vcc7-supply = <&vdd_5v0_sys>; |
| 1297 | vccio-supply = <&vdd_5v0_sys>; |
| 1298 | |
| 1299 | pmic-sleep-hog { |
| 1300 | gpio-hog; |
| 1301 | gpios = <0 GPIO_ACTIVE_HIGH>, |
| 1302 | <2 GPIO_ACTIVE_HIGH>, |
| 1303 | <6 GPIO_ACTIVE_HIGH>, |
| 1304 | <8 GPIO_ACTIVE_HIGH>; |
| 1305 | output-high; |
| 1306 | }; |
| 1307 | |
| 1308 | regulators { |
| 1309 | /* VDD1 is not used by Chagall */ |
| 1310 | |
| 1311 | vddio_1v2_ddr: vdd2 { |
| 1312 | regulator-name = "vddio_1v2_ddr"; |
| 1313 | regulator-min-microvolt = <1200000>; |
| 1314 | regulator-max-microvolt = <1200000>; |
| 1315 | regulator-always-on; |
| 1316 | regulator-boot-on; |
| 1317 | }; |
| 1318 | |
| 1319 | vdd_cpu: vddctrl { |
| 1320 | regulator-name = "vdd_cpu,vdd_sys"; |
| 1321 | regulator-min-microvolt = <600000>; |
| 1322 | regulator-max-microvolt = <1400000>; |
| 1323 | regulator-coupled-with = <&vdd_core>; |
| 1324 | regulator-coupled-max-spread = <300000>; |
| 1325 | regulator-max-step-microvolt = <100000>; |
| 1326 | regulator-always-on; |
| 1327 | regulator-boot-on; |
| 1328 | ti,regulator-ext-sleep-control = <1>; |
| 1329 | |
| 1330 | nvidia,tegra-cpu-regulator; |
| 1331 | }; |
| 1332 | |
| 1333 | vdd_1v8_vio: vio { |
| 1334 | regulator-name = "vdd_1v8_gen"; |
| 1335 | /* FIXME: eMMC won't work, if set to 1.8 V */ |
| 1336 | regulator-min-microvolt = <1500000>; |
| 1337 | regulator-max-microvolt = <3300000>; |
| 1338 | regulator-always-on; |
| 1339 | regulator-boot-on; |
| 1340 | }; |
| 1341 | |
| 1342 | /* eMMC VDD */ |
| 1343 | vcore_emmc: ldo1 { |
| 1344 | regulator-name = "vdd_emmc_core"; |
| 1345 | regulator-min-microvolt = <1000000>; |
| 1346 | regulator-max-microvolt = <3300000>; |
| 1347 | regulator-always-on; |
| 1348 | }; |
| 1349 | |
| 1350 | /* uSD slot VDD */ |
| 1351 | vdd_usd: ldo2 { |
| 1352 | regulator-name = "vdd_usd"; |
| 1353 | regulator-min-microvolt = <3200000>; |
| 1354 | regulator-max-microvolt = <3200000>; |
| 1355 | }; |
| 1356 | |
| 1357 | /* uSD slot VDDIO */ |
| 1358 | vddio_usd: ldo3 { |
| 1359 | regulator-name = "vddio_usd"; |
| 1360 | regulator-min-microvolt = <1900000>; |
| 1361 | regulator-max-microvolt = <3200000>; |
| 1362 | }; |
| 1363 | |
| 1364 | ldo4 { |
| 1365 | regulator-name = "vdd_rtc"; |
| 1366 | regulator-min-microvolt = <1200000>; |
| 1367 | regulator-max-microvolt = <1200000>; |
| 1368 | regulator-always-on; |
| 1369 | }; |
| 1370 | |
| 1371 | ldo5 { |
| 1372 | regulator-name = "vdd_1v3_cam_isp"; |
| 1373 | regulator-min-microvolt = <1300000>; |
| 1374 | regulator-max-microvolt = <1300000>; |
| 1375 | }; |
| 1376 | |
| 1377 | ldo6 { |
| 1378 | regulator-name = "avdd_dsi_csi,pwrdet_mipi"; |
| 1379 | regulator-min-microvolt = <1200000>; |
| 1380 | regulator-max-microvolt = <1200000>; |
| 1381 | }; |
| 1382 | |
| 1383 | ldo7 { |
| 1384 | regulator-name = "vdd_pllm,x,u,a_p_c_s"; |
| 1385 | regulator-min-microvolt = <1200000>; |
| 1386 | regulator-max-microvolt = <1200000>; |
| 1387 | regulator-always-on; |
| 1388 | regulator-boot-on; |
| 1389 | ti,regulator-ext-sleep-control = <8>; |
| 1390 | }; |
| 1391 | |
| 1392 | ldo8 { |
| 1393 | regulator-name = "vdd_ddr_hs"; |
| 1394 | regulator-min-microvolt = <1000000>; |
| 1395 | regulator-max-microvolt = <1000000>; |
| 1396 | regulator-always-on; |
| 1397 | ti,regulator-ext-sleep-control = <8>; |
| 1398 | }; |
| 1399 | }; |
| 1400 | }; |
| 1401 | |
| 1402 | nct72: temperature-sensor@4c { |
| 1403 | compatible = "onnn,nct1008"; |
| 1404 | reg = <0x4c>; |
| 1405 | |
| 1406 | interrupt-parent = <&gpio>; |
| 1407 | interrupts = <TEGRA_GPIO(U, 5) IRQ_TYPE_EDGE_FALLING>; |
| 1408 | |
| 1409 | vcc-supply = <&vdd_3v3_sys>; |
| 1410 | #thermal-sensor-cells = <1>; |
| 1411 | }; |
| 1412 | |
| 1413 | vdd_core: core-regulator@60 { |
| 1414 | compatible = "ti,tps62361"; |
| 1415 | reg = <0x60>; |
| 1416 | |
| 1417 | regulator-name = "tps62361-vout"; |
| 1418 | regulator-min-microvolt = <500000>; |
| 1419 | regulator-max-microvolt = <1770000>; |
| 1420 | regulator-coupled-with = <&vdd_cpu>; |
| 1421 | regulator-coupled-max-spread = <300000>; |
| 1422 | regulator-max-step-microvolt = <100000>; |
| 1423 | regulator-boot-on; |
| 1424 | regulator-always-on; |
| 1425 | ti,enable-vout-discharge; |
| 1426 | ti,vsel0-state-high; |
| 1427 | ti,vsel1-state-high; |
| 1428 | |
| 1429 | nvidia,tegra-core-regulator; |
| 1430 | }; |
| 1431 | }; |
| 1432 | |
| 1433 | vdd_5v0_sys: regulator-5v { |
| 1434 | compatible = "regulator-fixed"; |
| 1435 | regulator-name = "vdd_5v0_sys"; |
| 1436 | regulator-min-microvolt = <5000000>; |
| 1437 | regulator-max-microvolt = <5000000>; |
| 1438 | regulator-always-on; |
| 1439 | regulator-boot-on; |
| 1440 | }; |
| 1441 | |
| 1442 | vdd_3v3_sys: regulator-3v { |
| 1443 | compatible = "regulator-fixed"; |
| 1444 | regulator-name = "vdd_3v3_sys"; |
| 1445 | regulator-min-microvolt = <3300000>; |
| 1446 | regulator-max-microvolt = <3300000>; |
| 1447 | regulator-always-on; |
| 1448 | regulator-boot-on; |
| 1449 | }; |
| 1450 | |
| 1451 | vdd_pnl: regulator-panel { |
| 1452 | compatible = "regulator-fixed"; |
| 1453 | regulator-name = "vdd_panel"; |
| 1454 | regulator-min-microvolt = <3300000>; |
| 1455 | regulator-max-microvolt = <3300000>; |
| 1456 | regulator-enable-ramp-delay = <300000>; |
| 1457 | gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>; |
| 1458 | enable-active-high; |
| 1459 | vin-supply = <&vdd_3v3_sys>; |
| 1460 | }; |
| 1461 | |
| 1462 | vdd_3v3_sen: regulator-sensors { |
| 1463 | compatible = "regulator-fixed"; |
| 1464 | regulator-name = "sen_3v3_en"; |
| 1465 | regulator-min-microvolt = <3300000>; |
| 1466 | regulator-max-microvolt = <3300000>; |
| 1467 | gpio = <&gpio TEGRA_GPIO(K, 5) GPIO_ACTIVE_HIGH>; |
| 1468 | enable-active-high; |
| 1469 | vin-supply = <&vdd_3v3_sys>; |
| 1470 | }; |
| 1471 | |
| 1472 | vdd_5v0_bl: regulator-bl { |
| 1473 | compatible = "regulator-fixed"; |
| 1474 | regulator-name = "vdd_5v0_bl"; |
| 1475 | regulator-min-microvolt = <5000000>; |
| 1476 | regulator-max-microvolt = <5000000>; |
| 1477 | regulator-boot-on; |
| 1478 | gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; |
| 1479 | enable-active-high; |
| 1480 | vin-supply = <&vdd_5v0_sys>; |
| 1481 | }; |
| 1482 | |
| 1483 | hdmi_5v0_sys: regulator-hdmi { |
| 1484 | compatible = "regulator-fixed"; |
| 1485 | regulator-name = "hdmi_5v0_sys"; |
| 1486 | regulator-min-microvolt = <5000000>; |
| 1487 | regulator-max-microvolt = <5000000>; |
| 1488 | gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; |
| 1489 | enable-active-high; |
| 1490 | vin-supply = <&vdd_5v0_sys>; |
| 1491 | }; |
| 1492 | |
| 1493 | vdd_vbus_usb1: regulator-usb1 { |
| 1494 | compatible = "regulator-fixed"; |
| 1495 | regulator-name = "vdd_vbus_micro_usb"; |
| 1496 | regulator-min-microvolt = <5000000>; |
| 1497 | regulator-max-microvolt = <5000000>; |
| 1498 | gpio = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_HIGH>; |
| 1499 | enable-active-high; |
| 1500 | vin-supply = <&vdd_5v0_sys>; |
| 1501 | }; |
| 1502 | |
| 1503 | vdd_vbus_usb3: regulator-usb3 { |
| 1504 | compatible = "regulator-fixed"; |
| 1505 | regulator-name = "vdd_vbus_typea_usb"; |
| 1506 | regulator-min-microvolt = <5000000>; |
| 1507 | regulator-max-microvolt = <5000000>; |
| 1508 | gpio = <&gpio TEGRA_GPIO(CC, 6) GPIO_ACTIVE_HIGH>; |
| 1509 | enable-active-high; |
| 1510 | vin-supply = <&vdd_5v0_sys>; |
| 1511 | }; |
| 1512 | |
| 1513 | pmc@7000e400 { |
| 1514 | status = "okay"; |
| 1515 | nvidia,invert-interrupt; |
| 1516 | nvidia,suspend-mode = <2>; |
| 1517 | nvidia,cpu-pwr-good-time = <2000>; |
| 1518 | nvidia,cpu-pwr-off-time = <200>; |
| 1519 | nvidia,core-pwr-good-time = <3845 3845>; |
| 1520 | nvidia,core-pwr-off-time = <0>; |
| 1521 | nvidia,core-power-req-active-high; |
| 1522 | nvidia,sys-clock-req-active-high; |
| 1523 | core-supply = <&vdd_core>; |
| 1524 | |
| 1525 | /* Set DEV_OFF + PWR_OFF_SET bit in DCDC control register of TPS65911 PMIC */ |
| 1526 | i2c-thermtrip { |
| 1527 | nvidia,i2c-controller-id = <4>; |
| 1528 | nvidia,bus-addr = <0x2d>; |
| 1529 | nvidia,reg-addr = <0x3f>; |
| 1530 | nvidia,reg-data = <0x81>; |
| 1531 | }; |
| 1532 | }; |
| 1533 | |
| 1534 | memory-controller@7000f000 { |
| 1535 | emc-timings-0 { |
| 1536 | /* SAMSUNG K4P8G304EB FGC1 */ |
| 1537 | nvidia,ram-code = <0>; |
| 1538 | |
| 1539 | timing-25500000 { |
| 1540 | clock-frequency = <25500000>; |
| 1541 | |
| 1542 | nvidia,emem-configuration = < 0x00020001 0xc0000010 |
| 1543 | 0x00000001 0x00000001 0x00000002 0x00000000 |
| 1544 | 0x00000003 0x00000001 0x00000002 0x00000004 |
| 1545 | 0x00000001 0x00000000 0x00000002 0x00000002 |
| 1546 | 0x02020001 0x00060402 0x73e30303 0x001f0000 >; |
| 1547 | }; |
| 1548 | |
| 1549 | timing-51000000 { |
| 1550 | clock-frequency = <51000000>; |
| 1551 | |
| 1552 | nvidia,emem-configuration = < 0x00010001 0xc0000010 |
| 1553 | 0x00000001 0x00000001 0x00000002 0x00000000 |
| 1554 | 0x00000003 0x00000001 0x00000002 0x00000004 |
| 1555 | 0x00000001 0x00000000 0x00000002 0x00000002 |
| 1556 | 0x02020001 0x00060402 0x72c30303 0x001f0000 >; |
| 1557 | }; |
| 1558 | |
| 1559 | timing-102000000 { |
| 1560 | clock-frequency = <102000000>; |
| 1561 | |
| 1562 | nvidia,emem-configuration = < 0x00000001 0xc0000018 |
| 1563 | 0x00000001 0x00000001 0x00000003 0x00000001 |
| 1564 | 0x00000003 0x00000001 0x00000002 0x00000004 |
| 1565 | 0x00000001 0x00000000 0x00000002 0x00000002 |
| 1566 | 0x02020001 0x00060403 0x72430504 0x001f0000 >; |
| 1567 | }; |
| 1568 | |
| 1569 | timing-204000000 { |
| 1570 | clock-frequency = <204000000>; |
| 1571 | |
| 1572 | nvidia,emem-configuration = < 0x00000003 0xc0000025 |
| 1573 | 0x00000001 0x00000001 0x00000006 0x00000003 |
| 1574 | 0x00000005 0x00000001 0x00000002 0x00000004 |
| 1575 | 0x00000001 0x00000000 0x00000003 0x00000002 |
| 1576 | 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; |
| 1577 | }; |
| 1578 | |
| 1579 | timing-400000000 { |
| 1580 | clock-frequency = <400000000>; |
| 1581 | |
| 1582 | nvidia,emem-configuration = < 0x00000006 0xc0000048 |
| 1583 | 0x00000002 0x00000003 0x0000000c 0x00000007 |
| 1584 | 0x00000009 0x00000001 0x00000002 0x00000006 |
| 1585 | 0x00000001 0x00000000 0x00000004 0x00000004 |
| 1586 | 0x04040001 0x000d090c 0x7026120d 0x001f0000 >; |
| 1587 | }; |
| 1588 | }; |
| 1589 | |
| 1590 | emc-timings-1 { |
| 1591 | /* ELPIDA EDB8132B2MA 8D_F */ |
| 1592 | nvidia,ram-code = <1>; |
| 1593 | |
| 1594 | timing-25500000 { |
| 1595 | clock-frequency = <25500000>; |
| 1596 | |
| 1597 | nvidia,emem-configuration = < 0x00020001 0xc0000010 |
| 1598 | 0x00000001 0x00000001 0x00000002 0x00000000 |
| 1599 | 0x00000003 0x00000001 0x00000002 0x00000004 |
| 1600 | 0x00000001 0x00000000 0x00000002 0x00000002 |
| 1601 | 0x02020001 0x00060402 0x73e30303 0x001f0000 >; |
| 1602 | }; |
| 1603 | |
| 1604 | timing-51000000 { |
| 1605 | clock-frequency = <51000000>; |
| 1606 | |
| 1607 | nvidia,emem-configuration = < 0x00010001 0xc0000010 |
| 1608 | 0x00000001 0x00000001 0x00000002 0x00000000 |
| 1609 | 0x00000003 0x00000001 0x00000002 0x00000004 |
| 1610 | 0x00000001 0x00000000 0x00000002 0x00000002 |
| 1611 | 0x02020001 0x00060402 0x72c30303 0x001f0000 >; |
| 1612 | }; |
| 1613 | |
| 1614 | timing-102000000 { |
| 1615 | clock-frequency = <102000000>; |
| 1616 | |
| 1617 | nvidia,emem-configuration = < 0x00000001 0xc0000018 |
| 1618 | 0x00000001 0x00000001 0x00000003 0x00000001 |
| 1619 | 0x00000003 0x00000001 0x00000002 0x00000004 |
| 1620 | 0x00000001 0x00000000 0x00000002 0x00000002 |
| 1621 | 0x02020001 0x00060403 0x72430504 0x001f0000 >; |
| 1622 | }; |
| 1623 | |
| 1624 | timing-204000000 { |
| 1625 | clock-frequency = <204000000>; |
| 1626 | |
| 1627 | nvidia,emem-configuration = < 0x00000003 0xc0000025 |
| 1628 | 0x00000001 0x00000001 0x00000006 0x00000003 |
| 1629 | 0x00000005 0x00000001 0x00000002 0x00000004 |
| 1630 | 0x00000001 0x00000000 0x00000003 0x00000002 |
| 1631 | 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; |
| 1632 | }; |
| 1633 | |
| 1634 | timing-400000000 { |
| 1635 | clock-frequency = <400000000>; |
| 1636 | |
| 1637 | nvidia,emem-configuration = < 0x00000006 0xc0000048 |
| 1638 | 0x00000002 0x00000003 0x0000000c 0x00000007 |
| 1639 | 0x00000009 0x00000001 0x00000002 0x00000006 |
| 1640 | 0x00000001 0x00000000 0x00000004 0x00000004 |
| 1641 | 0x04040001 0x000d090c 0x7026120d 0x001f0000 >; |
| 1642 | }; |
| 1643 | }; |
| 1644 | |
| 1645 | emc-timings-2 { |
| 1646 | /* SAMSUNG K4P8G304EB FGC2 */ |
| 1647 | nvidia,ram-code = <2>; |
| 1648 | |
| 1649 | timing-25500000 { |
| 1650 | clock-frequency = <25500000>; |
| 1651 | |
| 1652 | nvidia,emem-configuration = < 0x00020001 0xc0000010 |
| 1653 | 0x00000001 0x00000001 0x00000002 0x00000000 |
| 1654 | 0x00000003 0x00000001 0x00000002 0x00000004 |
| 1655 | 0x00000001 0x00000000 0x00000002 0x00000002 |
| 1656 | 0x02020001 0x00060402 0x73e30303 0x001f0000 >; |
| 1657 | }; |
| 1658 | |
| 1659 | timing-51000000 { |
| 1660 | clock-frequency = <51000000>; |
| 1661 | |
| 1662 | nvidia,emem-configuration = < 0x00010001 0xc0000010 |
| 1663 | 0x00000001 0x00000001 0x00000002 0x00000000 |
| 1664 | 0x00000003 0x00000001 0x00000002 0x00000004 |
| 1665 | 0x00000001 0x00000000 0x00000002 0x00000002 |
| 1666 | 0x02020001 0x00060402 0x72c30303 0x001f0000 >; |
| 1667 | }; |
| 1668 | |
| 1669 | timing-102000000 { |
| 1670 | clock-frequency = <102000000>; |
| 1671 | |
| 1672 | nvidia,emem-configuration = < 0x00000001 0xc0000018 |
| 1673 | 0x00000001 0x00000001 0x00000003 0x00000001 |
| 1674 | 0x00000003 0x00000001 0x00000002 0x00000004 |
| 1675 | 0x00000001 0x00000000 0x00000002 0x00000002 |
| 1676 | 0x02020001 0x00060403 0x72430504 0x001f0000 >; |
| 1677 | }; |
| 1678 | |
| 1679 | timing-204000000 { |
| 1680 | clock-frequency = <204000000>; |
| 1681 | |
| 1682 | nvidia,emem-configuration = < 0x00000003 0xc0000025 |
| 1683 | 0x00000001 0x00000001 0x00000006 0x00000003 |
| 1684 | 0x00000005 0x00000001 0x00000002 0x00000004 |
| 1685 | 0x00000001 0x00000000 0x00000003 0x00000002 |
| 1686 | 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; |
| 1687 | }; |
| 1688 | |
| 1689 | timing-533000000 { |
| 1690 | clock-frequency = <533000000>; |
| 1691 | |
| 1692 | nvidia,emem-configuration = < 0x00000008 0xc0000060 |
| 1693 | 0x00000003 0x00000004 0x00000010 0x0000000a |
| 1694 | 0x0000000d 0x00000002 0x00000002 0x00000008 |
| 1695 | 0x00000002 0x00000000 0x00000004 0x00000005 |
| 1696 | 0x05040002 0x00110b10 0x70281811 0x001f0000 >; |
| 1697 | }; |
| 1698 | }; |
| 1699 | |
| 1700 | emc-timings-3 { |
| 1701 | /* HYNIX H9TCNNN8JDMMPR NGM */ |
| 1702 | nvidia,ram-code = <3>; |
| 1703 | |
| 1704 | timing-25500000 { |
| 1705 | clock-frequency = <25500000>; |
| 1706 | |
| 1707 | nvidia,emem-configuration = < 0x00020001 0xc0000010 |
| 1708 | 0x00000001 0x00000001 0x00000002 0x00000000 |
| 1709 | 0x00000003 0x00000001 0x00000002 0x00000004 |
| 1710 | 0x00000001 0x00000000 0x00000002 0x00000002 |
| 1711 | 0x02020001 0x00060402 0x73e30303 0x001f0000 >; |
| 1712 | }; |
| 1713 | |
| 1714 | timing-51000000 { |
| 1715 | clock-frequency = <51000000>; |
| 1716 | |
| 1717 | nvidia,emem-configuration = < 0x00010001 0xc0000010 |
| 1718 | 0x00000001 0x00000001 0x00000002 0x00000000 |
| 1719 | 0x00000003 0x00000001 0x00000002 0x00000004 |
| 1720 | 0x00000001 0x00000000 0x00000002 0x00000002 |
| 1721 | 0x02020001 0x00060402 0x72c30303 0x001f0000 >; |
| 1722 | }; |
| 1723 | |
| 1724 | timing-102000000 { |
| 1725 | clock-frequency = <102000000>; |
| 1726 | |
| 1727 | nvidia,emem-configuration = < 0x00000001 0xc0000018 |
| 1728 | 0x00000001 0x00000001 0x00000003 0x00000001 |
| 1729 | 0x00000003 0x00000001 0x00000002 0x00000004 |
| 1730 | 0x00000001 0x00000000 0x00000002 0x00000002 |
| 1731 | 0x02020001 0x00060403 0x72430504 0x001f0000 >; |
| 1732 | }; |
| 1733 | |
| 1734 | timing-204000000 { |
| 1735 | clock-frequency = <204000000>; |
| 1736 | |
| 1737 | nvidia,emem-configuration = < 0x00000003 0xc0000025 |
| 1738 | 0x00000001 0x00000001 0x00000006 0x00000003 |
| 1739 | 0x00000005 0x00000001 0x00000002 0x00000004 |
| 1740 | 0x00000001 0x00000000 0x00000003 0x00000002 |
| 1741 | 0x02030001 0x00070506 0x71e40a07 0x001f0000 >; |
| 1742 | }; |
| 1743 | |
| 1744 | timing-533000000 { |
| 1745 | clock-frequency = <533000000>; |
| 1746 | |
| 1747 | nvidia,emem-configuration = < 0x00000008 0xc0000060 |
| 1748 | 0x00000003 0x00000004 0x00000010 0x0000000a |
| 1749 | 0x0000000d 0x00000002 0x00000002 0x00000008 |
| 1750 | 0x00000002 0x00000000 0x00000004 0x00000005 |
| 1751 | 0x05040002 0x00110b10 0x70281811 0x001f0000 >; |
| 1752 | }; |
| 1753 | }; |
| 1754 | }; |
| 1755 | |
| 1756 | memory-controller@7000f400 { |
| 1757 | emc-timings-0 { |
| 1758 | /* SAMSUNG K4P8G304EB FGC1 */ |
| 1759 | nvidia,ram-code = <0>; |
| 1760 | |
| 1761 | timing-25500000 { |
| 1762 | clock-frequency = <25500000>; |
| 1763 | |
| 1764 | nvidia,emc-auto-cal-interval = <0x001fffff>; |
| 1765 | nvidia,emc-mode-1 = <0x00010022>; |
| 1766 | nvidia,emc-mode-2 = <0x00020001>; |
| 1767 | nvidia,emc-mode-reset = <0x00000000>; |
| 1768 | nvidia,emc-zcal-cnt-long = <0x00000009>; |
| 1769 | nvidia,emc-cfg-dyn-self-ref; |
| 1770 | nvidia,emc-cfg-periodic-qrst; |
| 1771 | |
| 1772 | nvidia,emc-configuration = < 0x00000001 |
| 1773 | 0x00000003 0x00000002 0x00000002 0x00000004 |
| 1774 | 0x00000004 0x00000001 0x00000005 0x00000002 |
| 1775 | 0x00000002 0x00000001 0x00000001 0x00000000 |
| 1776 | 0x00000001 0x00000003 0x00000001 0x0000000b |
| 1777 | 0x00000009 0x00000060 0x00000000 0x00000018 |
| 1778 | 0x00000001 0x00000001 0x00000002 0x00000000 |
| 1779 | 0x00000001 0x00000007 0x00000004 0x00000004 |
| 1780 | 0x00000003 0x00000008 0x00000004 0x00000004 |
| 1781 | 0x00000002 0x0000006b 0x00000004 0x00000004 |
| 1782 | 0x00000000 0x00000000 0x00004282 0x007800a4 |
| 1783 | 0x00008000 0x000fc000 0x000fc000 0x000fc000 |
| 1784 | 0x000fc000 0x000fc000 0x000fc000 0x000fc000 |
| 1785 | 0x000fc000 0x00000000 0x00000000 0x00000000 |
| 1786 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 1787 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 1788 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 1789 | 0x00000000 0x000fc000 0x000fc000 0x000fc000 |
| 1790 | 0x000fc000 0x00100220 0x0800201c 0x00000000 |
| 1791 | 0x77ffc004 0x01f1f008 0x00000000 0x00000007 |
| 1792 | 0x08000068 0x08000000 0x00000802 0x00064000 |
| 1793 | 0x0000000a 0x00090009 0xa0f10000 0x00000000 |
| 1794 | 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; |
| 1795 | }; |
| 1796 | |
| 1797 | timing-51000000 { |
| 1798 | clock-frequency = <51000000>; |
| 1799 | |
| 1800 | nvidia,emc-auto-cal-interval = <0x001fffff>; |
| 1801 | nvidia,emc-mode-1 = <0x00010022>; |
| 1802 | nvidia,emc-mode-2 = <0x00020001>; |
| 1803 | nvidia,emc-mode-reset = <0x00000000>; |
| 1804 | nvidia,emc-zcal-cnt-long = <0x00000009>; |
| 1805 | nvidia,emc-cfg-dyn-self-ref; |
| 1806 | nvidia,emc-cfg-periodic-qrst; |
| 1807 | |
| 1808 | nvidia,emc-configuration = < 0x00000003 |
| 1809 | 0x00000006 0x00000002 0x00000002 0x00000004 |
| 1810 | 0x00000004 0x00000001 0x00000005 0x00000002 |
| 1811 | 0x00000002 0x00000001 0x00000001 0x00000000 |
| 1812 | 0x00000001 0x00000003 0x00000001 0x0000000b |
| 1813 | 0x00000009 0x000000c0 0x00000000 0x00000030 |
| 1814 | 0x00000001 0x00000001 0x00000002 0x00000000 |
| 1815 | 0x00000001 0x00000007 0x00000008 0x00000008 |
| 1816 | 0x00000003 0x00000008 0x00000004 0x00000004 |
| 1817 | 0x00000002 0x000000d5 0x00000004 0x00000004 |
| 1818 | 0x00000000 0x00000000 0x00004282 0x007800a4 |
| 1819 | 0x00008000 0x000fc000 0x000fc000 0x000fc000 |
| 1820 | 0x000fc000 0x000fc000 0x000fc000 0x000fc000 |
| 1821 | 0x000fc000 0x00000000 0x00000000 0x00000000 |
| 1822 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 1823 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 1824 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 1825 | 0x00000000 0x000fc000 0x000fc000 0x000fc000 |
| 1826 | 0x000fc000 0x00100220 0x0800201c 0x00000000 |
| 1827 | 0x77ffc004 0x01f1f008 0x00000000 0x00000007 |
| 1828 | 0x08000068 0x08000000 0x00000802 0x00064000 |
| 1829 | 0x00000013 0x00090009 0xa0f10000 0x00000000 |
| 1830 | 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; |
| 1831 | }; |
| 1832 | |
| 1833 | timing-102000000 { |
| 1834 | clock-frequency = <102000000>; |
| 1835 | |
| 1836 | nvidia,emc-auto-cal-interval = <0x001fffff>; |
| 1837 | nvidia,emc-mode-1 = <0x00010022>; |
| 1838 | nvidia,emc-mode-2 = <0x00020001>; |
| 1839 | nvidia,emc-mode-reset = <0x00000000>; |
| 1840 | nvidia,emc-zcal-cnt-long = <0x0000000a>; |
| 1841 | nvidia,emc-cfg-dyn-self-ref; |
| 1842 | nvidia,emc-cfg-periodic-qrst; |
| 1843 | |
| 1844 | nvidia,emc-configuration = < 0x00000006 |
| 1845 | 0x0000000d 0x00000004 0x00000002 0x00000004 |
| 1846 | 0x00000004 0x00000001 0x00000005 0x00000002 |
| 1847 | 0x00000002 0x00000001 0x00000001 0x00000000 |
| 1848 | 0x00000001 0x00000003 0x00000001 0x0000000b |
| 1849 | 0x00000009 0x00000181 0x00000000 0x00000060 |
| 1850 | 0x00000001 0x00000001 0x00000002 0x00000000 |
| 1851 | 0x00000001 0x00000007 0x0000000f 0x0000000f |
| 1852 | 0x00000003 0x00000008 0x00000004 0x00000004 |
| 1853 | 0x00000002 0x000001a9 0x00000004 0x00000004 |
| 1854 | 0x00000000 0x00000000 0x00004282 0x007800a4 |
| 1855 | 0x00008000 0x000fc000 0x000fc000 0x000fc000 |
| 1856 | 0x000fc000 0x000fc000 0x000fc000 0x000fc000 |
| 1857 | 0x000fc000 0x00000000 0x00000000 0x00000000 |
| 1858 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 1859 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 1860 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 1861 | 0x00000000 0x000fc000 0x000fc000 0x000fc000 |
| 1862 | 0x000fc000 0x00100220 0x0800201c 0x00000000 |
| 1863 | 0x77ffc004 0x01f1f008 0x00000000 0x00000007 |
| 1864 | 0x08000068 0x08000000 0x00000802 0x00064000 |
| 1865 | 0x00000025 0x00090009 0xa0f10000 0x00000000 |
| 1866 | 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; |
| 1867 | }; |
| 1868 | |
| 1869 | timing-204000000 { |
| 1870 | clock-frequency = <204000000>; |
| 1871 | |
| 1872 | nvidia,emc-auto-cal-interval = <0x001fffff>; |
| 1873 | nvidia,emc-mode-1 = <0x00010042>; |
| 1874 | nvidia,emc-mode-2 = <0x00020001>; |
| 1875 | nvidia,emc-mode-reset = <0x00000000>; |
| 1876 | nvidia,emc-zcal-cnt-long = <0x00000013>; |
| 1877 | nvidia,emc-cfg-dyn-self-ref; |
| 1878 | nvidia,emc-cfg-periodic-qrst; |
| 1879 | |
| 1880 | nvidia,emc-configuration = < 0x0000000c |
| 1881 | 0x0000001a 0x00000008 0x00000003 0x00000005 |
| 1882 | 0x00000004 0x00000001 0x00000006 0x00000003 |
| 1883 | 0x00000003 0x00000002 0x00000002 0x00000000 |
| 1884 | 0x00000001 0x00000003 0x00000001 0x0000000c |
| 1885 | 0x0000000a 0x00000303 0x00000000 0x000000c0 |
| 1886 | 0x00000001 0x00000001 0x00000003 0x00000000 |
| 1887 | 0x00000001 0x00000007 0x0000001d 0x0000001d |
| 1888 | 0x00000004 0x0000000b 0x00000005 0x00000004 |
| 1889 | 0x00000002 0x00000351 0x00000004 0x00000006 |
| 1890 | 0x00000000 0x00000000 0x00004282 0x004400a4 |
| 1891 | 0x00008000 0x00080000 0x00080000 0x00080000 |
| 1892 | 0x00080000 0x00080000 0x00080000 0x00080000 |
| 1893 | 0x00080000 0x00000000 0x00000000 0x00000000 |
| 1894 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 1895 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 1896 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 1897 | 0x00000000 0x00080000 0x00080000 0x00080000 |
| 1898 | 0x00080000 0x000e0220 0x0800201c 0x00000000 |
| 1899 | 0x77ffc004 0x01f1f008 0x00000000 0x00000007 |
| 1900 | 0x08000068 0x08000000 0x00000802 0x00064000 |
| 1901 | 0x0000004a 0x00090009 0xa0f10000 0x00000000 |
| 1902 | 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; |
| 1903 | }; |
| 1904 | |
| 1905 | timing-400000000 { |
| 1906 | clock-frequency = <400000000>; |
| 1907 | |
| 1908 | nvidia,emc-auto-cal-interval = <0x001fffff>; |
| 1909 | nvidia,emc-mode-1 = <0x00010082>; |
| 1910 | nvidia,emc-mode-2 = <0x00020004>; |
| 1911 | nvidia,emc-mode-reset = <0x00000000>; |
| 1912 | nvidia,emc-zcal-cnt-long = <0x00000024>; |
| 1913 | nvidia,emc-cfg-periodic-qrst; |
| 1914 | |
| 1915 | nvidia,emc-configuration = < 0x00000017 |
| 1916 | 0x00000033 0x00000010 0x00000007 0x00000007 |
| 1917 | 0x00000007 0x00000002 0x0000000a 0x00000007 |
| 1918 | 0x00000007 0x00000003 0x00000002 0x00000000 |
| 1919 | 0x00000003 0x00000007 0x00000004 0x0000000d |
| 1920 | 0x0000000e 0x000005e9 0x00000000 0x0000017a |
| 1921 | 0x00000002 0x00000002 0x00000007 0x00000000 |
| 1922 | 0x00000001 0x0000000c 0x00000038 0x00000038 |
| 1923 | 0x00000006 0x00000014 0x00000009 0x00000004 |
| 1924 | 0x00000002 0x00000680 0x00000000 0x00000006 |
| 1925 | 0x00000000 0x00000000 0x00006282 0x001d0084 |
| 1926 | 0x00008000 0x00034000 0x00034000 0x00034000 |
| 1927 | 0x00034000 0x00034000 0x00034000 0x00034000 |
| 1928 | 0x00034000 0x00000000 0x00000000 0x00000000 |
| 1929 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 1930 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 1931 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 1932 | 0x00000000 0x00038000 0x00038000 0x00038000 |
| 1933 | 0x00038000 0x00080220 0x0800003d 0x00000000 |
| 1934 | 0x77ffc004 0x01f1f408 0x00000000 0x00000007 |
| 1935 | 0x08000068 0x08000000 0x00000802 0x00064000 |
| 1936 | 0x00000090 0x000c000c 0xa0f10404 0x00000000 |
| 1937 | 0x00000000 0x80000ce6 0xe0000000 0xff00ff88 >; |
| 1938 | }; |
| 1939 | }; |
| 1940 | |
| 1941 | emc-timings-1 { |
| 1942 | /* ELPIDA EDB8132B2MA 8D_F */ |
| 1943 | nvidia,ram-code = <1>; |
| 1944 | |
| 1945 | timing-25500000 { |
| 1946 | clock-frequency = <25500000>; |
| 1947 | |
| 1948 | nvidia,emc-auto-cal-interval = <0x001fffff>; |
| 1949 | nvidia,emc-mode-1 = <0x00010022>; |
| 1950 | nvidia,emc-mode-2 = <0x00020001>; |
| 1951 | nvidia,emc-mode-reset = <0x00000000>; |
| 1952 | nvidia,emc-zcal-cnt-long = <0x00000009>; |
| 1953 | nvidia,emc-cfg-dyn-self-ref; |
| 1954 | nvidia,emc-cfg-periodic-qrst; |
| 1955 | |
| 1956 | nvidia,emc-configuration = < 0x00000001 |
| 1957 | 0x00000003 0x00000002 0x00000002 0x00000004 |
| 1958 | 0x00000004 0x00000001 0x00000005 0x00000002 |
| 1959 | 0x00000002 0x00000001 0x00000001 0x00000000 |
| 1960 | 0x00000001 0x00000003 0x00000001 0x0000000b |
| 1961 | 0x0000000a 0x00000060 0x00000000 0x00000018 |
| 1962 | 0x00000001 0x00000001 0x00000002 0x00000000 |
| 1963 | 0x00000001 0x00000007 0x00000004 0x00000004 |
| 1964 | 0x00000003 0x00000008 0x00000004 0x00000004 |
| 1965 | 0x00000002 0x0000006b 0x00000004 0x00000004 |
| 1966 | 0x00000000 0x00000000 0x00004282 0x007800a4 |
| 1967 | 0x00008000 0x000fc000 0x000fc000 0x000fc000 |
| 1968 | 0x000fc000 0x000fc000 0x000fc000 0x000fc000 |
| 1969 | 0x000fc000 0x00000000 0x00000000 0x00000000 |
| 1970 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 1971 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 1972 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 1973 | 0x00000000 0x000fc000 0x000fc000 0x000fc000 |
| 1974 | 0x000fc000 0x00100220 0x0800201c 0x00000000 |
| 1975 | 0x77ffc004 0x01f1f008 0x00000000 0x00000007 |
| 1976 | 0x08000068 0x08000000 0x00000802 0x00064000 |
| 1977 | 0x0000000a 0x00090009 0xa0f10000 0x00000000 |
| 1978 | 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; |
| 1979 | }; |
| 1980 | |
| 1981 | timing-51000000 { |
| 1982 | clock-frequency = <51000000>; |
| 1983 | |
| 1984 | nvidia,emc-auto-cal-interval = <0x001fffff>; |
| 1985 | nvidia,emc-mode-1 = <0x00010022>; |
| 1986 | nvidia,emc-mode-2 = <0x00020001>; |
| 1987 | nvidia,emc-mode-reset = <0x00000000>; |
| 1988 | nvidia,emc-zcal-cnt-long = <0x00000009>; |
| 1989 | nvidia,emc-cfg-dyn-self-ref; |
| 1990 | nvidia,emc-cfg-periodic-qrst; |
| 1991 | |
| 1992 | nvidia,emc-configuration = < 0x00000003 |
| 1993 | 0x00000006 0x00000002 0x00000002 0x00000004 |
| 1994 | 0x00000004 0x00000001 0x00000005 0x00000002 |
| 1995 | 0x00000002 0x00000001 0x00000001 0x00000000 |
| 1996 | 0x00000001 0x00000003 0x00000001 0x0000000b |
| 1997 | 0x0000000a 0x000000c0 0x00000000 0x00000030 |
| 1998 | 0x00000001 0x00000001 0x00000002 0x00000000 |
| 1999 | 0x00000001 0x00000007 0x00000008 0x00000008 |
| 2000 | 0x00000003 0x00000008 0x00000004 0x00000004 |
| 2001 | 0x00000002 0x000000d5 0x00000004 0x00000004 |
| 2002 | 0x00000000 0x00000000 0x00004282 0x007800a4 |
| 2003 | 0x00008000 0x000fc000 0x000fc000 0x000fc000 |
| 2004 | 0x000fc000 0x000fc000 0x000fc000 0x000fc000 |
| 2005 | 0x000fc000 0x00000000 0x00000000 0x00000000 |
| 2006 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2007 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2008 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2009 | 0x00000000 0x000fc000 0x000fc000 0x000fc000 |
| 2010 | 0x000fc000 0x00100220 0x0800201c 0x00000000 |
| 2011 | 0x77ffc004 0x01f1f008 0x00000000 0x00000007 |
| 2012 | 0x08000068 0x08000000 0x00000802 0x00064000 |
| 2013 | 0x00000013 0x00090009 0xa0f10000 0x00000000 |
| 2014 | 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; |
| 2015 | }; |
| 2016 | |
| 2017 | timing-102000000 { |
| 2018 | clock-frequency = <102000000>; |
| 2019 | |
| 2020 | nvidia,emc-auto-cal-interval = <0x001fffff>; |
| 2021 | nvidia,emc-mode-1 = <0x00010022>; |
| 2022 | nvidia,emc-mode-2 = <0x00020001>; |
| 2023 | nvidia,emc-mode-reset = <0x00000000>; |
| 2024 | nvidia,emc-zcal-cnt-long = <0x0000000a>; |
| 2025 | nvidia,emc-cfg-dyn-self-ref; |
| 2026 | nvidia,emc-cfg-periodic-qrst; |
| 2027 | |
| 2028 | nvidia,emc-configuration = < 0x00000006 |
| 2029 | 0x0000000d 0x00000004 0x00000002 0x00000004 |
| 2030 | 0x00000004 0x00000001 0x00000005 0x00000002 |
| 2031 | 0x00000002 0x00000001 0x00000001 0x00000000 |
| 2032 | 0x00000001 0x00000003 0x00000001 0x0000000b |
| 2033 | 0x0000000a 0x00000181 0x00000000 0x00000060 |
| 2034 | 0x00000001 0x00000001 0x00000002 0x00000000 |
| 2035 | 0x00000001 0x00000007 0x0000000f 0x0000000f |
| 2036 | 0x00000003 0x00000008 0x00000004 0x00000004 |
| 2037 | 0x00000002 0x000001a9 0x00000004 0x00000004 |
| 2038 | 0x00000000 0x00000000 0x00004282 0x007800a4 |
| 2039 | 0x00008000 0x000fc000 0x000fc000 0x000fc000 |
| 2040 | 0x000fc000 0x000fc000 0x000fc000 0x000fc000 |
| 2041 | 0x000fc000 0x00000000 0x00000000 0x00000000 |
| 2042 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2043 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2044 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2045 | 0x00000000 0x000fc000 0x000fc000 0x000fc000 |
| 2046 | 0x000fc000 0x00100220 0x0800201c 0x00000000 |
| 2047 | 0x77ffc004 0x01f1f008 0x00000000 0x00000007 |
| 2048 | 0x08000068 0x08000000 0x00000802 0x00064000 |
| 2049 | 0x00000025 0x00090009 0xa0f10000 0x00000000 |
| 2050 | 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; |
| 2051 | }; |
| 2052 | |
| 2053 | timing-204000000 { |
| 2054 | clock-frequency = <204000000>; |
| 2055 | |
| 2056 | nvidia,emc-auto-cal-interval = <0x001fffff>; |
| 2057 | nvidia,emc-mode-1 = <0x00010042>; |
| 2058 | nvidia,emc-mode-2 = <0x00020001>; |
| 2059 | nvidia,emc-mode-reset = <0x00000000>; |
| 2060 | nvidia,emc-zcal-cnt-long = <0x00000013>; |
| 2061 | nvidia,emc-cfg-dyn-self-ref; |
| 2062 | nvidia,emc-cfg-periodic-qrst; |
| 2063 | |
| 2064 | nvidia,emc-configuration = < 0x0000000c |
| 2065 | 0x0000001a 0x00000008 0x00000003 0x00000005 |
| 2066 | 0x00000004 0x00000001 0x00000006 0x00000003 |
| 2067 | 0x00000003 0x00000002 0x00000002 0x00000000 |
| 2068 | 0x00000001 0x00000003 0x00000001 0x0000000c |
| 2069 | 0x0000000a 0x00000303 0x00000000 0x000000c0 |
| 2070 | 0x00000001 0x00000001 0x00000003 0x00000000 |
| 2071 | 0x00000001 0x00000007 0x0000001d 0x0000001d |
| 2072 | 0x00000004 0x0000000b 0x00000005 0x00000004 |
| 2073 | 0x00000002 0x00000351 0x00000004 0x00000006 |
| 2074 | 0x00000000 0x00000000 0x00004282 0x004400a4 |
| 2075 | 0x00008000 0x00070000 0x00070000 0x00070000 |
| 2076 | 0x00070000 0x00070000 0x00070000 0x00070000 |
| 2077 | 0x00070000 0x00000000 0x00000000 0x00000000 |
| 2078 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2079 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2080 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2081 | 0x00000000 0x00080000 0x00080000 0x00080000 |
| 2082 | 0x00080000 0x000e0220 0x0800201c 0x00000000 |
| 2083 | 0x77ffc004 0x01f1f008 0x00000000 0x00000007 |
| 2084 | 0x08000068 0x08000000 0x00000802 0x00064000 |
| 2085 | 0x0000004a 0x00090009 0xa0f10000 0x00000000 |
| 2086 | 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; |
| 2087 | }; |
| 2088 | |
| 2089 | timing-400000000 { |
| 2090 | clock-frequency = <400000000>; |
| 2091 | |
| 2092 | nvidia,emc-auto-cal-interval = <0x001fffff>; |
| 2093 | nvidia,emc-mode-1 = <0x00010082>; |
| 2094 | nvidia,emc-mode-2 = <0x00020004>; |
| 2095 | nvidia,emc-mode-reset = <0x00000000>; |
| 2096 | nvidia,emc-zcal-cnt-long = <0x00000024>; |
| 2097 | nvidia,emc-cfg-periodic-qrst; |
| 2098 | |
| 2099 | nvidia,emc-configuration = < 0x00000017 |
| 2100 | 0x00000033 0x00000010 0x00000007 0x00000007 |
| 2101 | 0x00000007 0x00000002 0x0000000a 0x00000007 |
| 2102 | 0x00000007 0x00000003 0x00000002 0x00000000 |
| 2103 | 0x00000003 0x00000007 0x00000004 0x0000000d |
| 2104 | 0x0000000e 0x000005e9 0x00000000 0x0000017a |
| 2105 | 0x00000002 0x00000002 0x00000007 0x00000000 |
| 2106 | 0x00000001 0x0000000c 0x00000038 0x00000038 |
| 2107 | 0x00000006 0x00000014 0x00000009 0x00000004 |
| 2108 | 0x00000002 0x00000680 0x00000000 0x00000004 |
| 2109 | 0x00000000 0x00000000 0x00006282 0x001d0084 |
| 2110 | 0x00008000 0x00034000 0x00034000 0x00034000 |
| 2111 | 0x00034000 0x00034000 0x00034000 0x00034000 |
| 2112 | 0x00034000 0x00000000 0x00000000 0x00000000 |
| 2113 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2114 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2115 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2116 | 0x00000000 0x00048000 0x00048000 0x00048000 |
| 2117 | 0x00048000 0x00060220 0x0800003d 0x00000000 |
| 2118 | 0x77ffc004 0x01f1f408 0x00000000 0x00000007 |
| 2119 | 0x08000068 0x08000000 0x00000802 0x00064000 |
| 2120 | 0x00000090 0x000c000c 0xa0f10000 0x00000000 |
| 2121 | 0x00000000 0x80000ce6 0xe0000000 0xff00ff88 >; |
| 2122 | }; |
| 2123 | }; |
| 2124 | |
| 2125 | emc-timings-2 { |
| 2126 | /* SAMSUNG K4P8G304EB FGC2 */ |
| 2127 | nvidia,ram-code = <2>; |
| 2128 | |
| 2129 | timing-25500000 { |
| 2130 | clock-frequency = <25500000>; |
| 2131 | |
| 2132 | nvidia,emc-auto-cal-interval = <0x001fffff>; |
| 2133 | nvidia,emc-mode-1 = <0x00010022>; |
| 2134 | nvidia,emc-mode-2 = <0x00020001>; |
| 2135 | nvidia,emc-mode-reset = <0x00000000>; |
| 2136 | nvidia,emc-zcal-cnt-long = <0x00000009>; |
| 2137 | nvidia,emc-cfg-dyn-self-ref; |
| 2138 | nvidia,emc-cfg-periodic-qrst; |
| 2139 | |
| 2140 | nvidia,emc-configuration = < 0x00000001 |
| 2141 | 0x00000003 0x00000002 0x00000002 0x00000004 |
| 2142 | 0x00000004 0x00000001 0x00000005 0x00000002 |
| 2143 | 0x00000002 0x00000001 0x00000001 0x00000000 |
| 2144 | 0x00000001 0x00000003 0x00000001 0x0000000b |
| 2145 | 0x0000000a 0x00000060 0x00000000 0x00000018 |
| 2146 | 0x00000001 0x00000001 0x00000002 0x00000000 |
| 2147 | 0x00000001 0x00000007 0x00000004 0x00000004 |
| 2148 | 0x00000003 0x00000008 0x00000004 0x00000004 |
| 2149 | 0x00000002 0x0000006b 0x00000004 0x00000004 |
| 2150 | 0x00000000 0x00000000 0x00004282 0x007800a4 |
| 2151 | 0x00008000 0x000fc000 0x000fc000 0x000fc000 |
| 2152 | 0x000fc000 0x000fc000 0x000fc000 0x000fc000 |
| 2153 | 0x000fc000 0x00000000 0x00000000 0x00000000 |
| 2154 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2155 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2156 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2157 | 0x00000000 0x000fc000 0x000fc000 0x000fc000 |
| 2158 | 0x000fc000 0x00100220 0x0800201c 0x00000000 |
| 2159 | 0x77ffc004 0x01f1f008 0x00000000 0x00000007 |
| 2160 | 0x08000068 0x08000000 0x00000802 0x00064000 |
| 2161 | 0x0000000a 0x00090009 0xa0f10000 0x00000000 |
| 2162 | 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; |
| 2163 | }; |
| 2164 | |
| 2165 | timing-51000000 { |
| 2166 | clock-frequency = <51000000>; |
| 2167 | |
| 2168 | nvidia,emc-auto-cal-interval = <0x001fffff>; |
| 2169 | nvidia,emc-mode-1 = <0x00010022>; |
| 2170 | nvidia,emc-mode-2 = <0x00020001>; |
| 2171 | nvidia,emc-mode-reset = <0x00000000>; |
| 2172 | nvidia,emc-zcal-cnt-long = <0x00000009>; |
| 2173 | nvidia,emc-cfg-dyn-self-ref; |
| 2174 | nvidia,emc-cfg-periodic-qrst; |
| 2175 | |
| 2176 | nvidia,emc-configuration = < 0x00000003 |
| 2177 | 0x00000006 0x00000002 0x00000002 0x00000004 |
| 2178 | 0x00000004 0x00000001 0x00000005 0x00000002 |
| 2179 | 0x00000002 0x00000001 0x00000001 0x00000000 |
| 2180 | 0x00000001 0x00000003 0x00000001 0x0000000b |
| 2181 | 0x0000000a 0x000000c0 0x00000000 0x00000030 |
| 2182 | 0x00000001 0x00000001 0x00000002 0x00000000 |
| 2183 | 0x00000001 0x00000007 0x00000008 0x00000008 |
| 2184 | 0x00000003 0x00000008 0x00000004 0x00000004 |
| 2185 | 0x00000002 0x000000d5 0x00000004 0x00000004 |
| 2186 | 0x00000000 0x00000000 0x00004282 0x007800a4 |
| 2187 | 0x00008000 0x000fc000 0x000fc000 0x000fc000 |
| 2188 | 0x000fc000 0x000fc000 0x000fc000 0x000fc000 |
| 2189 | 0x000fc000 0x00000000 0x00000000 0x00000000 |
| 2190 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2191 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2192 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2193 | 0x00000000 0x000fc000 0x000fc000 0x000fc000 |
| 2194 | 0x000fc000 0x00100220 0x0800201c 0x00000000 |
| 2195 | 0x77ffc004 0x01f1f008 0x00000000 0x00000007 |
| 2196 | 0x08000068 0x08000000 0x00000802 0x00064000 |
| 2197 | 0x00000013 0x00090009 0xa0f10000 0x00000000 |
| 2198 | 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; |
| 2199 | }; |
| 2200 | |
| 2201 | timing-102000000 { |
| 2202 | clock-frequency = <102000000>; |
| 2203 | |
| 2204 | nvidia,emc-auto-cal-interval = <0x001fffff>; |
| 2205 | nvidia,emc-mode-1 = <0x00010022>; |
| 2206 | nvidia,emc-mode-2 = <0x00020001>; |
| 2207 | nvidia,emc-mode-reset = <0x00000000>; |
| 2208 | nvidia,emc-zcal-cnt-long = <0x0000000a>; |
| 2209 | nvidia,emc-cfg-dyn-self-ref; |
| 2210 | nvidia,emc-cfg-periodic-qrst; |
| 2211 | |
| 2212 | nvidia,emc-configuration = < 0x00000006 |
| 2213 | 0x0000000d 0x00000004 0x00000002 0x00000004 |
| 2214 | 0x00000004 0x00000001 0x00000005 0x00000002 |
| 2215 | 0x00000002 0x00000001 0x00000001 0x00000000 |
| 2216 | 0x00000001 0x00000003 0x00000001 0x0000000b |
| 2217 | 0x00000009 0x00000181 0x00000000 0x00000060 |
| 2218 | 0x00000001 0x00000001 0x00000002 0x00000000 |
| 2219 | 0x00000001 0x00000007 0x0000000f 0x0000000f |
| 2220 | 0x00000003 0x00000008 0x00000004 0x00000004 |
| 2221 | 0x00000002 0x000001a9 0x00000004 0x00000004 |
| 2222 | 0x00000000 0x00000000 0x00004282 0x007800a4 |
| 2223 | 0x00008000 0x000fc000 0x000fc000 0x000fc000 |
| 2224 | 0x000fc000 0x000fc000 0x000fc000 0x000fc000 |
| 2225 | 0x000fc000 0x00000000 0x00000000 0x00000000 |
| 2226 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2227 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2228 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2229 | 0x00000000 0x000fc000 0x000fc000 0x000fc000 |
| 2230 | 0x000fc000 0x00100220 0x0800201c 0x00000000 |
| 2231 | 0x77ffc004 0x01f1f008 0x00000000 0x00000007 |
| 2232 | 0x08000068 0x08000000 0x00000802 0x00064000 |
| 2233 | 0x00000025 0x00090009 0xa0f10000 0x00000000 |
| 2234 | 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; |
| 2235 | }; |
| 2236 | |
| 2237 | timing-204000000 { |
| 2238 | clock-frequency = <204000000>; |
| 2239 | |
| 2240 | nvidia,emc-auto-cal-interval = <0x001fffff>; |
| 2241 | nvidia,emc-mode-1 = <0x00010042>; |
| 2242 | nvidia,emc-mode-2 = <0x00020001>; |
| 2243 | nvidia,emc-mode-reset = <0x00000000>; |
| 2244 | nvidia,emc-zcal-cnt-long = <0x00000013>; |
| 2245 | nvidia,emc-cfg-dyn-self-ref; |
| 2246 | nvidia,emc-cfg-periodic-qrst; |
| 2247 | |
| 2248 | nvidia,emc-configuration = < 0x0000000c |
| 2249 | 0x0000001a 0x00000008 0x00000003 0x00000005 |
| 2250 | 0x00000004 0x00000001 0x00000006 0x00000003 |
| 2251 | 0x00000003 0x00000002 0x00000002 0x00000000 |
| 2252 | 0x00000001 0x00000004 0x00000001 0x0000000c |
| 2253 | 0x0000000a 0x00000303 0x00000000 0x000000c0 |
| 2254 | 0x00000001 0x00000001 0x00000003 0x00000000 |
| 2255 | 0x00000001 0x00000007 0x0000001d 0x0000001d |
| 2256 | 0x00000004 0x0000000b 0x00000005 0x00000004 |
| 2257 | 0x00000002 0x00000351 0x00000005 0x00000004 |
| 2258 | 0x00000000 0x00000000 0x00004282 0x004400a4 |
| 2259 | 0x00008000 0x00080000 0x00080000 0x00080000 |
| 2260 | 0x00080000 0x00080000 0x00080000 0x00080000 |
| 2261 | 0x00080000 0x00000000 0x00000000 0x00000000 |
| 2262 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2263 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2264 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2265 | 0x00000000 0x00080000 0x00080000 0x00080000 |
| 2266 | 0x00080000 0x000e0220 0x0800201c 0x00000000 |
| 2267 | 0x77ffc004 0x01f1f008 0x00000000 0x00000007 |
| 2268 | 0x08000068 0x08000000 0x00000802 0x00064000 |
| 2269 | 0x0000004a 0x00090009 0xa0f10000 0x00000000 |
| 2270 | 0x00000000 0x80000713 0xe0000000 0xff00ff00 >; |
| 2271 | }; |
| 2272 | |
| 2273 | timing-533000000 { |
| 2274 | clock-frequency = <533000000>; |
| 2275 | |
| 2276 | nvidia,emc-auto-cal-interval = <0x001fffff>; |
| 2277 | nvidia,emc-mode-1 = <0x000100c2>; |
| 2278 | nvidia,emc-mode-2 = <0x00020006>; |
| 2279 | nvidia,emc-mode-reset = <0x00000000>; |
| 2280 | nvidia,emc-zcal-cnt-long = <0x00000030>; |
| 2281 | nvidia,emc-cfg-periodic-qrst; |
| 2282 | |
| 2283 | nvidia,emc-configuration = < 0x0000001f |
| 2284 | 0x00000045 0x00000016 0x00000009 0x00000008 |
| 2285 | 0x00000009 0x00000003 0x0000000d 0x00000009 |
| 2286 | 0x00000009 0x00000005 0x00000003 0x00000000 |
| 2287 | 0x00000004 0x0000000a 0x00000006 0x0000000d |
| 2288 | 0x00000010 0x000007df 0x00000000 0x000001f7 |
| 2289 | 0x00000003 0x00000003 0x00000009 0x00000000 |
| 2290 | 0x00000001 0x0000000f 0x0000004b 0x0000004b |
| 2291 | 0x00000008 0x0000001b 0x0000000c 0x00000004 |
| 2292 | 0x00000002 0x000008aa 0x00000000 0x00000004 |
| 2293 | 0x00000000 0x00000000 0x00006282 0xf0120091 |
| 2294 | 0x00008000 0x007f8008 0x007f8008 0x007f8008 |
| 2295 | 0x007f8008 0x007f8008 0x007f8008 0x007f8008 |
| 2296 | 0x007f8008 0x00000000 0x00000000 0x00000000 |
| 2297 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2298 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2299 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2300 | 0x00000000 0x0000000c 0x0000000c 0x0000000c |
| 2301 | 0x0000000c 0x00080220 0x0200003d 0x00000000 |
| 2302 | 0x77ffc004 0x01f1f408 0x00000000 0x00000007 |
| 2303 | 0x08000068 0x08000000 0x00000802 0x00064000 |
| 2304 | 0x000000c0 0x000e000e 0xa0f10000 0x00000000 |
| 2305 | 0x00000000 0x800010d9 0xf0000000 0xff00ff88 >; |
| 2306 | }; |
| 2307 | }; |
| 2308 | |
| 2309 | emc-timings-3 { |
| 2310 | /* HYNIX H9TCNNN8JDMMPR NGM */ |
| 2311 | nvidia,ram-code = <3>; |
| 2312 | |
| 2313 | timing-25500000 { |
| 2314 | clock-frequency = <25500000>; |
| 2315 | |
| 2316 | nvidia,emc-auto-cal-interval = <0x001fffff>; |
| 2317 | nvidia,emc-mode-1 = <0x00010022>; |
| 2318 | nvidia,emc-mode-2 = <0x00020001>; |
| 2319 | nvidia,emc-mode-reset = <0x00000000>; |
| 2320 | nvidia,emc-zcal-cnt-long = <0x00000009>; |
| 2321 | nvidia,emc-cfg-dyn-self-ref; |
| 2322 | nvidia,emc-cfg-periodic-qrst; |
| 2323 | |
| 2324 | nvidia,emc-configuration = < 0x00000001 |
| 2325 | 0x00000003 0x00000002 0x00000002 0x00000004 |
| 2326 | 0x00000004 0x00000001 0x00000005 0x00000002 |
| 2327 | 0x00000002 0x00000001 0x00000001 0x00000000 |
| 2328 | 0x00000001 0x00000003 0x00000001 0x0000000b |
| 2329 | 0x0000000a 0x00000060 0x00000000 0x00000018 |
| 2330 | 0x00000001 0x00000001 0x00000002 0x00000000 |
| 2331 | 0x00000001 0x00000007 0x00000004 0x00000004 |
| 2332 | 0x00000003 0x00000008 0x00000004 0x00000004 |
| 2333 | 0x00000002 0x0000006b 0x00000004 0x00000004 |
| 2334 | 0x00000000 0x00000000 0x00004282 0x007800a4 |
| 2335 | 0x00008000 0x000fc000 0x000fc000 0x000fc000 |
| 2336 | 0x000fc000 0x000fc000 0x000fc000 0x000fc000 |
| 2337 | 0x000fc000 0x00000000 0x00000000 0x00000000 |
| 2338 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2339 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2340 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2341 | 0x00000000 0x000fc000 0x000fc000 0x000fc000 |
| 2342 | 0x000fc000 0x00100220 0x0800201c 0x00000000 |
| 2343 | 0x77ffc004 0x01f1f008 0x00000000 0x00000007 |
| 2344 | 0x08000068 0x08000000 0x00000802 0x00064000 |
| 2345 | 0x0000000a 0x00090009 0xa0f10000 0x00000000 |
| 2346 | 0x00000000 0x800001c5 0xe0000000 0xff00ff00 >; |
| 2347 | }; |
| 2348 | |
| 2349 | timing-51000000 { |
| 2350 | clock-frequency = <51000000>; |
| 2351 | |
| 2352 | nvidia,emc-auto-cal-interval = <0x001fffff>; |
| 2353 | nvidia,emc-mode-1 = <0x00010022>; |
| 2354 | nvidia,emc-mode-2 = <0x00020001>; |
| 2355 | nvidia,emc-mode-reset = <0x00000000>; |
| 2356 | nvidia,emc-zcal-cnt-long = <0x00000009>; |
| 2357 | nvidia,emc-cfg-dyn-self-ref; |
| 2358 | nvidia,emc-cfg-periodic-qrst; |
| 2359 | |
| 2360 | nvidia,emc-configuration = < 0x00000003 |
| 2361 | 0x00000006 0x00000002 0x00000002 0x00000004 |
| 2362 | 0x00000004 0x00000001 0x00000005 0x00000002 |
| 2363 | 0x00000002 0x00000001 0x00000001 0x00000000 |
| 2364 | 0x00000001 0x00000003 0x00000001 0x0000000b |
| 2365 | 0x0000000a 0x000000c0 0x00000000 0x00000030 |
| 2366 | 0x00000001 0x00000001 0x00000002 0x00000000 |
| 2367 | 0x00000001 0x00000007 0x00000008 0x00000008 |
| 2368 | 0x00000003 0x00000008 0x00000004 0x00000004 |
| 2369 | 0x00000002 0x000000d5 0x00000004 0x00000004 |
| 2370 | 0x00000000 0x00000000 0x00004282 0x007800a4 |
| 2371 | 0x00008000 0x000fc000 0x000fc000 0x000fc000 |
| 2372 | 0x000fc000 0x000fc000 0x000fc000 0x000fc000 |
| 2373 | 0x000fc000 0x00000000 0x00000000 0x00000000 |
| 2374 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2375 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2376 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2377 | 0x00000000 0x000fc000 0x000fc000 0x000fc000 |
| 2378 | 0x000fc000 0x00100220 0x0800201c 0x00000000 |
| 2379 | 0x77ffc004 0x01f1f008 0x00000000 0x00000007 |
| 2380 | 0x08000068 0x08000000 0x00000802 0x00064000 |
| 2381 | 0x00000013 0x00090009 0xa0f10000 0x00000000 |
| 2382 | 0x00000000 0x80000287 0xe0000000 0xff00ff00 >; |
| 2383 | }; |
| 2384 | |
| 2385 | timing-102000000 { |
| 2386 | clock-frequency = <102000000>; |
| 2387 | |
| 2388 | nvidia,emc-auto-cal-interval = <0x001fffff>; |
| 2389 | nvidia,emc-mode-1 = <0x00010022>; |
| 2390 | nvidia,emc-mode-2 = <0x00020001>; |
| 2391 | nvidia,emc-mode-reset = <0x00000000>; |
| 2392 | nvidia,emc-zcal-cnt-long = <0x0000000a>; |
| 2393 | nvidia,emc-cfg-dyn-self-ref; |
| 2394 | nvidia,emc-cfg-periodic-qrst; |
| 2395 | |
| 2396 | nvidia,emc-configuration = < 0x00000006 |
| 2397 | 0x0000000d 0x00000004 0x00000002 0x00000004 |
| 2398 | 0x00000004 0x00000001 0x00000005 0x00000002 |
| 2399 | 0x00000002 0x00000001 0x00000001 0x00000000 |
| 2400 | 0x00000001 0x00000003 0x00000001 0x0000000b |
| 2401 | 0x0000000a 0x00000181 0x00000000 0x00000060 |
| 2402 | 0x00000001 0x00000001 0x00000002 0x00000000 |
| 2403 | 0x00000001 0x00000007 0x0000000f 0x0000000f |
| 2404 | 0x00000003 0x00000008 0x00000004 0x00000004 |
| 2405 | 0x00000002 0x000001a9 0x00000004 0x00000004 |
| 2406 | 0x00000000 0x00000000 0x00004282 0x007800a4 |
| 2407 | 0x00008000 0x000fc000 0x000fc000 0x000fc000 |
| 2408 | 0x000fc000 0x000fc000 0x000fc000 0x000fc000 |
| 2409 | 0x000fc000 0x00000000 0x00000000 0x00000000 |
| 2410 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2411 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2412 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2413 | 0x00000000 0x000fc000 0x000fc000 0x000fc000 |
| 2414 | 0x000fc000 0x00100220 0x0800201c 0x00000000 |
| 2415 | 0x77ffc004 0x01f1f008 0x00000000 0x00000007 |
| 2416 | 0x08000068 0x08000000 0x00000802 0x00064000 |
| 2417 | 0x00000025 0x00090009 0xa0f10000 0x00000000 |
| 2418 | 0x00000000 0x8000040b 0xe0000000 0xff00ff00 >; |
| 2419 | }; |
| 2420 | |
| 2421 | timing-204000000 { |
| 2422 | clock-frequency = <204000000>; |
| 2423 | |
| 2424 | nvidia,emc-auto-cal-interval = <0x001fffff>; |
| 2425 | nvidia,emc-mode-1 = <0x00010042>; |
| 2426 | nvidia,emc-mode-2 = <0x00020001>; |
| 2427 | nvidia,emc-mode-reset = <0x00000000>; |
| 2428 | nvidia,emc-zcal-cnt-long = <0x00000013>; |
| 2429 | nvidia,emc-cfg-dyn-self-ref; |
| 2430 | nvidia,emc-cfg-periodic-qrst; |
| 2431 | |
| 2432 | nvidia,emc-configuration = < 0x0000000c |
| 2433 | 0x0000001a 0x00000008 0x00000003 0x00000005 |
| 2434 | 0x00000004 0x00000001 0x00000006 0x00000003 |
| 2435 | 0x00000003 0x00000002 0x00000002 0x00000000 |
| 2436 | 0x00000001 0x00000003 0x00000001 0x0000000c |
| 2437 | 0x0000000b 0x00000303 0x00000000 0x000000c0 |
| 2438 | 0x00000001 0x00000001 0x00000003 0x00000000 |
| 2439 | 0x00000001 0x00000007 0x0000001d 0x0000001d |
| 2440 | 0x00000004 0x0000000b 0x00000005 0x00000004 |
| 2441 | 0x00000002 0x00000351 0x00000004 0x00000006 |
| 2442 | 0x00000000 0x00000000 0x00004282 0x004400a4 |
| 2443 | 0x00008000 0x00072000 0x00072000 0x00072000 |
| 2444 | 0x00072000 0x00072000 0x00072000 0x00072000 |
| 2445 | 0x00072000 0x00000000 0x00000000 0x00000000 |
| 2446 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2447 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2448 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2449 | 0x00000000 0x00080000 0x00080000 0x00080000 |
| 2450 | 0x00080000 0x000e0220 0x0800201c 0x00000000 |
| 2451 | 0x77ffc004 0x01f1f008 0x00000000 0x00000007 |
| 2452 | 0x08000068 0x08000000 0x00000802 0x00064000 |
| 2453 | 0x0000004a 0x00090009 0xa0f10000 0x00000000 |
| 2454 | 0x00000000 0x80000713 0xd0000000 0xff00ff00 >; |
| 2455 | }; |
| 2456 | |
| 2457 | timing-533000000 { |
| 2458 | clock-frequency = <533000000>; |
| 2459 | |
| 2460 | nvidia,emc-auto-cal-interval = <0x001fffff>; |
| 2461 | nvidia,emc-mode-1 = <0x000100c2>; |
| 2462 | nvidia,emc-mode-2 = <0x00020006>; |
| 2463 | nvidia,emc-mode-reset = <0x00000000>; |
| 2464 | nvidia,emc-zcal-cnt-long = <0x00000030>; |
| 2465 | nvidia,emc-cfg-periodic-qrst; |
| 2466 | |
| 2467 | nvidia,emc-configuration = < 0x0000001f |
| 2468 | 0x00000045 0x00000016 0x00000009 0x00000008 |
| 2469 | 0x00000009 0x00000003 0x0000000d 0x00000009 |
| 2470 | 0x00000009 0x00000005 0x00000003 0x00000000 |
| 2471 | 0x00000004 0x00000009 0x00000006 0x0000000d |
| 2472 | 0x00000010 0x000007df 0x00000000 0x000001f7 |
| 2473 | 0x00000003 0x00000003 0x00000009 0x00000000 |
| 2474 | 0x00000001 0x0000000f 0x0000004b 0x0000004b |
| 2475 | 0x00000008 0x0000001b 0x0000000c 0x00000004 |
| 2476 | 0x00000002 0x000008aa 0x00000000 0x00000006 |
| 2477 | 0x00000000 0x00000000 0x00006282 0xf0120091 |
| 2478 | 0x00008000 0x0000000a 0x0000000a 0x0000000a |
| 2479 | 0x0000000a 0x0000000a 0x0000000a 0x0000000a |
| 2480 | 0x0000000a 0x00000000 0x00000000 0x00000000 |
| 2481 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2482 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2483 | 0x00000000 0x00000000 0x00000000 0x00000000 |
| 2484 | 0x00000000 0x0000000c 0x0000000c 0x0000000c |
| 2485 | 0x0000000c 0x000a0220 0x0800003d 0x00000000 |
| 2486 | 0x77ffc004 0x01f1f408 0x00000000 0x00000007 |
| 2487 | 0x08000068 0x08000000 0x00000802 0x00064000 |
| 2488 | 0x000000c0 0x000e000e 0xa0f10000 0x00000000 |
| 2489 | 0x00000000 0x800010d9 0xe0000000 0xff00ff88 >; |
| 2490 | }; |
| 2491 | }; |
| 2492 | }; |
| 2493 | |
| 2494 | hda@70030000 { |
| 2495 | status = "okay"; |
| 2496 | }; |
| 2497 | |
| 2498 | ahub@70080000 { |
| 2499 | i2s@70080400 { /* i2s1 */ |
| 2500 | status = "okay"; |
| 2501 | }; |
| 2502 | |
| 2503 | /* BT SCO */ |
| 2504 | i2s@70080600 { /* i2s3 */ |
| 2505 | status = "okay"; |
| 2506 | }; |
| 2507 | }; |
| 2508 | |
| 2509 | sdmmc1: mmc@78000000 { |
| 2510 | status = "okay"; |
| 2511 | |
| 2512 | cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; |
| 2513 | bus-width = <4>; |
| 2514 | |
| 2515 | vmmc-supply = <&vdd_usd>; /* ldo2 */ |
| 2516 | vqmmc-supply = <&vddio_usd>; /* ldo3 */ |
| 2517 | }; |
| 2518 | |
| 2519 | sdmmc3: mmc@78000400 { |
| 2520 | status = "okay"; |
| 2521 | |
| 2522 | #address-cells = <1>; |
| 2523 | #size-cells = <0>; |
| 2524 | |
| 2525 | assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; |
| 2526 | assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; |
| 2527 | assigned-clock-rates = <50000000>; |
| 2528 | |
| 2529 | max-frequency = <50000000>; |
| 2530 | keep-power-in-suspend; |
| 2531 | bus-width = <4>; |
| 2532 | non-removable; |
| 2533 | |
| 2534 | mmc-pwrseq = <&brcm_wifi_pwrseq>; |
| 2535 | vmmc-supply = <&vdd_3v3_sys>; |
| 2536 | vqmmc-supply = <&vdd_1v8_vio>; |
| 2537 | |
| 2538 | /* Azurewave AW-AH663 BCM4330B1 */ |
| 2539 | wifi@1 { |
| 2540 | compatible = "brcm,bcm4329-fmac"; |
| 2541 | reg = <1>; |
| 2542 | |
| 2543 | interrupt-parent = <&gpio>; |
| 2544 | interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_HIGH>; |
| 2545 | interrupt-names = "host-wake"; |
| 2546 | }; |
| 2547 | }; |
| 2548 | |
| 2549 | sdmmc4: mmc@78000600 { |
| 2550 | status = "okay"; |
| 2551 | bus-width = <8>; |
| 2552 | vmmc-supply = <&vcore_emmc>; |
| 2553 | vqmmc-supply = <&vdd_1v8_vio>; |
| 2554 | non-removable; |
| 2555 | }; |
| 2556 | |
| 2557 | usb@7d000000 { |
| 2558 | compatible = "nvidia,tegra30-udc"; |
| 2559 | status = "okay"; |
| 2560 | dr_mode = "otg"; |
| 2561 | vbus-supply = <&vdd_vbus_usb1>; |
| 2562 | }; |
| 2563 | |
| 2564 | usb-phy@7d000000 { |
| 2565 | status = "okay"; |
| 2566 | dr_mode = "otg"; |
| 2567 | nvidia,hssync-start-delay = <0>; |
| 2568 | nvidia,xcvr-lsfslew = <2>; |
| 2569 | nvidia,xcvr-lsrslew = <2>; |
| 2570 | }; |
| 2571 | |
| 2572 | usb@7d008000 { |
| 2573 | status = "okay"; |
| 2574 | }; |
| 2575 | |
| 2576 | usb-phy@7d008000 { |
| 2577 | status = "okay"; |
| 2578 | vbus-supply = <&vdd_vbus_usb3>; |
| 2579 | }; |
| 2580 | |
| 2581 | mains: ac-adapter-detect { |
| 2582 | compatible = "gpio-charger"; |
| 2583 | charger-type = "mains"; |
| 2584 | gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; |
| 2585 | }; |
| 2586 | |
| 2587 | backlight: backlight { |
| 2588 | compatible = "pwm-backlight"; |
| 2589 | |
| 2590 | enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; |
| 2591 | power-supply = <&vdd_5v0_bl>; |
| 2592 | pwms = <&pwm 0 5000000>; |
| 2593 | |
| 2594 | brightness-levels = <1 255>; |
| 2595 | num-interpolated-steps = <254>; |
| 2596 | default-brightness-level = <15>; |
| 2597 | }; |
| 2598 | |
| 2599 | /* PMIC has a built-in 32KHz oscillator which is used by PMC */ |
| 2600 | clk32k_in: clock-32k { |
| 2601 | compatible = "fixed-clock"; |
| 2602 | #clock-cells = <0>; |
| 2603 | clock-frequency = <32768>; |
| 2604 | clock-output-names = "pmic-oscillator"; |
| 2605 | }; |
| 2606 | |
| 2607 | cpus { |
| 2608 | cpu0: cpu@0 { |
| 2609 | cpu-supply = <&vdd_cpu>; |
| 2610 | operating-points-v2 = <&cpu0_opp_table>; |
| 2611 | #cooling-cells = <2>; |
| 2612 | }; |
| 2613 | cpu1: cpu@1 { |
| 2614 | cpu-supply = <&vdd_cpu>; |
| 2615 | operating-points-v2 = <&cpu0_opp_table>; |
| 2616 | #cooling-cells = <2>; |
| 2617 | }; |
| 2618 | cpu2: cpu@2 { |
| 2619 | cpu-supply = <&vdd_cpu>; |
| 2620 | operating-points-v2 = <&cpu0_opp_table>; |
| 2621 | #cooling-cells = <2>; |
| 2622 | }; |
| 2623 | cpu3: cpu@3 { |
| 2624 | cpu-supply = <&vdd_cpu>; |
| 2625 | operating-points-v2 = <&cpu0_opp_table>; |
| 2626 | #cooling-cells = <2>; |
| 2627 | }; |
| 2628 | }; |
| 2629 | |
| 2630 | display-panel { |
| 2631 | compatible = "hannstar,hsd101pww2", "panel-lvds"; |
| 2632 | |
| 2633 | width-mm = <217>; |
| 2634 | height-mm = <136>; |
| 2635 | |
| 2636 | data-mapping = "jeida-24"; |
| 2637 | |
| 2638 | panel-timing { |
| 2639 | /* 1280x800@60Hz */ |
| 2640 | clock-frequency = <68000000>; |
| 2641 | hactive = <1280>; |
| 2642 | vactive = <800>; |
| 2643 | hfront-porch = <48>; |
| 2644 | hback-porch = <18>; |
| 2645 | hsync-len = <30>; |
| 2646 | vsync-len = <5>; |
| 2647 | vfront-porch = <3>; |
| 2648 | vback-porch = <12>; |
| 2649 | }; |
| 2650 | }; |
| 2651 | |
| 2652 | extcon-keys { |
| 2653 | compatible = "gpio-keys"; |
| 2654 | |
| 2655 | switch-dock-insert { |
| 2656 | label = "Chagall Dock"; |
| 2657 | gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; |
| 2658 | linux,input-type = <EV_SW>; |
| 2659 | linux,code = <SW_DOCK>; |
| 2660 | debounce-interval = <10>; |
| 2661 | wakeup-event-action = <EV_ACT_ASSERTED>; |
| 2662 | wakeup-source; |
| 2663 | }; |
| 2664 | |
| 2665 | switch-lineout-detect { |
| 2666 | label = "Audio dock line-out detect"; |
| 2667 | gpios = <&gpio TEGRA_GPIO(S, 3) GPIO_ACTIVE_LOW>; |
| 2668 | linux,input-type = <EV_SW>; |
| 2669 | linux,code = <SW_LINEOUT_INSERT>; |
| 2670 | debounce-interval = <10>; |
| 2671 | wakeup-event-action = <EV_ACT_ASSERTED>; |
| 2672 | wakeup-source; |
| 2673 | }; |
| 2674 | }; |
| 2675 | |
| 2676 | gpio-keys { |
| 2677 | compatible = "gpio-keys"; |
| 2678 | |
| 2679 | key-power { |
| 2680 | label = "Power"; |
| 2681 | gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; |
| 2682 | linux,code = <KEY_POWER>; |
| 2683 | debounce-interval = <10>; |
| 2684 | wakeup-event-action = <EV_ACT_ASSERTED>; |
| 2685 | wakeup-source; |
| 2686 | }; |
| 2687 | |
| 2688 | key-volume-down { |
| 2689 | label = "Volume Down"; |
| 2690 | gpios = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_LOW>; |
| 2691 | linux,code = <KEY_VOLUMEDOWN>; |
| 2692 | debounce-interval = <10>; |
| 2693 | wakeup-event-action = <EV_ACT_ASSERTED>; |
| 2694 | wakeup-source; |
| 2695 | }; |
| 2696 | |
| 2697 | key-volume-up { |
| 2698 | label = "Volume Up"; |
| 2699 | gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; |
| 2700 | linux,code = <KEY_VOLUMEUP>; |
| 2701 | debounce-interval = <10>; |
| 2702 | wakeup-event-action = <EV_ACT_ASSERTED>; |
| 2703 | wakeup-source; |
| 2704 | }; |
| 2705 | }; |
| 2706 | |
| 2707 | haptic-feedback { |
| 2708 | compatible = "gpio-vibrator"; |
| 2709 | enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; |
| 2710 | vcc-supply = <&vdd_3v3_sys>; |
| 2711 | }; |
| 2712 | |
| 2713 | opp-table-actmon { |
| 2714 | /delete-node/ opp-625000000; |
| 2715 | /delete-node/ opp-667000000; |
| 2716 | /delete-node/ opp-750000000; |
| 2717 | /delete-node/ opp-800000000; |
| 2718 | /delete-node/ opp-900000000; |
| 2719 | }; |
| 2720 | |
| 2721 | opp-table-emc { |
| 2722 | /delete-node/ opp-625000000-1200; |
| 2723 | /delete-node/ opp-625000000-1250; |
| 2724 | /delete-node/ opp-667000000-1200; |
| 2725 | /delete-node/ opp-750000000-1300; |
| 2726 | /delete-node/ opp-800000000-1300; |
| 2727 | /delete-node/ opp-900000000-1350; |
| 2728 | }; |
| 2729 | |
| 2730 | brcm_wifi_pwrseq: pwrseq-wifi { |
| 2731 | compatible = "mmc-pwrseq-simple"; |
| 2732 | |
| 2733 | clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; |
| 2734 | clock-names = "ext_clock"; |
| 2735 | |
| 2736 | reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>; |
| 2737 | post-power-on-delay-ms = <300>; |
| 2738 | power-off-delay-us = <300>; |
| 2739 | }; |
| 2740 | |
| 2741 | sound { |
| 2742 | compatible = "pegatron,tegra-audio-wm8903-chagall", |
| 2743 | "nvidia,tegra-audio-wm8903"; |
| 2744 | nvidia,model = "Pegatron Chagall WM8903"; |
| 2745 | |
| 2746 | nvidia,audio-routing = |
| 2747 | "Headphone Jack", "HPOUTR", |
| 2748 | "Headphone Jack", "HPOUTL", |
| 2749 | "Int Spk", "ROP", |
| 2750 | "Int Spk", "RON", |
| 2751 | "Int Spk", "LOP", |
| 2752 | "Int Spk", "LON", |
| 2753 | "IN1R", "Mic Jack", |
| 2754 | "DMICDAT", "Int Mic"; |
| 2755 | |
| 2756 | nvidia,i2s-controller = <&tegra_i2s1>; |
| 2757 | nvidia,audio-codec = <&wm8903>; |
| 2758 | |
| 2759 | nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; |
| 2760 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; |
| 2761 | nvidia,headset; |
| 2762 | |
| 2763 | clocks = <&tegra_car TEGRA30_CLK_PLL_A>, |
| 2764 | <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, |
| 2765 | <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; |
| 2766 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
| 2767 | |
| 2768 | assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, |
| 2769 | <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; |
| 2770 | |
| 2771 | assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, |
| 2772 | <&tegra_car TEGRA30_CLK_EXTERN1>; |
| 2773 | }; |
| 2774 | |
| 2775 | thermal-zones { |
| 2776 | /* |
| 2777 | * NCT72 has two sensors: |
| 2778 | * |
| 2779 | * 0: internal that monitors ambient/skin temperature |
| 2780 | * 1: external that is connected to the CPU's diode |
| 2781 | * |
| 2782 | * Ideally we should use userspace thermal governor, |
| 2783 | * but it's a much more complex solution. The "skin" |
| 2784 | * zone exists as a simpler solution which prevents |
| 2785 | * Chagall from getting too hot from a user's tactile |
| 2786 | * perspective. The CPU zone is intended to protect |
| 2787 | * silicon from damage. |
| 2788 | */ |
| 2789 | |
| 2790 | skin-thermal { |
| 2791 | polling-delay-passive = <1000>; /* milliseconds */ |
| 2792 | polling-delay = <5000>; /* milliseconds */ |
| 2793 | |
| 2794 | thermal-sensors = <&nct72 0>; |
| 2795 | |
| 2796 | trips { |
| 2797 | trip0: skin-alert { |
| 2798 | /* throttle at 57C until temperature drops to 56.8C */ |
| 2799 | temperature = <57000>; |
| 2800 | hysteresis = <200>; |
| 2801 | type = "passive"; |
| 2802 | }; |
| 2803 | |
| 2804 | trip1: skin-crit { |
| 2805 | /* shut down at 65C */ |
| 2806 | temperature = <65000>; |
| 2807 | hysteresis = <2000>; |
| 2808 | type = "critical"; |
| 2809 | }; |
| 2810 | }; |
| 2811 | |
| 2812 | cooling-maps { |
| 2813 | map0 { |
| 2814 | trip = <&trip0>; |
| 2815 | cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| 2816 | <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| 2817 | <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| 2818 | <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| 2819 | <&actmon THERMAL_NO_LIMIT |
| 2820 | THERMAL_NO_LIMIT>; |
| 2821 | }; |
| 2822 | }; |
| 2823 | }; |
| 2824 | |
| 2825 | cpu-thermal { |
| 2826 | polling-delay-passive = <1000>; /* milliseconds */ |
| 2827 | polling-delay = <5000>; /* milliseconds */ |
| 2828 | |
| 2829 | thermal-sensors = <&nct72 1>; |
| 2830 | |
| 2831 | trips { |
| 2832 | trip2: cpu-alert { |
| 2833 | /* throttle at 85C until temperature drops to 84.8C */ |
| 2834 | temperature = <85000>; |
| 2835 | hysteresis = <200>; |
| 2836 | type = "passive"; |
| 2837 | }; |
| 2838 | |
| 2839 | trip3: cpu-crit { |
| 2840 | /* shut down at 90C */ |
| 2841 | temperature = <90000>; |
| 2842 | hysteresis = <2000>; |
| 2843 | type = "critical"; |
| 2844 | }; |
| 2845 | }; |
| 2846 | |
| 2847 | cooling-maps { |
| 2848 | map1 { |
| 2849 | trip = <&trip2>; |
| 2850 | cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| 2851 | <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| 2852 | <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| 2853 | <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| 2854 | <&actmon THERMAL_NO_LIMIT |
| 2855 | THERMAL_NO_LIMIT>; |
| 2856 | }; |
| 2857 | }; |
| 2858 | }; |
| 2859 | }; |
| 2860 | }; |