blob: 318289b76bcd7ba2b1de06e4deecdb09bb48d2ed [file] [log] [blame]
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -03001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2021 Collabora Ltd.
4 */
5
6#ifndef __IMX8MN_VAR_SOM_H
7#define __IMX8MN_VAR_SOM_H
8
9#include <linux/sizes.h>
10#include <linux/stringify.h>
11#include <asm/arch/imx-regs.h>
12
13#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
14
15#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K)
16#define CONFIG_SYS_MONITOR_LEN SZ_512K
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -030017#define CONFIG_SYS_UBOOT_BASE \
18 (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
19
20#define CONFIG_SPL_STACK 0x980000
21#define CONFIG_SPL_BSS_START_ADDR 0x950000
22#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K
23#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
24#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
25
26#define BOOT_TARGET_DEVICES(func) \
27 func(MMC, mmc, 1) \
28 func(MMC, mmc, 2) \
29 func(MMC, mmc, 0) \
30 func(PXE, pxe, na) \
31 func(DHCP, dhcp, na) \
32
33#include <config_distro_bootcmd.h>
34
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -030035#define MEM_LAYOUT_ENV_SETTINGS \
36 "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
37 "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
38 "ramdisk_addr_r=0x43800000\0" \
39 "fdt_addr_r=0x43000000\0" \
40 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
41 "fastboot_partition_alias_all=" \
42 __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) ".0:0\0" \
43 "fastboot_partition_alias_bootloader=" \
44 __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) ".1:0\0" \
45 "emmc_dev=" __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) "\0" \
46 "emmc_ack=1\0" \
47 "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
48
49/* Initial environment variables */
50#define CONFIG_EXTRA_ENV_SETTINGS \
51 MEM_LAYOUT_ENV_SETTINGS \
52 BOOTENV
53
54/* Link Definitions */
55
56#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
57#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
58#define CONFIG_SYS_INIT_SP_OFFSET \
59 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
60#define CONFIG_SYS_INIT_SP_ADDR \
61 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
62
63#define CONFIG_SYS_SDRAM_BASE 0x40000000
64#define PHYS_SDRAM 0x40000000
65#define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */
66
67#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR
68
69/* Monitor Command Prompt */
70#define CONFIG_SYS_CBSIZE SZ_2K
71#define CONFIG_SYS_MAXARGS 64
72#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
73#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
74 sizeof(CONFIG_SYS_PROMPT) + 16)
75
76/* USDHC */
77#define CONFIG_SYS_FSL_ESDHC_ADDR 0
78
Ariel D'Alessandrob6d5e132021-11-23 13:33:30 -030079#endif /* __IMX8MN_VAR_SOM_H */