blob: 1234399f33b36ef6695f66b4dfb240fabfcdc555 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Patrice Chotardf2505b12017-09-05 11:04:24 +02002/*
3 * STiH407 family DWC3 specific Glue layer
4 *
Patrice Chotard9e216242017-10-23 09:53:57 +02005 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
Patrice Chotard5d9950d2020-12-02 18:47:30 +01006 * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
Patrice Chotardf2505b12017-09-05 11:04:24 +02007 */
8
9#include <common.h>
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Patrice Chotardf2505b12017-09-05 11:04:24 +020011#include <asm/io.h>
12#include <dm.h>
13#include <errno.h>
Patrice Chotardf2505b12017-09-05 11:04:24 +020014#include <dm/lists.h>
15#include <regmap.h>
16#include <reset-uclass.h>
17#include <syscon.h>
18#include <usb.h>
19
20#include <linux/usb/dwc3.h>
21#include <linux/usb/otg.h>
22#include <dwc3-sti-glue.h>
23
24DECLARE_GLOBAL_DATA_PTR;
25
26/*
Simon Glassb75b15b2020-12-03 16:55:23 -070027 * struct sti_dwc3_glue_plat - dwc3 STi glue driver private structure
Patrice Chotardf2505b12017-09-05 11:04:24 +020028 * @syscfg_base: addr for the glue syscfg
29 * @glue_base: addr for the glue registers
30 * @syscfg_offset: usb syscfg control offset
31 * @powerdown_ctl: rest controller for powerdown signal
32 * @softreset_ctl: reset controller for softreset signal
33 * @mode: drd static host/device config
34 */
Simon Glassb75b15b2020-12-03 16:55:23 -070035struct sti_dwc3_glue_plat {
Patrice Chotardf2505b12017-09-05 11:04:24 +020036 phys_addr_t syscfg_base;
37 phys_addr_t glue_base;
38 phys_addr_t syscfg_offset;
39 struct reset_ctl powerdown_ctl;
40 struct reset_ctl softreset_ctl;
41 enum usb_dr_mode mode;
42};
43
Simon Glassb75b15b2020-12-03 16:55:23 -070044static int sti_dwc3_glue_drd_init(struct sti_dwc3_glue_plat *plat)
Patrice Chotardf2505b12017-09-05 11:04:24 +020045{
46 unsigned long val;
47
48 val = readl(plat->syscfg_base + plat->syscfg_offset);
49
50 val &= USB3_CONTROL_MASK;
51
52 switch (plat->mode) {
53 case USB_DR_MODE_PERIPHERAL:
54 val &= ~(USB3_DELAY_VBUSVALID
55 | USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3)
56 | USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2
57 | USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2);
58
59 val |= USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID;
60 break;
61
62 case USB_DR_MODE_HOST:
63 val &= ~(USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID
64 | USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3)
65 | USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2
66 | USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2);
67
68 val |= USB3_DELAY_VBUSVALID;
69 break;
70
71 default:
Masahiro Yamada81e10422017-09-16 14:10:41 +090072 pr_err("Unsupported mode of operation %d\n", plat->mode);
Patrice Chotardf2505b12017-09-05 11:04:24 +020073 return -EINVAL;
74 }
75 writel(val, plat->syscfg_base + plat->syscfg_offset);
76
77 return 0;
78}
79
Simon Glassb75b15b2020-12-03 16:55:23 -070080static void sti_dwc3_glue_init(struct sti_dwc3_glue_plat *plat)
Patrice Chotardf2505b12017-09-05 11:04:24 +020081{
82 unsigned long reg;
83
84 reg = readl(plat->glue_base + CLKRST_CTRL);
85
86 reg |= AUX_CLK_EN | EXT_CFG_RESET_N | XHCI_REVISION;
87 reg &= ~SW_PIPEW_RESET_N;
88
89 writel(reg, plat->glue_base + CLKRST_CTRL);
90
91 /* configure mux for vbus, powerpresent and bvalid signals */
92 reg = readl(plat->glue_base + USB2_VBUS_MNGMNT_SEL1);
93
94 reg |= SEL_OVERRIDE_VBUSVALID(USB2_VBUS_UTMIOTG) |
95 SEL_OVERRIDE_POWERPRESENT(USB2_VBUS_UTMIOTG) |
96 SEL_OVERRIDE_BVALID(USB2_VBUS_UTMIOTG);
97
98 writel(reg, plat->glue_base + USB2_VBUS_MNGMNT_SEL1);
99
100 setbits_le32(plat->glue_base + CLKRST_CTRL, SW_PIPEW_RESET_N);
101}
102
Simon Glassaad29ae2020-12-03 16:55:21 -0700103static int sti_dwc3_glue_of_to_plat(struct udevice *dev)
Patrice Chotardf2505b12017-09-05 11:04:24 +0200104{
Simon Glassb75b15b2020-12-03 16:55:23 -0700105 struct sti_dwc3_glue_plat *plat = dev_get_plat(dev);
Patrice Chotardf2505b12017-09-05 11:04:24 +0200106 struct udevice *syscon;
107 struct regmap *regmap;
108 int ret;
109 u32 reg[4];
110
Simon Glassa7ece582020-12-19 10:40:14 -0700111 ret = ofnode_read_u32_array(dev_ofnode(dev), "reg", reg,
112 ARRAY_SIZE(reg));
Patrice Chotardf2505b12017-09-05 11:04:24 +0200113 if (ret) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900114 pr_err("unable to find st,stih407-dwc3 reg property(%d)\n", ret);
Patrice Chotardf2505b12017-09-05 11:04:24 +0200115 return ret;
116 }
117
118 plat->glue_base = reg[0];
119 plat->syscfg_offset = reg[2];
120
121 /* get corresponding syscon phandle */
122 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "st,syscfg",
123 &syscon);
124 if (ret) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900125 pr_err("unable to find syscon device (%d)\n", ret);
Patrice Chotardf2505b12017-09-05 11:04:24 +0200126 return ret;
127 }
128
129 /* get syscfg-reg base address */
130 regmap = syscon_get_regmap(syscon);
131 if (!regmap) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900132 pr_err("unable to find regmap\n");
Patrice Chotardf2505b12017-09-05 11:04:24 +0200133 return -ENODEV;
134 }
Masahiro Yamada54c5ecb2018-04-19 12:14:01 +0900135 plat->syscfg_base = regmap->ranges[0].start;
Patrice Chotardf2505b12017-09-05 11:04:24 +0200136
137 /* get powerdown reset */
138 ret = reset_get_by_name(dev, "powerdown", &plat->powerdown_ctl);
139 if (ret) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900140 pr_err("can't get powerdown reset for %s (%d)", dev->name, ret);
Patrice Chotardf2505b12017-09-05 11:04:24 +0200141 return ret;
142 }
143
144 /* get softreset reset */
145 ret = reset_get_by_name(dev, "softreset", &plat->softreset_ctl);
146 if (ret)
Masahiro Yamada81e10422017-09-16 14:10:41 +0900147 pr_err("can't get soft reset for %s (%d)", dev->name, ret);
Patrice Chotardf2505b12017-09-05 11:04:24 +0200148
149 return ret;
150};
151
152static int sti_dwc3_glue_bind(struct udevice *dev)
153{
Simon Glassb75b15b2020-12-03 16:55:23 -0700154 struct sti_dwc3_glue_plat *plat = dev_get_plat(dev);
Kever Yang1b807052020-03-04 08:59:50 +0800155 ofnode node, dwc3_node;
Patrice Chotardf2505b12017-09-05 11:04:24 +0200156
Kever Yang1b807052020-03-04 08:59:50 +0800157 /* Find snps,dwc3 node from subnode */
Simon Glassa7ece582020-12-19 10:40:14 -0700158 ofnode_for_each_subnode(node, dev_ofnode(dev)) {
Kever Yang1b807052020-03-04 08:59:50 +0800159 if (ofnode_device_is_compatible(node, "snps,dwc3"))
160 dwc3_node = node;
Patrice Chotardf2505b12017-09-05 11:04:24 +0200161 }
162
Patrice Chotard7c7640a2020-06-29 11:19:02 +0200163 if (!ofnode_valid(dwc3_node)) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900164 pr_err("Can't find dwc3 subnode for %s\n", dev->name);
Patrice Chotardf2505b12017-09-05 11:04:24 +0200165 return -ENODEV;
166 }
167
168 /* retrieve the DWC3 dual role mode */
169 plat->mode = usb_get_dr_mode(dwc3_node);
170 if (plat->mode == USB_DR_MODE_UNKNOWN)
171 /* by default set dual role mode to HOST */
172 plat->mode = USB_DR_MODE_HOST;
173
174 return dm_scan_fdt_dev(dev);
175}
176
177static int sti_dwc3_glue_probe(struct udevice *dev)
178{
Simon Glassb75b15b2020-12-03 16:55:23 -0700179 struct sti_dwc3_glue_plat *plat = dev_get_plat(dev);
Patrice Chotardf2505b12017-09-05 11:04:24 +0200180 int ret;
181
182 /* deassert both powerdown and softreset */
183 ret = reset_deassert(&plat->powerdown_ctl);
184 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900185 pr_err("DWC3 powerdown reset deassert failed: %d", ret);
Patrice Chotardf2505b12017-09-05 11:04:24 +0200186 return ret;
187 }
188
189 ret = reset_deassert(&plat->softreset_ctl);
190 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900191 pr_err("DWC3 soft reset deassert failed: %d", ret);
Patrice Chotardf2505b12017-09-05 11:04:24 +0200192 goto softreset_err;
193 }
194
195 ret = sti_dwc3_glue_drd_init(plat);
196 if (ret)
197 goto init_err;
198
199 sti_dwc3_glue_init(plat);
200
201 return 0;
202
203init_err:
204 ret = reset_assert(&plat->softreset_ctl);
205 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900206 pr_err("DWC3 soft reset deassert failed: %d", ret);
Patrice Chotardf2505b12017-09-05 11:04:24 +0200207 return ret;
208 }
209
210softreset_err:
211 ret = reset_assert(&plat->powerdown_ctl);
212 if (ret < 0)
Masahiro Yamada81e10422017-09-16 14:10:41 +0900213 pr_err("DWC3 powerdown reset deassert failed: %d", ret);
Patrice Chotardf2505b12017-09-05 11:04:24 +0200214
215 return ret;
216}
217
218static int sti_dwc3_glue_remove(struct udevice *dev)
219{
Simon Glassb75b15b2020-12-03 16:55:23 -0700220 struct sti_dwc3_glue_plat *plat = dev_get_plat(dev);
Patrice Chotardf2505b12017-09-05 11:04:24 +0200221 int ret;
222
223 /* assert both powerdown and softreset */
224 ret = reset_assert(&plat->powerdown_ctl);
225 if (ret < 0) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900226 pr_err("DWC3 powerdown reset deassert failed: %d", ret);
Patrice Chotardf2505b12017-09-05 11:04:24 +0200227 return ret;
228 }
229
230 ret = reset_assert(&plat->softreset_ctl);
231 if (ret < 0)
Masahiro Yamada81e10422017-09-16 14:10:41 +0900232 pr_err("DWC3 soft reset deassert failed: %d", ret);
Patrice Chotardf2505b12017-09-05 11:04:24 +0200233
234 return ret;
235}
236
237static const struct udevice_id sti_dwc3_glue_ids[] = {
238 { .compatible = "st,stih407-dwc3" },
239 { }
240};
241
242U_BOOT_DRIVER(dwc3_sti_glue) = {
243 .name = "dwc3_sti_glue",
Patrice Chotard190ee832020-04-28 13:49:50 +0200244 .id = UCLASS_NOP,
Patrice Chotardf2505b12017-09-05 11:04:24 +0200245 .of_match = sti_dwc3_glue_ids,
Simon Glassaad29ae2020-12-03 16:55:21 -0700246 .of_to_plat = sti_dwc3_glue_of_to_plat,
Patrice Chotardf2505b12017-09-05 11:04:24 +0200247 .probe = sti_dwc3_glue_probe,
248 .remove = sti_dwc3_glue_remove,
249 .bind = sti_dwc3_glue_bind,
Simon Glassb75b15b2020-12-03 16:55:23 -0700250 .plat_auto = sizeof(struct sti_dwc3_glue_plat),
Patrice Chotardf2505b12017-09-05 11:04:24 +0200251 .flags = DM_FLAG_ALLOC_PRIV_DMA,
252};