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Helmut Raigere5ecbb72011-10-27 01:31:15 +00001/*
2 * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at>
3 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
4 *
5 * Configuration settings for the HALE TT-01 board.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29#include <asm/arch/imx-regs.h>
30
31/* High Level Configuration Options */
32#define CONFIG_ARM1136
33#define CONFIG_MX31
34#define CONFIG_MX31_HCLK_FREQ 26000000
35#define CONFIG_MX31_CLK32 32768
36
37#define CONFIG_DISPLAY_CPUINFO
38#define CONFIG_DISPLAY_BOARDINFO
39
40#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
41#define CONFIG_SETUP_MEMORY_TAGS
42#define CONFIG_INITRD_TAG
43
44#define CONFIG_MACH_TYPE 3726 /* not yet in mach-types.h */
45#define CONFIG_SYS_TEXT_BASE 0xA0000000
46
47
48/*
49 * Physical Memory Map:
50 * CS settings are defined by i.MX31:
51 * - CSD0 and CDS1 are 256MB each, starting at 0x80000000 and 0x9000000
52 * - CS0 and CS1 are 128MB each, at A0000000 and A8000000
53 * - CS2 to CS5 are 32MB each, at B0.., B2.., B4.., B6..
54 *
55 * HALE set-up of the bluetechnix board for now is:
56 * - 128MB DDR (2x64MB, 2x16bit), connected to 32bit DDR ram interface
57 * - NOR-Flash (Spansion 32MB MCP, Flash+16MB PSRAM), 16bit interface at CS0
58 * - S71WS256ND0BFWYM (and CS1 for 64MB S71WS512ND0 without PSRAM)
59 * the flash chip is a mirrorbit S29WS256N !
60 * - the PSRAM is hooked to CS5 (0xB6000000)
61 * - Intel Strata Flash PF48F2000P0ZB00, 16bit interface at (CS0 or) CS1
62 * - 64Mbit = 8MByte (will go away in the production set-up)
63 * - NAND-Flash NAND01GR3B2BZA6 at NAND-FC:
64 * 1Gbit=128MB, 2048+64 bytes/page, 64pages x 1024 blocks
65 * - Ethernet controller SMC9118 at CS4 via FPGA, 16bit interface
66 *
67 * u-boot will support the 32MB nor flash and the 128MB NAND flash, the PSRAM
68 * is not used right now. We should be able to reduce the SOM to NAND flash
69 * only and boot from there.
70 */
71#define CONFIG_NR_DRAM_BANKS 1
72#define PHYS_SDRAM_1 CSD0_BASE
73#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
74
75#define CONFIG_BOARD_EARLY_INIT_F
76#define CONFIG_BOARD_LATE_INIT
77
78#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
79#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
80#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
81#define CONFIG_SYS_GBL_DATA_OFFSET \
82 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
83#define CONFIG_SYS_INIT_SP_ADDR \
84 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
85
86/* default load address, 1MB up the road */
87#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1+0x100000)
88
89/* The stack sizes are set up in start.S using the settings below */
90#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
91
92/* Size of malloc() pool, make sure possible frame buffer fits */
93#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 10*1024*1024)
94
95/* memtest works on all but the last 1MB (u-boot) and malloc area */
96#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
97#define CONFIG_SYS_MEMTEST_END \
98 (PHYS_SDRAM_1+(PHYS_SDRAM_1_SIZE-CONFIG_SYS_MALLOC_LEN-0x100000))
99
100/* CFI FLASH driver setup */
101#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
102#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
103#define CONFIG_FLASH_SPANSION_S29WS_N
104/*
105 * TODO: Bluetechnix (the supplier of the SOM) did define these values
106 * in their original version of u-boot (1.2 or so). This should be
107 * reviewed.
108 *
109 * #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
110 * #define CONFIG_SYS_FLASH_PROTECTION
111 */
112#define CONFIG_SYS_FLASH_BASE CS0_BASE
113#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
114#define CONFIG_SYS_MAX_FLASH_SECT (254+8) /* max number of sectors per chip */
115
116/*
117 * FLASH and environment organization, only the Spansion chip is supported:
118 * - it has 254 * 128kB + 8 * 32kB blocks
119 * - this setup uses 4*32k+3*128k as monitor space = 0xA000 0000 to 0xA00F FFFF
120 * and 2 sectors with 128k as environment =
121 * A010 0000 to 0xA011 FFFF and 0xA012 0000 to 0xA013 FFFF
122 * - this could be less, but this is only for developer versions of the board
123 * and no-one is going to use the NOR flash anyway.
124 *
125 * Monitor is at the beginning of the NOR-Flash, 1MB reserved. Again this is
126 * way to large, but it avoids ENV overwrite (when updating u-boot) in case
127 * size breaks the next boundary (as it has with 128k).
128 */
129#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
130#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
131
132#define CONFIG_ENV_IS_IN_FLASH
133#define CONFIG_ENV_SECT_SIZE (128 * 1024)
134#define CONFIG_ENV_SIZE (8 * 1024) /* smaller for faster access */
135
136/* Address and size of Redundant Environment Sector */
137#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
138#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
139
140#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
141
142/* Hardware drivers */
143
144/*
145 * on TT-01 UART1 pins are used by Audio, so we use UART2
146 * TT-01 implements a hardware that turns off components depending on
147 * the power level. In PL=1 the RS232 transceiver is usually off,
148 * make sure that the transceiver is enabled during PL=1 for testing!
149 */
150#define CONFIG_MXC_UART
151#define CONFIG_SYS_MX31_UART2
152
153#define CONFIG_MXC_SPI
154#define CONFIG_MXC_GPIO
155
156/* MC13783 connected to CSPI3 and SS0 */
157#define CONFIG_PMIC
158#define CONFIG_PMIC_SPI
159#define CONFIG_PMIC_FSL
160
161#define CONFIG_FSL_PMIC_BUS 2
162#define CONFIG_FSL_PMIC_CS 0
163#define CONFIG_FSL_PMIC_CLK 1000000
164#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
165#define CONFIG_FSL_PMIC_BITLEN 32
166
167#define CONFIG_RTC_MC13XXX
168
169/* allow to overwrite serial and ethaddr */
170#define CONFIG_ENV_OVERWRITE
171/* console is UART2 on TT-01 */
172#define CONFIG_CONS_INDEX 1
173#define CONFIG_BAUDRATE 115200
174#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
175
176/* ethernet setup for the onboard smc9118 */
177#define CONFIG_MII
178#define CONFIG_SMC911X
179/* 16 bit, onboard ethernet, decoded via MACH-MX0 FPGA at 0x84200000 */
180#define CONFIG_SMC911X_BASE (CS4_BASE+0x200000)
181#define CONFIG_SMC911X_16_BIT
182
183/*
184 * Command definition
185 */
186
187#include <config_cmd_default.h>
188
189#define CONFIG_CMD_DATE
190#define CONFIG_CMD_PING
191#define CONFIG_CMD_DHCP
192#define CONFIG_CMD_SAVEENV
193#define CONFIG_CMD_NAND
194/*
195 * #define CONFIG_CMD_NAND_LOCK_UNLOCK the NAND01... chip does not support
196 * the NAND_CMD_LOCK_STATUS command, however the NFC of i.MX31 supports
197 * a software locking scheme.
198 */
199
200#define CONFIG_BOOTDELAY 3
201
202/*
203 * currently a default setting for booting via script is implemented
204 * set user to login name and serverip to tftp host, define your
205 * boot behaviour in bootscript.loginname
206 */
207#define CONFIG_EXTRA_ENV_SETTINGS \
208 "bootcmd=dhcp bootscript.$(user); source\0"
209
210#define CONFIG_BOOTP_SERVERIP /* tftp serverip not overruled by dhcp server */
211#define CONFIG_BOOTP_SEND_HOSTNAME /* if env-var 'hostname' is set, send it */
212
213/* Miscellaneous configurable options */
214#define CONFIG_HUSH_PARSER
215#define CONFIG_PROMPT_HUSH_PS2 "> "
216
217#define CONFIG_SYS_LONGHELP /* undef to save memory */
218#define CONFIG_SYS_PROMPT "TT01> "
219#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
220/* Print Buffer Size */
221#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
222 sizeof(CONFIG_SYS_PROMPT)+16)
223/* max number of command args */
224#define CONFIG_SYS_MAXARGS 16
225/* Boot Argument Buffer Size */
226#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
227
228#define CONFIG_SYS_HZ 1000
229
230#define CONFIG_CMDLINE_EDITING
231
232#define CONFIG_NAND_MXC
233#define CONFIG_SYS_MAX_NAND_DEVICE 1
234#define CONFIG_SYS_NAND_MAX_CHIPS 1
235
236/*
237 * actually this is nothing someone wants to configure!
238 * CONFIG_SYS_NAND_BASE despite being passed to board_nand_init()
239 * is not used by the driver.
240 */
241#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
242#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
243#define CONFIG_MXC_NAND_HWECC
244
245/* the current u-boot driver does not use the nand flash setup! */
246#define CONFIG_SYS_NAND_LARGEPAGE
247/*
248 * it's not 16 bit:
249 * #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
250 * the current u-boot mxc_nand.c tries to auto-detect, but this only
251 * reads the boot settings during reset (which might be wrong)
252 */
253
254#endif /* __CONFIG_H */