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Angus Ainslie3f8667c2022-08-25 06:46:02 -07001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2017 NXP
4 * Copyright 2018 Emcraft Systems
5 * Copyright 2022 Purism
6 *
7 */
8
9#ifndef __LIBREM5_H
10#define __LIBREM5_H
11
12/* #define DEBUG */
13
14#include <version.h>
15#include <linux/sizes.h>
16#include <asm/arch/imx-regs.h>
17
Angus Ainslie3f8667c2022-08-25 06:46:02 -070018#ifdef CONFIG_SPL_BUILD
19
20#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
21
22#define CONFIG_POWER_BD71837
23#define CONFIG_POWER_BD71837_I2C_BUS 0
24#define CONFIG_POWER_BD71837_I2C_ADDR 0x4B
25
26#endif /* CONFIG_SPL_BUILD*/
27
Tom Rini376b88a2022-10-28 20:27:13 -040028#define CFG_SYS_FSL_USDHC_NUM 2
Angus Ainslie3f8667c2022-08-25 06:46:02 -070029
30#define CONFIG_USBD_HS
31
32#define CONSOLE_ON_UART1
33
34#ifdef CONSOLE_ON_UART1
35#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
36#define CONSOLE_UART_CLK 0
37#define CONSOLE "ttymxc0"
38#elif defined(CONSOLE_ON_UART2)
39#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
40#define CONSOLE_UART_CLK 1
41#define CONSOLE "ttymxc1"
42#elif defined(CONSOLE_ON_UART3)
43#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
44#define CONSOLE_UART_CLK 2
45#define CONSOLE "ttymxc2"
46#elif defined(CONSOLE_ON_UART4)
47#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR
48#define CONSOLE_UART_CLK 3
49#define CONSOLE "ttymxc3"
50#else
51#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
52#define CONSOLE_UART_CLK 0
53#define CONSOLE "ttymxc0"
54#endif
55
56#ifndef CONFIG_SPL_BUILD
57#define BOOT_TARGET_DEVICES(func) \
58 func(MMC, mmc, 0) \
59 func(USB, usb, 0) \
60 func(DHCP, dhcp, na)
61#include <config_distro_bootcmd.h>
62#else
63#define BOOTENV
64#endif
65
66/* Initial environment variables */
67#define CONFIG_EXTRA_ENV_SETTINGS \
68 "scriptaddr=0x80000000\0" \
69 "pxefile_addr_r=0x80100000\0" \
70 "kernel_addr_r=0x80800000\0" \
71 "fdt_addr_r=0x84800000\0" \
72 "ramdisk_addr_r=0x85000000\0" \
73 "console=" CONSOLE ",115200\0" \
74 "bootargs=u_boot_version=" PLAIN_VERSION "\0" \
75 "stdin=usbacm,serial\0" \
76 "stdout=usbacm,serial\0" \
77 "stderr=usbacm,serial\0" \
78 BOOTENV
79
80/* Link Definitions */
81
82#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
83#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
84
85#define CONFIG_SYS_SDRAM_BASE 0x40000000
86#define PHYS_SDRAM 0x40000000
87#define PHYS_SDRAM_SIZE 0xc0000000 /* 3GB LPDDR4 one Rank */
88
89/* Monitor Command Prompt */
90
Tom Rini376b88a2022-10-28 20:27:13 -040091#define CFG_SYS_FSL_ESDHC_ADDR 0
Angus Ainslie3f8667c2022-08-25 06:46:02 -070092
93#endif