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git01.mediatek.com / filogic / uboot / a3547360569372d675a46d9ec74c2270b87c5365 / . / arch / arm / dts / k3-am68-sk-base-board-u-boot.dtsi
blob: 79faa1b5737df9a6fc1d8c79673680ee8a51dbe9 [file] [log] [blame]
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
Neha Malcom Francis9409fb62023-07-22 00:14:36 +0530[diff] [blame]6#include "k3-j721s2-binman.dtsi"
7
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]8/ {
9 chosen {
10 stdout-path = "serial2:115200n8";
11 tick-timer = &timer1;
12 };
13
14 aliases {
15 serial0 = &wkup_uart0;
16 serial1 = &mcu_uart0;
17 serial2 = &main_uart8;
18 i2c0 = &wkup_i2c0;
19 i2c1 = &mcu_i2c0;
20 i2c2 = &mcu_i2c1;
21 i2c3 = &main_i2c0;
22 ethernet0 = &cpsw_port1;
23 mmc1 = &main_sdhci1;
24 };
25};
26
27&wkup_i2c0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]28 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]29};
30
31&cbass_main {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]32 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]33};
34
35&main_navss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]36 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]37};
38
39&cbass_mcu_wakeup {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]40 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]41
42 timer1: timer@40400000 {
43 compatible = "ti,omap5430-timer";
44 reg = <0x0 0x40400000 0x0 0x80>;
45 ti,timer-alwon;
46 clock-frequency = <250000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]47 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]48 };
49
50 chipid@43000014 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]51 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]52 };
53};
54
55&mcu_navss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]56 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]57};
58
59&mcu_ringacc {
60 reg = <0x0 0x2b800000 0x0 0x400000>,
61 <0x0 0x2b000000 0x0 0x400000>,
62 <0x0 0x28590000 0x0 0x100>,
63 <0x0 0x2a500000 0x0 0x40000>,
64 <0x0 0x28440000 0x0 0x40000>;
65 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]66 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]67};
68
69&mcu_udmap {
70 reg = <0x0 0x285c0000 0x0 0x100>,
71 <0x0 0x284c0000 0x0 0x4000>,
72 <0x0 0x2a800000 0x0 0x40000>,
73 <0x0 0x284a0000 0x0 0x4000>,
74 <0x0 0x2aa00000 0x0 0x40000>,
75 <0x0 0x28400000 0x0 0x2000>;
76 reg-names = "gcfg", "rchan", "rchanrt", "tchan",
77 "tchanrt", "rflow";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]78 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]79};
80
81&secure_proxy_main {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]82 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]83};
84
85&sms {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]86 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]87 k3_sysreset: sysreset-controller {
88 compatible = "ti,sci-sysreset";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]89 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]90 };
91};
92
93&main_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]94 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]95};
96
97&main_uart8_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]98 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]99};
100
101&main_mmc1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]102 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]103};
104
105&wkup_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]106 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]107};
108
109&k3_pds {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]110 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]111};
112
113&k3_clks {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]114 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]115};
116
117&k3_reset {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]118 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]119};
120
121&main_uart8 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]122 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]123};
124
125&mcu_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]126 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]127};
128
129&wkup_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]130 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]131};
132
133&mcu_cpsw {
134 reg = <0x0 0x46000000 0x0 0x200000>,
135 <0x0 0x40f00200 0x0 0x8>;
136 reg-names = "cpsw_nuss", "mac_efuse";
137 /delete-property/ ranges;
138
139 cpsw-phy-sel@40f04040 {
140 compatible = "ti,am654-cpsw-phy-sel";
141 reg= <0x0 0x40f04040 0x0 0x4>;
142 reg-names = "gmii-sel";
143 };
144};
145
146&main_sdhci0 {
147 status = "disabled";
148};
149
150&main_sdhci1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]151 bootph-pre-ram;
Sinthu Rajad44e0c62023-01-10 21:17:56 +0530[diff] [blame]152};