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git01.mediatek.com / filogic / uboot / a349b3b842096ed00e2a911d49ac603480bf9a48 / . / configs / chromebook_speedy_defconfig
blob: e3d4c30739ee9febe5f0ea85edb52f2684fc1cb3 [file] [log] [blame]
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]1CONFIG_ARM=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]2# CONFIG_SPL_USE_ARCH_MEMCPY is not set
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]3CONFIG_ARCH_ROCKCHIP=y
4CONFIG_SYS_TEXT_BASE=0x00100000
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]5CONFIG_NR_DRAM_BANKS=1
Tom Rini47dece32020-04-28 16:15:47 -0400[diff] [blame]6CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
Tom Rini0332a1a2020-07-06 13:54:25 -0400[diff] [blame]7CONFIG_SPL_TEXT_BASE=0xff704000
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]8CONFIG_ROCKCHIP_RK3288=y
9# CONFIG_SPL_MMC_SUPPORT is not set
10CONFIG_TARGET_CHROMEBOOK_SPEEDY=y
Tom Rinic9285bf2019-04-29 15:54:04 -0400[diff] [blame]11CONFIG_SPL_STACK_R_ADDR=0x80000
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]12CONFIG_DEBUG_UART_BASE=0xff690000
13CONFIG_DEBUG_UART_CLOCK=24000000
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]14CONFIG_SPL_SPI_FLASH_SUPPORT=y
15CONFIG_SPL_SPI_SUPPORT=y
Tom Rini47dece32020-04-28 16:15:47 -0400[diff] [blame]16CONFIG_SPL_PAYLOAD="u-boot.img"
Tom Rini90fa4e92020-07-06 15:46:38 -0400[diff] [blame]17CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy"
Tom Rini84610272020-07-28 08:46:52 -0400[diff] [blame]18CONFIG_DEBUG_UART=y
Simon Glass4be229d2019-07-20 20:51:14 -0600[diff] [blame]19CONFIG_USE_PREBOOT=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]20CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb"
Tom Rinif92b6fa2020-10-09 12:22:06 -0400[diff] [blame]21CONFIG_SILENT_CONSOLE=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]22# CONFIG_DISPLAY_CPUINFO is not set
23CONFIG_DISPLAY_BOARDINFO_LATE=y
Urja Rannikkoe8c4c962020-05-13 19:15:21 +0000[diff] [blame]24CONFIG_BOARD_EARLY_INIT_R=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]25# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]26CONFIG_SPL_STACK_R=y
27CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]28# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
29# CONFIG_SPL_CRC32_SUPPORT is not set
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]30CONFIG_SPL_SPI_LOAD=y
31CONFIG_CMD_GPIO=y
32CONFIG_CMD_GPT=y
33CONFIG_CMD_I2C=y
34CONFIG_CMD_MMC=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]35CONFIG_CMD_SF_TEST=y
36CONFIG_CMD_SPI=y
37CONFIG_CMD_USB=y
38# CONFIG_CMD_SETEXPR is not set
39CONFIG_CMD_CACHE=y
40CONFIG_CMD_TIME=y
41CONFIG_CMD_PMIC=y
42CONFIG_CMD_REGULATOR=y
43# CONFIG_SPL_DOS_PARTITION is not set
44# CONFIG_SPL_EFI_PARTITION is not set
45CONFIG_SPL_PARTITION_UUIDS=y
46CONFIG_SPL_OF_CONTROL=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]47CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
48CONFIG_SPL_OF_PLATDATA=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]49CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]50CONFIG_REGMAP=y
51CONFIG_SPL_REGMAP=y
52CONFIG_SYSCON=y
53CONFIG_SPL_SYSCON=y
54# CONFIG_SPL_SIMPLE_BUS is not set
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]55# CONFIG_SPL_BLK is not set
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]56CONFIG_CLK=y
57CONFIG_SPL_CLK=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]58CONFIG_ROCKCHIP_GPIO=y
59CONFIG_I2C_CROS_EC_TUNNEL=y
60CONFIG_SYS_I2C_ROCKCHIP=y
61CONFIG_I2C_MUX=y
62CONFIG_DM_KEYBOARD=y
63CONFIG_CROS_EC_KEYB=y
64CONFIG_CROS_EC=y
65CONFIG_CROS_EC_SPI=y
66CONFIG_PWRSEQ=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]67# CONFIG_SPL_DM_MMC is not set
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]68CONFIG_MMC_DW=y
69CONFIG_MMC_DW_ROCKCHIP=y
Miquel Raynal2e35dbb2019-10-03 19:50:05 +0200[diff] [blame]70CONFIG_MTD=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]71CONFIG_SF_DEFAULT_BUS=2
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]72CONFIG_SF_DEFAULT_SPEED=20000000
Urja Rannikko7a19eec2019-05-13 13:51:03 +0000[diff] [blame]73CONFIG_SPI_FLASH_GIGADEVICE=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]74CONFIG_PINCTRL=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]75CONFIG_PINCONF=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]76CONFIG_SPL_PINCTRL=y
Urja Rannikkoaa02ec02020-05-13 19:15:23 +0000[diff] [blame]77# CONFIG_SPL_PINCTRL_FULL is not set
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]78CONFIG_DM_PMIC=y
79# CONFIG_SPL_PMIC_CHILDREN is not set
80CONFIG_PMIC_RK8XX=y
81CONFIG_DM_REGULATOR_FIXED=y
82CONFIG_REGULATOR_RK8XX=y
83CONFIG_PWM_ROCKCHIP=y
84CONFIG_RAM=y
85CONFIG_SPL_RAM=y
86CONFIG_DEBUG_UART_SHIFT=2
87CONFIG_ROCKCHIP_SERIAL=y
88CONFIG_ROCKCHIP_SPI=y
89CONFIG_SYSRESET=y
90CONFIG_USB=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]91# CONFIG_SPL_DM_USB is not set
92CONFIG_USB_DWC2=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]93CONFIG_ROCKCHIP_USB2_PHY=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]94CONFIG_DM_VIDEO=y
Anatolij Gustschindba36702020-02-04 22:43:06 +0100[diff] [blame]95# CONFIG_VIDEO_BPP8 is not set
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]96CONFIG_CONSOLE_TRUETYPE=y
97CONFIG_DISPLAY=y
98CONFIG_VIDEO_ROCKCHIP=y
99CONFIG_DISPLAY_ROCKCHIP_EDP=y
100CONFIG_DISPLAY_ROCKCHIP_HDMI=y
101# CONFIG_USE_PRIVATE_LIBGCC is not set
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]102CONFIG_SPL_TINY_MEMSET=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]103CONFIG_CMD_DHRYSTONE=y
104CONFIG_ERRNO_STR=y