Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1 | /* |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 2 | * Copyright 2008-2014 Freescale Semiconductor, Inc. |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 3 | * |
Tom Rini | e237880 | 2016-01-14 22:05:13 -0500 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0 |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef FSL_DDR_MEMCTL_H |
| 8 | #define FSL_DDR_MEMCTL_H |
| 9 | |
| 10 | /* |
| 11 | * Pick a basic DDR Technology. |
| 12 | */ |
| 13 | #include <ddr_spd.h> |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 14 | #include <fsl_ddrc_version.h> |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 15 | |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 16 | #define SDRAM_TYPE_DDR1 2 |
| 17 | #define SDRAM_TYPE_DDR2 3 |
| 18 | #define SDRAM_TYPE_LPDDR1 6 |
| 19 | #define SDRAM_TYPE_DDR3 7 |
| 20 | #define SDRAM_TYPE_DDR4 5 |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 21 | |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 22 | #define DDR_BL4 4 /* burst length 4 */ |
| 23 | #define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */ |
| 24 | #define DDR_OTF 6 /* on-the-fly BC4 and BL8 */ |
| 25 | #define DDR_BL8 8 /* burst length 8 */ |
| 26 | |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 27 | #define DDR3_RTT_OFF 0 |
Dave Liu | 0489919 | 2010-03-05 12:23:00 +0800 | [diff] [blame] | 28 | #define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */ |
| 29 | #define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */ |
| 30 | #define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */ |
| 31 | #define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */ |
| 32 | #define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */ |
| 33 | |
York Sun | 5cb12f6 | 2015-11-04 10:03:17 -0800 | [diff] [blame] | 34 | #define DDR4_RTT_OFF 0 |
| 35 | #define DDR4_RTT_60_OHM 1 /* RZQ/4 */ |
| 36 | #define DDR4_RTT_120_OHM 2 /* RZQ/2 */ |
| 37 | #define DDR4_RTT_40_OHM 3 /* RZQ/6 */ |
| 38 | #define DDR4_RTT_240_OHM 4 /* RZQ/1 */ |
| 39 | #define DDR4_RTT_48_OHM 5 /* RZQ/5 */ |
| 40 | #define DDR4_RTT_80_OHM 6 /* RZQ/3 */ |
| 41 | #define DDR4_RTT_34_OHM 7 /* RZQ/7 */ |
| 42 | |
York Sun | 454f507 | 2011-08-26 11:32:43 -0700 | [diff] [blame] | 43 | #define DDR2_RTT_OFF 0 |
| 44 | #define DDR2_RTT_75_OHM 1 |
| 45 | #define DDR2_RTT_150_OHM 2 |
| 46 | #define DDR2_RTT_50_OHM 3 |
| 47 | |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 48 | #if defined(CONFIG_SYS_FSL_DDR1) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 49 | #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1) |
| 50 | typedef ddr1_spd_eeprom_t generic_spd_eeprom_t; |
| 51 | #ifndef CONFIG_FSL_SDRAM_TYPE |
| 52 | #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1 |
| 53 | #endif |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 54 | #elif defined(CONFIG_SYS_FSL_DDR2) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 55 | #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) |
| 56 | typedef ddr2_spd_eeprom_t generic_spd_eeprom_t; |
| 57 | #ifndef CONFIG_FSL_SDRAM_TYPE |
| 58 | #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2 |
| 59 | #endif |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 60 | #elif defined(CONFIG_SYS_FSL_DDR3) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 61 | typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; |
Dave Liu | 4758d53 | 2008-11-21 16:31:29 +0800 | [diff] [blame] | 62 | #ifndef CONFIG_FSL_SDRAM_TYPE |
| 63 | #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3 |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 64 | #endif |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 65 | #elif defined(CONFIG_SYS_FSL_DDR4) |
| 66 | #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */ |
| 67 | typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; |
| 68 | #ifndef CONFIG_FSL_SDRAM_TYPE |
| 69 | #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR4 |
| 70 | #endif |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 71 | #endif /* #if defined(CONFIG_SYS_FSL_DDR1) */ |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 72 | |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 73 | #define FSL_DDR_ODT_NEVER 0x0 |
| 74 | #define FSL_DDR_ODT_CS 0x1 |
| 75 | #define FSL_DDR_ODT_ALL_OTHER_CS 0x2 |
| 76 | #define FSL_DDR_ODT_OTHER_DIMM 0x3 |
| 77 | #define FSL_DDR_ODT_ALL 0x4 |
| 78 | #define FSL_DDR_ODT_SAME_DIMM 0x5 |
| 79 | #define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6 |
| 80 | #define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7 |
| 81 | |
Haiying Wang | 272b596 | 2008-10-03 12:36:39 -0400 | [diff] [blame] | 82 | /* define bank(chip select) interleaving mode */ |
| 83 | #define FSL_DDR_CS0_CS1 0x40 |
| 84 | #define FSL_DDR_CS2_CS3 0x20 |
| 85 | #define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3) |
| 86 | #define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04) |
| 87 | |
| 88 | /* define memory controller interleaving mode */ |
| 89 | #define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0 |
| 90 | #define FSL_DDR_PAGE_INTERLEAVING 0x1 |
| 91 | #define FSL_DDR_BANK_INTERLEAVING 0x2 |
| 92 | #define FSL_DDR_SUPERBANK_INTERLEAVING 0x3 |
York Sun | c459ae6 | 2014-02-10 13:59:44 -0800 | [diff] [blame] | 93 | #define FSL_DDR_256B_INTERLEAVING 0x8 |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 94 | #define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA |
| 95 | #define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC |
| 96 | #define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD |
| 97 | /* placeholder for 4-way interleaving */ |
| 98 | #define FSL_DDR_4WAY_1KB_INTERLEAVING 0x1A |
| 99 | #define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C |
| 100 | #define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D |
Haiying Wang | 272b596 | 2008-10-03 12:36:39 -0400 | [diff] [blame] | 101 | |
York Sun | 98df4d1 | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 102 | #define SDRAM_CS_CONFIG_EN 0x80000000 |
| 103 | |
Poonam_Aggrwal-b10812 | 30cb145 | 2009-01-04 08:46:38 +0530 | [diff] [blame] | 104 | /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration |
| 105 | */ |
| 106 | #define SDRAM_CFG_MEM_EN 0x80000000 |
| 107 | #define SDRAM_CFG_SREN 0x40000000 |
| 108 | #define SDRAM_CFG_ECC_EN 0x20000000 |
| 109 | #define SDRAM_CFG_RD_EN 0x10000000 |
| 110 | #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 |
| 111 | #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 |
| 112 | #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 |
| 113 | #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 |
| 114 | #define SDRAM_CFG_DYN_PWR 0x00200000 |
Matthew McClintock | 78fb175 | 2012-08-13 08:10:37 +0000 | [diff] [blame] | 115 | #define SDRAM_CFG_DBW_MASK 0x00180000 |
York Sun | 016095d | 2012-10-08 07:44:24 +0000 | [diff] [blame] | 116 | #define SDRAM_CFG_DBW_SHIFT 19 |
Poonam_Aggrwal-b10812 | 30cb145 | 2009-01-04 08:46:38 +0530 | [diff] [blame] | 117 | #define SDRAM_CFG_32_BE 0x00080000 |
Poonam Aggrwal | 42d3640 | 2011-02-07 15:09:51 +0530 | [diff] [blame] | 118 | #define SDRAM_CFG_16_BE 0x00100000 |
Poonam_Aggrwal-b10812 | 30cb145 | 2009-01-04 08:46:38 +0530 | [diff] [blame] | 119 | #define SDRAM_CFG_8_BE 0x00040000 |
| 120 | #define SDRAM_CFG_NCAP 0x00020000 |
| 121 | #define SDRAM_CFG_2T_EN 0x00008000 |
| 122 | #define SDRAM_CFG_BI 0x00000001 |
| 123 | |
Tang Yuantian | 064f126 | 2014-11-21 11:17:15 +0800 | [diff] [blame] | 124 | #define SDRAM_CFG2_FRC_SR 0x80000000 |
York Sun | c8fc959 | 2011-01-25 22:05:49 -0800 | [diff] [blame] | 125 | #define SDRAM_CFG2_D_INIT 0x00000010 |
| 126 | #define SDRAM_CFG2_ODT_CFG_MASK 0x00600000 |
York Sun | 15f874a | 2011-08-26 11:32:40 -0700 | [diff] [blame] | 127 | #define SDRAM_CFG2_ODT_NEVER 0 |
| 128 | #define SDRAM_CFG2_ODT_ONLY_WRITE 1 |
| 129 | #define SDRAM_CFG2_ODT_ONLY_READ 2 |
| 130 | #define SDRAM_CFG2_ODT_ALWAYS 3 |
York Sun | c8fc959 | 2011-01-25 22:05:49 -0800 | [diff] [blame] | 131 | |
Shengzhou Liu | bdda96c | 2015-12-16 16:45:41 +0800 | [diff] [blame] | 132 | #define SDRAM_INTERVAL_BSTOPRE 0x3FFF |
York Sun | c8fc959 | 2011-01-25 22:05:49 -0800 | [diff] [blame] | 133 | #define TIMING_CFG_2_CPO_MASK 0x0F800000 |
| 134 | |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 135 | #if defined(CONFIG_SYS_FSL_DDR_VER) && \ |
| 136 | (CONFIG_SYS_FSL_DDR_VER > FSL_DDR_VER_4_4) |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 137 | #define RD_TO_PRE_MASK 0xf |
| 138 | #define RD_TO_PRE_SHIFT 13 |
| 139 | #define WR_DATA_DELAY_MASK 0xf |
| 140 | #define WR_DATA_DELAY_SHIFT 9 |
| 141 | #else |
| 142 | #define RD_TO_PRE_MASK 0x7 |
| 143 | #define RD_TO_PRE_SHIFT 13 |
| 144 | #define WR_DATA_DELAY_MASK 0x7 |
| 145 | #define WR_DATA_DELAY_SHIFT 10 |
| 146 | #endif |
| 147 | |
York Sun | 922f40f | 2011-01-10 12:03:01 +0000 | [diff] [blame] | 148 | /* DDR_MD_CNTL */ |
| 149 | #define MD_CNTL_MD_EN 0x80000000 |
| 150 | #define MD_CNTL_CS_SEL_CS0 0x00000000 |
| 151 | #define MD_CNTL_CS_SEL_CS1 0x10000000 |
| 152 | #define MD_CNTL_CS_SEL_CS2 0x20000000 |
| 153 | #define MD_CNTL_CS_SEL_CS3 0x30000000 |
| 154 | #define MD_CNTL_CS_SEL_CS0_CS1 0x40000000 |
| 155 | #define MD_CNTL_CS_SEL_CS2_CS3 0x50000000 |
| 156 | #define MD_CNTL_MD_SEL_MR 0x00000000 |
| 157 | #define MD_CNTL_MD_SEL_EMR 0x01000000 |
| 158 | #define MD_CNTL_MD_SEL_EMR2 0x02000000 |
| 159 | #define MD_CNTL_MD_SEL_EMR3 0x03000000 |
| 160 | #define MD_CNTL_SET_REF 0x00800000 |
| 161 | #define MD_CNTL_SET_PRE 0x00400000 |
| 162 | #define MD_CNTL_CKE_CNTL_LOW 0x00100000 |
| 163 | #define MD_CNTL_CKE_CNTL_HIGH 0x00200000 |
| 164 | #define MD_CNTL_WRCW 0x00080000 |
| 165 | #define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF) |
York Sun | 1f8d706 | 2015-03-19 09:30:29 -0700 | [diff] [blame] | 166 | #define MD_CNTL_CS_SEL(x) (((x) & 0x7) << 28) |
| 167 | #define MD_CNTL_MD_SEL(x) (((x) & 0xf) << 24) |
York Sun | 922f40f | 2011-01-10 12:03:01 +0000 | [diff] [blame] | 168 | |
York Sun | 00a69c0 | 2011-01-10 12:03:02 +0000 | [diff] [blame] | 169 | /* DDR_CDR1 */ |
| 170 | #define DDR_CDR1_DHC_EN 0x80000000 |
York Sun | 7d69ea3 | 2012-10-08 07:44:22 +0000 | [diff] [blame] | 171 | #define DDR_CDR1_ODT_SHIFT 17 |
| 172 | #define DDR_CDR1_ODT_MASK 0x6 |
| 173 | #define DDR_CDR2_ODT_MASK 0x1 |
| 174 | #define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT) |
| 175 | #define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK) |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 176 | #define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8)) |
Tang Yuantian | 064f126 | 2014-11-21 11:17:15 +0800 | [diff] [blame] | 177 | #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 |
York Sun | 0301703 | 2015-03-20 19:28:23 -0700 | [diff] [blame] | 178 | #define DDR_CDR2_VREF_RANGE_2 0x00000040 |
York Sun | 7d69ea3 | 2012-10-08 07:44:22 +0000 | [diff] [blame] | 179 | |
| 180 | #if (defined(CONFIG_SYS_FSL_DDR_VER) && \ |
| 181 | (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)) |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 182 | #ifdef CONFIG_SYS_FSL_DDR3L |
| 183 | #define DDR_CDR_ODT_OFF 0x0 |
| 184 | #define DDR_CDR_ODT_120ohm 0x1 |
| 185 | #define DDR_CDR_ODT_200ohm 0x2 |
| 186 | #define DDR_CDR_ODT_75ohm 0x3 |
| 187 | #define DDR_CDR_ODT_60ohm 0x5 |
| 188 | #define DDR_CDR_ODT_46ohm 0x7 |
| 189 | #elif defined(CONFIG_SYS_FSL_DDR4) |
| 190 | #define DDR_CDR_ODT_OFF 0x0 |
| 191 | #define DDR_CDR_ODT_100ohm 0x1 |
| 192 | #define DDR_CDR_ODT_120OHM 0x2 |
| 193 | #define DDR_CDR_ODT_80ohm 0x3 |
| 194 | #define DDR_CDR_ODT_60ohm 0x4 |
| 195 | #define DDR_CDR_ODT_40ohm 0x5 |
| 196 | #define DDR_CDR_ODT_50ohm 0x6 |
| 197 | #define DDR_CDR_ODT_30ohm 0x7 |
| 198 | #else |
York Sun | 7d69ea3 | 2012-10-08 07:44:22 +0000 | [diff] [blame] | 199 | #define DDR_CDR_ODT_OFF 0x0 |
| 200 | #define DDR_CDR_ODT_120ohm 0x1 |
| 201 | #define DDR_CDR_ODT_180ohm 0x2 |
| 202 | #define DDR_CDR_ODT_75ohm 0x3 |
| 203 | #define DDR_CDR_ODT_110ohm 0x4 |
| 204 | #define DDR_CDR_ODT_60hm 0x5 |
| 205 | #define DDR_CDR_ODT_70ohm 0x6 |
| 206 | #define DDR_CDR_ODT_47ohm 0x7 |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 207 | #endif /* DDR3L */ |
York Sun | 7d69ea3 | 2012-10-08 07:44:22 +0000 | [diff] [blame] | 208 | #else |
| 209 | #define DDR_CDR_ODT_75ohm 0x0 |
| 210 | #define DDR_CDR_ODT_55ohm 0x1 |
| 211 | #define DDR_CDR_ODT_60ohm 0x2 |
| 212 | #define DDR_CDR_ODT_50ohm 0x3 |
| 213 | #define DDR_CDR_ODT_150ohm 0x4 |
| 214 | #define DDR_CDR_ODT_43ohm 0x5 |
| 215 | #define DDR_CDR_ODT_120ohm 0x6 |
| 216 | #endif |
York Sun | 00a69c0 | 2011-01-10 12:03:02 +0000 | [diff] [blame] | 217 | |
Tang Yuantian | 064f126 | 2014-11-21 11:17:15 +0800 | [diff] [blame] | 218 | #define DDR_INIT_ADDR_EXT_UIA (1 << 31) |
| 219 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 220 | /* Record of register values computed */ |
| 221 | typedef struct fsl_ddr_cfg_regs_s { |
| 222 | struct { |
| 223 | unsigned int bnds; |
| 224 | unsigned int config; |
| 225 | unsigned int config_2; |
| 226 | } cs[CONFIG_CHIP_SELECTS_PER_CTRL]; |
| 227 | unsigned int timing_cfg_3; |
| 228 | unsigned int timing_cfg_0; |
| 229 | unsigned int timing_cfg_1; |
| 230 | unsigned int timing_cfg_2; |
| 231 | unsigned int ddr_sdram_cfg; |
| 232 | unsigned int ddr_sdram_cfg_2; |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 233 | unsigned int ddr_sdram_cfg_3; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 234 | unsigned int ddr_sdram_mode; |
| 235 | unsigned int ddr_sdram_mode_2; |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 236 | unsigned int ddr_sdram_mode_3; |
| 237 | unsigned int ddr_sdram_mode_4; |
| 238 | unsigned int ddr_sdram_mode_5; |
| 239 | unsigned int ddr_sdram_mode_6; |
| 240 | unsigned int ddr_sdram_mode_7; |
| 241 | unsigned int ddr_sdram_mode_8; |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 242 | unsigned int ddr_sdram_mode_9; |
| 243 | unsigned int ddr_sdram_mode_10; |
| 244 | unsigned int ddr_sdram_mode_11; |
| 245 | unsigned int ddr_sdram_mode_12; |
| 246 | unsigned int ddr_sdram_mode_13; |
| 247 | unsigned int ddr_sdram_mode_14; |
| 248 | unsigned int ddr_sdram_mode_15; |
| 249 | unsigned int ddr_sdram_mode_16; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 250 | unsigned int ddr_sdram_md_cntl; |
| 251 | unsigned int ddr_sdram_interval; |
| 252 | unsigned int ddr_data_init; |
| 253 | unsigned int ddr_sdram_clk_cntl; |
| 254 | unsigned int ddr_init_addr; |
| 255 | unsigned int ddr_init_ext_addr; |
| 256 | unsigned int timing_cfg_4; |
| 257 | unsigned int timing_cfg_5; |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 258 | unsigned int timing_cfg_6; |
| 259 | unsigned int timing_cfg_7; |
| 260 | unsigned int timing_cfg_8; |
| 261 | unsigned int timing_cfg_9; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 262 | unsigned int ddr_zq_cntl; |
| 263 | unsigned int ddr_wrlvl_cntl; |
York Sun | 7d69ea3 | 2012-10-08 07:44:22 +0000 | [diff] [blame] | 264 | unsigned int ddr_wrlvl_cntl_2; |
| 265 | unsigned int ddr_wrlvl_cntl_3; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 266 | unsigned int ddr_sr_cntr; |
| 267 | unsigned int ddr_sdram_rcw_1; |
| 268 | unsigned int ddr_sdram_rcw_2; |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 269 | unsigned int ddr_sdram_rcw_3; |
| 270 | unsigned int ddr_sdram_rcw_4; |
| 271 | unsigned int ddr_sdram_rcw_5; |
| 272 | unsigned int ddr_sdram_rcw_6; |
| 273 | unsigned int dq_map_0; |
| 274 | unsigned int dq_map_1; |
| 275 | unsigned int dq_map_2; |
| 276 | unsigned int dq_map_3; |
york | 4260372 | 2010-07-02 22:25:54 +0000 | [diff] [blame] | 277 | unsigned int ddr_eor; |
York Sun | 7dda847 | 2011-01-10 12:02:59 +0000 | [diff] [blame] | 278 | unsigned int ddr_cdr1; |
| 279 | unsigned int ddr_cdr2; |
| 280 | unsigned int err_disable; |
| 281 | unsigned int err_int_en; |
| 282 | unsigned int debug[32]; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 283 | } fsl_ddr_cfg_regs_t; |
| 284 | |
| 285 | typedef struct memctl_options_partial_s { |
Priyanka Jain | 4a71741 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 286 | unsigned int all_dimms_ecc_capable; |
| 287 | unsigned int all_dimms_tckmax_ps; |
| 288 | unsigned int all_dimms_burst_lengths_bitmask; |
| 289 | unsigned int all_dimms_registered; |
| 290 | unsigned int all_dimms_unbuffered; |
York Sun | 2896cb7 | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 291 | /* unsigned int lowest_common_spd_caslat; */ |
Priyanka Jain | 4a71741 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 292 | unsigned int all_dimms_minimum_trcd_ps; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 293 | } memctl_options_partial_t; |
| 294 | |
York Sun | dd803dd | 2011-05-27 07:25:51 +0800 | [diff] [blame] | 295 | #define DDR_DATA_BUS_WIDTH_64 0 |
| 296 | #define DDR_DATA_BUS_WIDTH_32 1 |
| 297 | #define DDR_DATA_BUS_WIDTH_16 2 |
York Sun | e0f6046 | 2014-09-05 13:52:43 +0800 | [diff] [blame] | 298 | #define DDR_CSWL_CS0 0x04000001 |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 299 | /* |
| 300 | * Generalized parameters for memory controller configuration, |
| 301 | * might be a little specific to the FSL memory controller |
| 302 | */ |
| 303 | typedef struct memctl_options_s { |
| 304 | /* |
| 305 | * Memory organization parameters |
| 306 | * |
| 307 | * if DIMM is present in the system |
| 308 | * where DIMMs are with respect to chip select |
| 309 | * where chip selects are with respect to memory boundaries |
| 310 | */ |
| 311 | unsigned int registered_dimm_en; /* use registered DIMM support */ |
| 312 | |
| 313 | /* Options local to a Chip Select */ |
| 314 | struct cs_local_opts_s { |
| 315 | unsigned int auto_precharge; |
| 316 | unsigned int odt_rd_cfg; |
| 317 | unsigned int odt_wr_cfg; |
York Sun | ba0c2eb | 2011-01-10 12:03:00 +0000 | [diff] [blame] | 318 | unsigned int odt_rtt_norm; |
| 319 | unsigned int odt_rtt_wr; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 320 | } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL]; |
| 321 | |
| 322 | /* Special configurations for chip select */ |
| 323 | unsigned int memctl_interleaving; |
| 324 | unsigned int memctl_interleaving_mode; |
| 325 | unsigned int ba_intlv_ctl; |
york | 4260372 | 2010-07-02 22:25:54 +0000 | [diff] [blame] | 326 | unsigned int addr_hash; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 327 | |
| 328 | /* Operational mode parameters */ |
Priyanka Jain | 4a71741 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 329 | unsigned int ecc_mode; /* Use ECC? */ |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 330 | /* Initialize ECC using memory controller? */ |
Priyanka Jain | 4a71741 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 331 | unsigned int ecc_init_using_memctl; |
| 332 | unsigned int dqs_config; /* Use DQS? maybe only with DDR2? */ |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 333 | /* SREN - self-refresh during sleep */ |
| 334 | unsigned int self_refresh_in_sleep; |
Joakim Tjernlund | 6dc192d | 2015-10-14 16:32:00 +0200 | [diff] [blame] | 335 | /* SR_IE - Self-refresh interrupt enable */ |
| 336 | unsigned int self_refresh_interrupt_en; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 337 | unsigned int dynamic_power; /* DYN_PWR */ |
| 338 | /* memory data width to use (16-bit, 32-bit, 64-bit) */ |
| 339 | unsigned int data_bus_width; |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 340 | unsigned int burst_length; /* BL4, OTF and BL8 */ |
| 341 | /* On-The-Fly Burst Chop enable */ |
Priyanka Jain | 4a71741 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 342 | unsigned int otf_burst_chop_en; |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 343 | /* mirrior DIMMs for DDR3 */ |
| 344 | unsigned int mirrored_dimm; |
york | f4f93c6 | 2010-07-02 22:25:53 +0000 | [diff] [blame] | 345 | unsigned int quad_rank_present; |
York Sun | 7dda847 | 2011-01-10 12:02:59 +0000 | [diff] [blame] | 346 | unsigned int ap_en; /* address parity enable for RDIMM */ |
York Sun | 4889c98 | 2013-06-25 11:37:47 -0700 | [diff] [blame] | 347 | unsigned int x4_en; /* enable x4 devices */ |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 348 | |
| 349 | /* Global Timing Parameters */ |
| 350 | unsigned int cas_latency_override; |
| 351 | unsigned int cas_latency_override_value; |
| 352 | unsigned int use_derated_caslat; |
| 353 | unsigned int additive_latency_override; |
| 354 | unsigned int additive_latency_override_value; |
| 355 | |
| 356 | unsigned int clk_adjust; /* */ |
| 357 | unsigned int cpo_override; |
| 358 | unsigned int write_data_delay; /* DQS adjust */ |
Dave Liu | 64ee7df | 2009-12-16 10:24:37 -0600 | [diff] [blame] | 359 | |
York Sun | e0f6046 | 2014-09-05 13:52:43 +0800 | [diff] [blame] | 360 | unsigned int cswl_override; |
Dave Liu | 64ee7df | 2009-12-16 10:24:37 -0600 | [diff] [blame] | 361 | unsigned int wrlvl_override; |
| 362 | unsigned int wrlvl_sample; /* Write leveling */ |
| 363 | unsigned int wrlvl_start; |
York Sun | 7d69ea3 | 2012-10-08 07:44:22 +0000 | [diff] [blame] | 364 | unsigned int wrlvl_ctl_2; |
| 365 | unsigned int wrlvl_ctl_3; |
Dave Liu | 64ee7df | 2009-12-16 10:24:37 -0600 | [diff] [blame] | 366 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 367 | unsigned int half_strength_driver_enable; |
Priyanka Jain | 4a71741 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 368 | unsigned int twot_en; |
| 369 | unsigned int threet_en; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 370 | unsigned int bstopre; |
Priyanka Jain | 4a71741 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 371 | unsigned int tfaw_window_four_activates_ps; /* tFAW -- FOUR_ACT */ |
Dave Liu | 2aad0ae | 2008-11-21 16:31:35 +0800 | [diff] [blame] | 372 | |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 373 | /* Rtt impedance */ |
| 374 | unsigned int rtt_override; /* rtt_override enable */ |
| 375 | unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */ |
Dave Liu | 2d0f125 | 2009-12-16 10:24:38 -0600 | [diff] [blame] | 376 | unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */ |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 377 | |
Dave Liu | 2aad0ae | 2008-11-21 16:31:35 +0800 | [diff] [blame] | 378 | /* Automatic self refresh */ |
| 379 | unsigned int auto_self_refresh_en; |
| 380 | unsigned int sr_it; |
Dave Liu | 4be87b2 | 2009-03-14 12:48:30 +0800 | [diff] [blame] | 381 | /* ZQ calibration */ |
| 382 | unsigned int zq_en; |
| 383 | /* Write leveling */ |
| 384 | unsigned int wrlvl_en; |
York Sun | 7dda847 | 2011-01-10 12:02:59 +0000 | [diff] [blame] | 385 | /* RCW override for RDIMM */ |
| 386 | unsigned int rcw_override; |
| 387 | unsigned int rcw_1; |
| 388 | unsigned int rcw_2; |
| 389 | /* control register 1 */ |
| 390 | unsigned int ddr_cdr1; |
York Sun | 7d69ea3 | 2012-10-08 07:44:22 +0000 | [diff] [blame] | 391 | unsigned int ddr_cdr2; |
York Sun | f8691fc | 2011-05-27 13:44:28 +0800 | [diff] [blame] | 392 | |
| 393 | unsigned int trwt_override; |
| 394 | unsigned int trwt; /* read-to-write turnaround */ |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 395 | } memctl_options_t; |
| 396 | |
York Sun | 79a779b | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 397 | phys_size_t fsl_ddr_sdram(void); |
| 398 | phys_size_t fsl_ddr_sdram_size(void); |
| 399 | phys_size_t fsl_other_ddr_sdram(unsigned long long base, |
| 400 | unsigned int first_ctrl, |
| 401 | unsigned int num_ctrls, |
| 402 | unsigned int dimm_slots_per_ctrl, |
| 403 | int (*board_need_reset)(void), |
| 404 | void (*board_reset)(void), |
| 405 | void (*board_de_reset)(void)); |
Kumar Gala | f582d98 | 2011-01-09 14:06:28 -0600 | [diff] [blame] | 406 | extern int fsl_use_spd(void); |
York Sun | 79a779b | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 407 | void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, |
| 408 | unsigned int ctrl_num, int step); |
York Sun | 016095d | 2012-10-08 07:44:24 +0000 | [diff] [blame] | 409 | u32 fsl_ddr_get_intl3r(void); |
York Sun | 79a779b | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 410 | void print_ddr_info(unsigned int start_ctrl); |
York Sun | 269c7eb | 2010-10-18 13:46:49 -0700 | [diff] [blame] | 411 | |
York Sun | 5e15555 | 2013-06-25 11:37:48 -0700 | [diff] [blame] | 412 | static void __board_assert_mem_reset(void) |
| 413 | { |
| 414 | } |
| 415 | |
| 416 | static void __board_deassert_mem_reset(void) |
| 417 | { |
| 418 | } |
| 419 | |
| 420 | void board_assert_mem_reset(void) |
| 421 | __attribute__((weak, alias("__board_assert_mem_reset"))); |
| 422 | |
| 423 | void board_deassert_mem_reset(void) |
| 424 | __attribute__((weak, alias("__board_deassert_mem_reset"))); |
| 425 | |
| 426 | static int __board_need_mem_reset(void) |
| 427 | { |
| 428 | return 0; |
| 429 | } |
| 430 | |
| 431 | int board_need_mem_reset(void) |
| 432 | __attribute__((weak, alias("__board_need_mem_reset"))); |
| 433 | |
Tang Yuantian | 064f126 | 2014-11-21 11:17:15 +0800 | [diff] [blame] | 434 | #if defined(CONFIG_DEEP_SLEEP) |
| 435 | void board_mem_sleep_setup(void); |
| 436 | bool is_warm_boot(void); |
| 437 | int fsl_dp_resume(void); |
| 438 | #endif |
Tang Yuantian | a7364af | 2014-04-17 15:33:46 +0800 | [diff] [blame] | 439 | |
Becky Bruce | 5e35d8a | 2010-12-17 17:17:56 -0600 | [diff] [blame] | 440 | /* |
| 441 | * The 85xx boards have a common prototype for fixed_sdram so put the |
| 442 | * declaration here. |
| 443 | */ |
| 444 | #ifdef CONFIG_MPC85xx |
| 445 | extern phys_size_t fixed_sdram(void); |
| 446 | #endif |
| 447 | |
| 448 | #if defined(CONFIG_DDR_ECC) |
| 449 | extern void ddr_enable_ecc(unsigned int dram_size); |
| 450 | #endif |
| 451 | |
| 452 | |
York Sun | 269c7eb | 2010-10-18 13:46:49 -0700 | [diff] [blame] | 453 | typedef struct fixed_ddr_parm{ |
| 454 | int min_freq; |
| 455 | int max_freq; |
| 456 | fsl_ddr_cfg_regs_t *ddr_settings; |
| 457 | } fixed_ddr_parm_t; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 458 | #endif |