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Sylvain Lemieux890cc772015-08-13 15:40:22 -04001/*
2 * Copyright (C) 2008 by NXP Semiconductors
3 * @Author: Based on code by Kevin Wells
4 * @Descr: USB driver - Embedded Artists LPC3250 OEM Board support functions
5 *
6 * Copyright (c) 2015 Tyco Fire Protection Products.
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11#include <common.h>
12#include <errno.h>
Mateusz Kulikowskiaf70d022016-01-23 11:54:31 +010013#include <wait_bit.h>
Sylvain Lemieux890cc772015-08-13 15:40:22 -040014#include <asm/io.h>
15#include <asm/arch/cpu.h>
16#include <asm/arch/clk.h>
17#include <usb.h>
18#include <i2c.h>
19
20/* OTG I2C controller module register structures */
21struct otgi2c_regs {
22 u32 otg_i2c_txrx; /* OTG I2C Tx/Rx Data FIFO */
23 u32 otg_i2c_stat; /* OTG I2C Status Register */
24 u32 otg_i2c_ctrl; /* OTG I2C Control Register */
25 u32 otg_i2c_clk_hi; /* OTG I2C Clock Divider high */
26 u32 otg_i2c_clk_lo; /* OTG I2C Clock Divider low */
27};
28
29/* OTG controller module register structures */
30struct otg_regs {
31 u32 reserved1[64];
32 u32 otg_int_sts; /* OTG int status register */
33 u32 otg_int_enab; /* OTG int enable register */
34 u32 otg_int_set; /* OTG int set register */
35 u32 otg_int_clr; /* OTG int clear register */
36 u32 otg_sts_ctrl; /* OTG status/control register */
37 u32 otg_timer; /* OTG timer register */
38 u32 reserved2[122];
39 struct otgi2c_regs otg_i2c;
40 u32 reserved3[824];
41 u32 otg_clk_ctrl; /* OTG clock control reg */
42 u32 otg_clk_sts; /* OTG clock status reg */
43};
44
45/* otg_sts_ctrl register definitions */
46#define OTG_HOST_EN (1 << 0) /* Enable host mode */
47
48/* otg_clk_ctrl and otg_clk_sts register definitions */
49#define OTG_CLK_AHB_EN (1 << 4) /* Enable AHB clock */
50#define OTG_CLK_OTG_EN (1 << 3) /* Enable OTG clock */
51#define OTG_CLK_I2C_EN (1 << 2) /* Enable I2C clock */
52#define OTG_CLK_HOST_EN (1 << 0) /* Enable host clock */
53
54/* ISP1301 USB transceiver I2C registers */
55#define MC1_SPEED_REG (1 << 0)
56#define MC1_DAT_SE0 (1 << 2)
57#define MC1_UART_EN (1 << 6)
58
59#define MC2_SPD_SUSP_CTRL (1 << 1)
60#define MC2_BI_DI (1 << 2)
61#define MC2_PSW_EN (1 << 6)
62
63#define OTG1_DP_PULLUP (1 << 0)
64#define OTG1_DM_PULLUP (1 << 1)
65#define OTG1_DP_PULLDOWN (1 << 2)
66#define OTG1_DM_PULLDOWN (1 << 3)
67#define OTG1_VBUS_DRV (1 << 5)
68
69#define ISP1301_I2C_ADDR CONFIG_USB_ISP1301_I2C_ADDR
70
71#define ISP1301_I2C_MODE_CONTROL_1_SET 0x04
72#define ISP1301_I2C_MODE_CONTROL_1_CLR 0x05
73#define ISP1301_I2C_MODE_CONTROL_2_SET 0x12
74#define ISP1301_I2C_MODE_CONTROL_2_CLR 0x13
75#define ISP1301_I2C_OTG_CONTROL_1_SET 0x06
76#define ISP1301_I2C_OTG_CONTROL_1_CLR 0x07
77#define ISP1301_I2C_INTERRUPT_LATCH_CLR 0x0B
78#define ISP1301_I2C_INTERRUPT_FALLING_CLR 0x0D
79#define ISP1301_I2C_INTERRUPT_RISING_CLR 0x0F
80
81static struct otg_regs *otg = (struct otg_regs *)USB_BASE;
82static struct clk_pm_regs *clk_pwr = (struct clk_pm_regs *)CLK_PM_BASE;
83
Sylvain Lemieux890cc772015-08-13 15:40:22 -040084static int isp1301_set_value(int reg, u8 value)
85{
86 return i2c_write(ISP1301_I2C_ADDR, reg, 1, &value, 1);
87}
88
89static void isp1301_configure(void)
90{
91 i2c_set_bus_num(I2C_2);
92
93 /*
94 * LPC32XX only supports DAT_SE0 USB mode
95 * This sequence is important
96 */
97
98 /* Disable transparent UART mode first */
99 isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_CLR, MC1_UART_EN);
100
101 isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_CLR, ~MC1_SPEED_REG);
102 isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_SET, MC1_SPEED_REG);
103 isp1301_set_value(ISP1301_I2C_MODE_CONTROL_2_CLR, ~0);
104 isp1301_set_value(ISP1301_I2C_MODE_CONTROL_2_SET,
105 MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL);
106
107 isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_CLR, ~0);
108 isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_SET, MC1_DAT_SE0);
109 isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_SET,
110 OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN);
111 isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_CLR,
112 OTG1_DM_PULLUP | OTG1_DP_PULLUP);
113 isp1301_set_value(ISP1301_I2C_INTERRUPT_LATCH_CLR, ~0);
114 isp1301_set_value(ISP1301_I2C_INTERRUPT_FALLING_CLR, ~0);
115 isp1301_set_value(ISP1301_I2C_INTERRUPT_RISING_CLR, ~0);
116
117 /* Enable usb_need_clk clock after transceiver is initialized */
118 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_USBDVND_EN);
119}
120
121static int usbpll_setup(void)
122{
123 u32 ret;
124
125 /* make sure clocks are disabled */
126 clrbits_le32(&clk_pwr->usb_ctrl,
127 CLK_USBCTRL_CLK_EN1 | CLK_USBCTRL_CLK_EN2);
128
129 /* start PLL clock input */
130 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_CLK_EN1);
131
132 /* Setup PLL. */
133 setbits_le32(&clk_pwr->usb_ctrl,
134 CLK_USBCTRL_FDBK_PLUS1(192 - 1));
135 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_POSTDIV_2POW(0x01));
136 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_PWRUP);
137
Mateusz Kulikowskiaf70d022016-01-23 11:54:31 +0100138 ret = wait_for_bit(__func__, &clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_STS,
139 true, CONFIG_SYS_HZ, false);
Sylvain Lemieux890cc772015-08-13 15:40:22 -0400140 if (ret)
141 return ret;
142
143 /* enable PLL output */
144 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_CLK_EN2);
145
146 return 0;
147}
148
149int usb_cpu_init(void)
150{
151 u32 ret;
152
153 /*
154 * USB pins routing setup is done by "lpc32xx_usb_init()" and should
155 * be call by board "board_init()" or "misc_init_r()" functions.
156 */
157
158 /* enable AHB slave USB clock */
159 setbits_le32(&clk_pwr->usb_ctrl,
160 CLK_USBCTRL_HCLK_EN | CLK_USBCTRL_BUS_KEEPER);
161
162 /* enable I2C clock */
163 writel(OTG_CLK_I2C_EN, &otg->otg_clk_ctrl);
Mateusz Kulikowskiaf70d022016-01-23 11:54:31 +0100164 ret = wait_for_bit(__func__, &otg->otg_clk_sts, OTG_CLK_I2C_EN, true,
165 CONFIG_SYS_HZ, false);
Sylvain Lemieux890cc772015-08-13 15:40:22 -0400166 if (ret)
167 return ret;
168
169 /* Configure ISP1301 */
170 isp1301_configure();
171
172 /* setup USB clocks and PLL */
173 ret = usbpll_setup();
174 if (ret)
175 return ret;
176
177 /* enable usb_host_need_clk */
178 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_USBHSTND_EN);
179
180 /* enable all needed USB clocks */
181 const u32 mask = OTG_CLK_AHB_EN | OTG_CLK_OTG_EN |
182 OTG_CLK_I2C_EN | OTG_CLK_HOST_EN;
183 writel(mask, &otg->otg_clk_ctrl);
184
Mateusz Kulikowskiaf70d022016-01-23 11:54:31 +0100185 ret = wait_for_bit(__func__, &otg->otg_clk_sts, mask, true,
186 CONFIG_SYS_HZ, false);
Sylvain Lemieux890cc772015-08-13 15:40:22 -0400187 if (ret)
188 return ret;
189
190 setbits_le32(&otg->otg_sts_ctrl, OTG_HOST_EN);
191 isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_SET, OTG1_VBUS_DRV);
192
193 return 0;
194}
195
196int usb_cpu_stop(void)
197{
198 /* vbus off */
199 isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_SET, OTG1_VBUS_DRV);
200
201 clrbits_le32(&otg->otg_sts_ctrl, OTG_HOST_EN);
202
203 clrbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_HCLK_EN);
204
205 return 0;
206}
207
208int usb_cpu_init_fail(void)
209{
210 return usb_cpu_stop();
211}