blob: d9409bad655200504bf77d0bc6d585195501c437 [file] [log] [blame]
Michal Simeka335bd22016-04-07 16:00:11 +02001/*
2 * Configuration for Xilinx ZynqMP zc1751 XM019 DC5
3 *
4 * (C) Copyright 2015 Xilinx, Inc.
5 * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
6 * Michal Simek <michal.simek@xilinx.com>
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11#ifndef __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H
12#define __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H
13
14#define CONFIG_ZYNQ_SDHCI0
15#define CONFIG_ZYNQ_I2C0
16#define CONFIG_ZYNQ_I2C1
17#define CONFIG_SYS_I2C_ZYNQ
18
19#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm019 dc5"
20
21#define CONFIG_KERNEL_FDT_OFST_SIZE \
22 "kernel_offset=0x400000\0" \
23 "fdt_offset=0x2400000\0" \
24 "kernel_size=0x2000000\0" \
25 "fdt_size=0x80000\0" \
26 "board=zc1751-dc5\0"
27
28#include <configs/xilinx_zynqmp.h>
29
30#endif /* __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H */