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git01.mediatek.com / filogic / uboot / a2fe8b2b44ca94610b4838583e38166891c7a198 / . / board / sunxi / gmac.c
blob: d8fdf7728e04537f27e4a301bbc1ba12f25eb79b [file] [log] [blame]
Ian Campbellba8311f2014-05-05 11:52:28 +0100[diff] [blame]1#include <common.h>
2#include <netdev.h>
3#include <miiphy.h>
4#include <asm/gpio.h>
5#include <asm/io.h>
6#include <asm/arch/clock.h>
7#include <asm/arch/gpio.h>
8
Hans de Goede42cbbe32016-03-17 13:53:03 +0100[diff] [blame]9void eth_init_board(void)
Ian Campbellba8311f2014-05-05 11:52:28 +0100[diff] [blame]10{
11 int pin;
12 struct sunxi_ccm_reg *const ccm =
13 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
14
Ian Campbellba8311f2014-05-05 11:52:28 +0100[diff] [blame]15 /* Set MII clock */
Chen-Yu Tsaic1f6aa32014-06-09 11:37:01 +0200[diff] [blame]16#ifdef CONFIG_RGMII
Ian Campbellba8311f2014-05-05 11:52:28 +0100[diff] [blame]17 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
18 CCM_GMAC_CTRL_GPIT_RGMII);
Hans de Goedebf880fe2015-01-25 12:10:48 +0100[diff] [blame]19 setbits_le32(&ccm->gmac_clk_cfg,
20 CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY));
Chen-Yu Tsaic1f6aa32014-06-09 11:37:01 +0200[diff] [blame]21#else
22 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
23 CCM_GMAC_CTRL_GPIT_MII);
24#endif
Ian Campbellba8311f2014-05-05 11:52:28 +0100[diff] [blame]25
Hans de Goede1a9a6fb2014-11-21 17:19:45 +0100[diff] [blame]26#ifndef CONFIG_MACH_SUN6I
Ian Campbellba8311f2014-05-05 11:52:28 +0100[diff] [blame]27 /* Configure pin mux settings for GMAC */
Stefan Mavrodieveaee8582017-11-03 08:56:51 +0200[diff] [blame]28#ifdef CONFIG_SUN7I_GMAC_FORCE_TXERR
29 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) {
30#else
Ian Campbellba8311f2014-05-05 11:52:28 +0100[diff] [blame]31 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
Stefan Mavrodieveaee8582017-11-03 08:56:51 +0200[diff] [blame]32#endif
Chen-Yu Tsaic1f6aa32014-06-09 11:37:01 +0200[diff] [blame]33#ifdef CONFIG_RGMII
Ian Campbellba8311f2014-05-05 11:52:28 +0100[diff] [blame]34 /* skip unused pins in RGMII mode */
35 if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
36 continue;
Chen-Yu Tsaic1f6aa32014-06-09 11:37:01 +0200[diff] [blame]37#endif
Paul Kocialkowskiae358a42015-03-22 18:12:22 +0100[diff] [blame]38 sunxi_gpio_set_cfgpin(pin, SUN7I_GPA_GMAC);
Ian Campbellba8311f2014-05-05 11:52:28 +0100[diff] [blame]39 sunxi_gpio_set_drv(pin, 3);
40 }
Hans de Goede1a9a6fb2014-11-21 17:19:45 +0100[diff] [blame]41#elif defined CONFIG_RGMII
42 /* Configure sun6i RGMII mode pin mux settings */
43 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) {
Paul Kocialkowskiae358a42015-03-22 18:12:22 +0100[diff] [blame]44 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
Hans de Goede1a9a6fb2014-11-21 17:19:45 +0100[diff] [blame]45 sunxi_gpio_set_drv(pin, 3);
46 }
47 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
Paul Kocialkowskiae358a42015-03-22 18:12:22 +0100[diff] [blame]48 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
Hans de Goede1a9a6fb2014-11-21 17:19:45 +0100[diff] [blame]49 sunxi_gpio_set_drv(pin, 3);
50 }
51 for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) {
Paul Kocialkowskiae358a42015-03-22 18:12:22 +0100[diff] [blame]52 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
Hans de Goede1a9a6fb2014-11-21 17:19:45 +0100[diff] [blame]53 sunxi_gpio_set_drv(pin, 3);
54 }
55 for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) {
Paul Kocialkowskiae358a42015-03-22 18:12:22 +0100[diff] [blame]56 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
Hans de Goede1a9a6fb2014-11-21 17:19:45 +0100[diff] [blame]57 sunxi_gpio_set_drv(pin, 3);
58 }
59#elif defined CONFIG_GMII
60 /* Configure sun6i GMII mode pin mux settings */
61 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) {
Paul Kocialkowskiae358a42015-03-22 18:12:22 +0100[diff] [blame]62 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
Hans de Goede1a9a6fb2014-11-21 17:19:45 +0100[diff] [blame]63 sunxi_gpio_set_drv(pin, 2);
64 }
65#else
66 /* Configure sun6i MII mode pin mux settings */
67 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++)
Paul Kocialkowskiae358a42015-03-22 18:12:22 +0100[diff] [blame]68 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
Hans de Goede1a9a6fb2014-11-21 17:19:45 +0100[diff] [blame]69 for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++)
Paul Kocialkowskiae358a42015-03-22 18:12:22 +0100[diff] [blame]70 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
Hans de Goede1a9a6fb2014-11-21 17:19:45 +0100[diff] [blame]71 for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++)
Paul Kocialkowskiae358a42015-03-22 18:12:22 +0100[diff] [blame]72 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
Hans de Goede1a9a6fb2014-11-21 17:19:45 +0100[diff] [blame]73 for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++)
Paul Kocialkowskiae358a42015-03-22 18:12:22 +0100[diff] [blame]74 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
Hans de Goede1a9a6fb2014-11-21 17:19:45 +0100[diff] [blame]75 for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
Paul Kocialkowskiae358a42015-03-22 18:12:22 +0100[diff] [blame]76 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
Hans de Goede1a9a6fb2014-11-21 17:19:45 +0100[diff] [blame]77#endif
Ian Campbellba8311f2014-05-05 11:52:28 +0100[diff] [blame]78}