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Yuri Tikhonovc147d482008-02-04 14:10:42 +01001/*
2 * (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com
3 *
4 * Developed for DENX Software Engineering GmbH
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Yuri Tikhonovc147d482008-02-04 14:10:42 +01007 */
8
9#include <common.h>
10
Yuri Tikhonovc147d482008-02-04 14:10:42 +010011#include <post.h>
12
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020013#if CONFIG_POST & CONFIG_SYS_POST_DSP
Yuri Tikhonovc147d482008-02-04 14:10:42 +010014#include <asm/io.h>
15
16/* This test verifies DSP status bits in FPGA */
17
18DECLARE_GLOBAL_DATA_PTR;
19
Sascha Laue249310a2010-08-19 09:38:56 +020020#define DSP_STATUS_REG 0xC4000008
21#define FPGA_STATUS_REG 0xC400000C
Yuri Tikhonovc147d482008-02-04 14:10:42 +010022
23int dsp_post_test(int flags)
24{
Sascha Laue249310a2010-08-19 09:38:56 +020025 uint old_value;
Yuri Tikhonovc147d482008-02-04 14:10:42 +010026 uint read_value;
27 int ret;
28
Sascha Laue249310a2010-08-19 09:38:56 +020029 /* momorize fpga status */
30 old_value = in_be32((void *)FPGA_STATUS_REG);
31 /* enable outputs */
32 out_be32((void *)FPGA_STATUS_REG, 0x30);
33
34 /* generate sync signal */
35 out_be32((void *)DSP_STATUS_REG, 0x300);
36 udelay(5);
37 out_be32((void *)DSP_STATUS_REG, 0);
38 udelay(500);
39
40 /* read status */
Yuri Tikhonovc147d482008-02-04 14:10:42 +010041 ret = 0;
42 read_value = in_be32((void *)DSP_STATUS_REG) & 0x3;
Sascha Laue249310a2010-08-19 09:38:56 +020043 if (read_value != 0x03) {
Yuri Tikhonovc147d482008-02-04 14:10:42 +010044 post_log("\nDSP status read %08X\n", read_value);
45 ret = 1;
46 }
47
Sascha Laue249310a2010-08-19 09:38:56 +020048 /* restore fpga status */
49 out_be32((void *)FPGA_STATUS_REG, old_value);
50
Yuri Tikhonovc147d482008-02-04 14:10:42 +010051 return ret;
52}
53
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020054#endif /* CONFIG_POST & CONFIG_SYS_POST_DSP */