| Cheick Traore | a2d2027 | 2025-03-11 15:30:34 +0100 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* |
| 3 | * Copyright (C) 2025, STMicroelectronics - All Rights Reserved |
| 4 | * Author: Cheick Traore <cheick.traore@foss.st.com> |
| 5 | * |
| 6 | * Originally based on the Linux kernel v6.1 include/linux/mfd/stm32-timers.h. |
| 7 | */ |
| 8 | |
| 9 | #ifndef __STM32_TIMERS_H |
| 10 | #define __STM32_TIMERS_H |
| 11 | |
| 12 | #include <clk.h> |
| 13 | |
| 14 | #define TIM_CR1 0x00 /* Control Register 1 */ |
| 15 | #define TIM_CR2 0x04 /* Control Register 2 */ |
| 16 | #define TIM_SMCR 0x08 /* Slave mode control reg */ |
| 17 | #define TIM_DIER 0x0C /* DMA/interrupt register */ |
| 18 | #define TIM_SR 0x10 /* Status register */ |
| 19 | #define TIM_EGR 0x14 /* Event Generation Reg */ |
| 20 | #define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */ |
| 21 | #define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */ |
| 22 | #define TIM_CCER 0x20 /* Capt/Comp Enable Reg */ |
| 23 | #define TIM_CNT 0x24 /* Counter */ |
| 24 | #define TIM_PSC 0x28 /* Prescaler */ |
| 25 | #define TIM_ARR 0x2c /* Auto-Reload Register */ |
| 26 | #define TIM_CCRx(x) (0x34 + 4 * ((x) - 1)) /* Capt/Comp Register x (x ∈ {1, .. 4}) */ |
| 27 | #define TIM_BDTR 0x44 /* Break and Dead-Time Reg */ |
| 28 | #define TIM_DCR 0x48 /* DMA control register */ |
| 29 | #define TIM_DMAR 0x4C /* DMA register for transfer */ |
| 30 | #define TIM_TISEL 0x68 /* Input Selection */ |
| 31 | |
| 32 | #define TIM_CR1_CEN BIT(0) /* Counter Enable */ |
| 33 | #define TIM_CR1_ARPE BIT(7) |
| 34 | #define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12)) |
| 35 | #define TIM_CCER_CC1E BIT(0) |
| 36 | #define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */ |
| 37 | #define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */ |
| 38 | #define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */ |
| 39 | #define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */ |
| 40 | #define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */ |
| 41 | #define TIM_BDTR_MOE BIT(15) /* Main Output Enable */ |
| 42 | #define TIM_EGR_UG BIT(0) /* Update Generation */ |
| 43 | |
| 44 | #define MAX_TIM_PSC 0xFFFF |
| 45 | |
| 46 | struct stm32_timers_plat { |
| 47 | void __iomem *base; |
| 48 | }; |
| 49 | |
| 50 | struct stm32_timers_priv { |
| 51 | u32 max_arr; |
| 52 | ulong rate; |
| 53 | }; |
| 54 | |
| 55 | #endif |