Blame - doc/README.dk1s10_mldk20 - filogic/uboot

wdenk

c0bc2e1

2004-02-09 23:12:24 +0000

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TODO: specify IDE i/f

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===============================================================================

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C P U , M E M O R Y , I N / O U T C O M P O N E N T S

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===============================================================================

see also [1]-[5]

CPU: "LDK2"

32 bit NIOS for 75 MHz

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512 Byte for register file (30 levels)

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with out instruction cache

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with out data cache

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2 KByte On Chip ROM with GERMS boot monitor

with out On Chip RAM

MSTEP multiplier

no Debug Core

no On Chip Instrumentation (OCI)

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Jean-Christophe PLAGNIOL-VILLARD

0383694

2008-10-16 15:01:15 +0200

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U-Boot CFG: CONFIG_SYS_NIOS_CPU_CLK = 75000000

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CONFIG_SYS_NIOS_CPU_ICACHE = (not present)

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CONFIG_SYS_NIOS_CPU_DCACHE = (not present)

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CONFIG_SYS_NIOS_CPU_REG_NUMS = 512

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CONFIG_SYS_NIOS_CPU_MUL = 0

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CONFIG_SYS_NIOS_CPU_MSTEP = 1

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CONFIG_SYS_NIOS_CPU_DBG_CORE = 0

wdenk

c0bc2e1

2004-02-09 23:12:24 +0000

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IRQ: Nr. | used by

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------+--------------------------------------------------------

Jean-Christophe PLAGNIOL-VILLARD

0383694

2008-10-16 15:01:15 +0200

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16 | TIMER0 | CONFIG_SYS_NIOS_CPU_TIMER0_IRQ = 16

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17 | UART0 | CONFIG_SYS_NIOS_CPU_UART0_IRQ = 17

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18 | UART1 | CONFIG_SYS_NIOS_CPU_UART1_IRQ = 18

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20 | LAN91C111 | CONFIG_SYS_NIOS_CPU_LAN0_IRQ = 20

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25 | IDE0 | CONFIG_SYS_NIOS_CPU_IDE0_IRQ = 25

wdenk

c0bc2e1

2004-02-09 23:12:24 +0000

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MEMORY: 8 MByte Flash

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16 MByte SDRAM

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Timer: TIMER0: high priority programmable timer (IRQ16)

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Jean-Christophe PLAGNIOL-VILLARD

0383694

2008-10-16 15:01:15 +0200

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U-Boot CFG: CONFIG_SYS_NIOS_CPU_TICK_TIMER = 0

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CONFIG_SYS_NIOS_CPU_USER_TIMER = (not present)

wdenk

c0bc2e1

2004-02-09 23:12:24 +0000

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PIO: Nr. | description

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------+--------------------------------------------------------

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PIO0 | CFPOWER: 1 output to controll CF power supply

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PIO1 | BUTTON: 4 inputs for user push buttons (no IRQ)

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------+--------------------------------------------------------

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not | LCD: 11 in/outputs for ASCII LCD

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pres.| LED: 8 outputs for user LEDs

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| SEVENSEG: 16 outputs for user seven segment display

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| RECONF: 1 in/output for . . . . . . . . . . . .

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| CFPRESENT: 1 input for CF present event (IRQ35)

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| CFATASEL: 1 output to controll CF ATA card select

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Jean-Christophe PLAGNIOL-VILLARD

0383694

2008-10-16 15:01:15 +0200

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U-Boot CFG: CONFIG_SYS_NIOS_CPU_BUTTON_PIO = 1

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CONFIG_SYS_NIOS_CPU_LCD_PIO = (not present)

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CONFIG_SYS_NIOS_CPU_LED_PIO = (not present)

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CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO = (not present)

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CONFIG_SYS_NIOS_CPU_RECONF_PIO = (not present)

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CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO = (not present)

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CONFIG_SYS_NIOS_CPU_CFPOWER_PIO = 0

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CONFIG_SYS_NIOS_CPU_CFATASEL_PIO = (not present)

wdenk

c0bc2e1

2004-02-09 23:12:24 +0000

[diff] [blame]

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UART: UART0: fixed baudrate of 115200, fixed protocol 8N2,

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without handshake RTS/CTS (IRQ17)

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UART1: fixed baudrate of 115200, fixed protocol 8N1,

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without handshake RTS/CTS (IRQ18)

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LAN: SMsC LAN91C111 with:

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- offset 0x300 (LAN91C111_REGISTERS_OFFSET)

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- data bus width 32 bit (LAN91C111_DATA_BUS_WIDTH)

IDE: (TODO)

===============================================================================

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M E M O R Y M A P

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===============================================================================

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- - - - - - - - - - - external memory - - - - - - - - - - - - - - - - - - -

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Jean-Christophe PLAGNIOL-VILLARD

0383694

2008-10-16 15:01:15 +0200

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0x02000000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_STACK

wdenk

c0bc2e1

2004-02-09 23:12:24 +0000

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0x02000000 --+32-----------16|15------------0+

| . | \ \

| . | | |

| . | | > stack area

| . | | |

| . | | V

| . | |

| . | |

Jean-Christophe PLAGNIOL-VILLARD

0383694

2008-10-16 15:01:15 +0200

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SDRAM | . | > CONFIG_SYS_NIOS_CPU_SDRAM_SIZE

wdenk

c0bc2e1

2004-02-09 23:12:24 +0000

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| . | | = 0x01000000

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| . | |

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0x01000100 |- - - - - - - - - - - - - - - -+-|-

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| . | | \

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| . | | |

Jean-Christophe PLAGNIOL-VILLARD

0383694

2008-10-16 15:01:15 +0200

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| . | | > CONFIG_SYS_NIOS_CPU_VEC_SIZE

wdenk

c0bc2e1

2004-02-09 23:12:24 +0000

[diff] [blame]

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| . | | | = 0x00000100

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| | / /

Jean-Christophe PLAGNIOL-VILLARD

0383694

2008-10-16 15:01:15 +0200

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0x01000000 |- - - - - - - - - - - - - - - -+- - CONFIG_SYS_NIOS_CPU_VEC_BASE

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0x01000000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_SDRAM_BASE

wdenk

c0bc2e1

2004-02-09 23:12:24 +0000

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| sector 127 | \

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+ 0x7f0000 |- - - - - - - - - - - - - - - -| |

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| : | |

Jean-Christophe PLAGNIOL-VILLARD

0383694

2008-10-16 15:01:15 +0200

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Flash |- - - - : - - - -| > CONFIG_SYS_NIOS_CPU_FLASH_SIZE

wdenk

c0bc2e1

2004-02-09 23:12:24 +0000

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| sector 1 : | | = 0x00800000

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+ 0x010000 |- - - - - - - - - - - - - - - -| |

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| sector 0 (size = 0x10000) | /

Jean-Christophe PLAGNIOL-VILLARD

0383694

2008-10-16 15:01:15 +0200

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0x00800000 ---8-------------4|3-------------0- CONFIG_SYS_NIOS_CPU_FLASH_BASE

wdenk

c0bc2e1

2004-02-09 23:12:24 +0000

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| |

: gap :

: :

- - - - - - - - - - - external i/o - - - - - - - - - - - - - - - - - - -

: :

: gap :

| |

0x00020000 ---32-----------16|15------------0-

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| gap | \

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0x00010310 --+-------------------------------| |

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| | |

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| register bank (size = 0x10) | |

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| +--------.---.---.--- | |

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| | bank 0 \ 1 \ 2 \ 3 \ | |

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| |---------------------------+ | |

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| |- - - - - - -|- - - - - - -| | > na_enet_size

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| | RPCR | MIR | | | = 0x00010000

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| |- - - - - - -|- - - - - - -| | |

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| | COUNTER | RCR | | |

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| |- - - - - - -|- - - - - - -| | |

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| | EPH STATUS | TCR | | |

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| +---------------------------+ | |

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0x00010300 --+--LAN91C111_REGISTERS_OFFSET---| |

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| gap | /

Jean-Christophe PLAGNIOL-VILLARD

0383694

2008-10-16 15:01:15 +0200

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0x00010000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_LAN0_BASE

wdenk

c0bc2e1

2004-02-09 23:12:24 +0000

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| |

: gap :

: :

- - - - - - - - - - - on chip i/o - - - - - - - - - - - - - - - - - - -

: :

: gap :

| |

0x00000980 ---32-----------16|15------------0-

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| | | \

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: (real size : : |

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IDE i/f : and content : : > 0x00000080

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[5] : unknown) : : |

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| | | /

Jean-Christophe PLAGNIOL-VILLARD

0383694

2008-10-16 15:01:15 +0200

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0x00000900 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_IDE0

wdenk

c0bc2e1

2004-02-09 23:12:24 +0000

[diff] [blame]

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| | \

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: gap : > (space for PIO4..7)

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| | /

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0x000008c0 ---32-----------16|15------------0-

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| (unused) | \

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+ 0x1c |- - - - - - - - - - - - - - - -| |

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| (unused) | |

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+ 0x18 |- - - - - - - - - - - - - - - -| |

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| (unused) | |

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+ 0x14 |- - - - - - - - - - - - - - - -| |

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UART1 | (unused) | > 0x00000020

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[2] + 0x10 |- - - - - - - - - - - - - - - -| |

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| control (10 bit) (rw) | |

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+ 0x0c |- - - - - - - - - - - - - - - -| |

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| status (10 bit) (rw) | |

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+ 0x08 |- - - - - - - - - - - - - - - -| |

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| txdata (8 bit) (wo) | |

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+ 0x04 |- - - - - - - - - - - - - - - -| |

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| rxdata (8 bit) (ro) | /

Jean-Christophe PLAGNIOL-VILLARD

0383694

2008-10-16 15:01:15 +0200

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0x000008a0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_UART1

wdenk

c0bc2e1

2004-02-09 23:12:24 +0000

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| | \

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: gap : > (space for PIO2..3)

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| | /

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0x00000880 ---32-----------16|15------------0-

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| edgecapture (4 bit) (rw) | \

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+ 0x0c |- - - - - - - - - - - - - - - -| |

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PIO1 | interruptmask (4 bit) (rw) | |

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[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010

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| (unused) | |

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+ 0x04 |- - - - - - - - - - - - - - - -| |

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| data (4 bit) (ro) | /

Jean-Christophe PLAGNIOL-VILLARD

0383694

2008-10-16 15:01:15 +0200

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0x00000870 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO1

wdenk

c0bc2e1

2004-02-09 23:12:24 +0000

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| (unused) | \

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+ 0x0c |- - - - - - - - - - - - - - - -| |

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PIO0 | (unused) | |

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[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010

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| (unused) | |

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+ 0x04 |- - - - - - - - - - - - - - - -| |

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| data (1 bit) (wo) | /

Jean-Christophe PLAGNIOL-VILLARD

0383694

2008-10-16 15:01:15 +0200

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0x00000860 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO0

wdenk

c0bc2e1

2004-02-09 23:12:24 +0000

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| (unused) | \

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+ 0x1c |- - - - - - - - - - - - - - - -| |

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| (unused) | |

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+ 0x18 |- - - - - - - - - - - - - - - -| |

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| snaph (16 bit) (rw) | |

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+ 0x14 |- - - - - - - - - - - - - - - -| |

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TIMER0 | snapl (16 bit) (rw) | |

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[3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020

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| periodh (16 bit) (rw) | |

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+ 0x0c |- - - - - - - - - - - - - - - -| |

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| periodl (16 bit) (rw) | |

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+ 0x08 |- - - - - - - - - - - - - - - -| |

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| control (4 bit) (rw) | |

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+ 0x04 |- - - - - - - - - - - - - - - -| |

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| status (2 bit) (rw) | /

Jean-Christophe PLAGNIOL-VILLARD

0383694

2008-10-16 15:01:15 +0200

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0x00000840 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_TIMER0

wdenk

c0bc2e1

2004-02-09 23:12:24 +0000

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| | \

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: gap : > (space for UART2)

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| | /

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0x00000820 ---32-----------16|15------------0-

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| (unused) | \

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+ 0x1c |- - - - - - - - - - - - - - - -| |

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| (unused) | |

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+ 0x18 |- - - - - - - - - - - - - - - -| |

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| (unused) | |

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+ 0x14 |- - - - - - - - - - - - - - - -| |

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UART0 | (unused) | > 0x00000020

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[2] + 0x10 |- - - - - - - - - - - - - - - -| |

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| control (10 bit) (rw) | |

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+ 0x0c |- - - - - - - - - - - - - - - -| |

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| status (10 bit) (rw) | |

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+ 0x08 |- - - - - - - - - - - - - - - -| |

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| txdata (8 bit) (wo) | |

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+ 0x04 |- - - - - - - - - - - - - - - -| |

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| rxdata (8 bit) (ro) | /

Jean-Christophe PLAGNIOL-VILLARD

0383694

2008-10-16 15:01:15 +0200

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0x00000800 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_UART0

wdenk

c0bc2e1

2004-02-09 23:12:24 +0000

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- - - - - - - - - - - on chip memory 1 - - - - - - - - - - -

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0x00000800 ---32-----------16|15------------0-

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| : | \

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| : | |

Jean-Christophe PLAGNIOL-VILLARD

0383694

2008-10-16 15:01:15 +0200

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GERMS | : | > CONFIG_SYS_NIOS_CPU_ROM_SIZE

wdenk

c0bc2e1

2004-02-09 23:12:24 +0000

[diff] [blame]

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| : | | = 0x00000800

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| : | /

Jean-Christophe PLAGNIOL-VILLARD

0383694

2008-10-16 15:01:15 +0200

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0x00000000 |- - - - - - - - - - - - - - - -+- - CONFIG_SYS_NIOS_CPU_RST_VECT

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0x00000000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_ROM_BASE

wdenk

c0bc2e1

2004-02-09 23:12:24 +0000

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===============================================================================

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F L A S H M E M O R Y A L L O C A T I O N

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===============================================================================

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0x01000000 ---8-------------4|3-------------0-

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| : | \

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SAFE | : | > 1 MByte

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FPGA conf. | : | / (NOT usable by software)

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0x00f00000 --+- - - - - - - -:- - - - - - - -+-

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| : | \

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USER | : | > 1 MByte

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FPGA conf. | : | / (NOT usable by software)

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0x00e00000 --+- - - - - - - -:- - - - - - - -+-

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| : | \

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| : | |

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WEB pages | : | > 2 MByte

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| : | | (provisory usable)

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| : | /

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0x00c00000 --+- - - - - - - -:- - - - - - - -+-

| : | \

| : | |

| : | |

| : | > 4 MByte free for use

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| : | |

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0x00840000 --+- - - - - - - -:- - - - - - - -+-|- u-boot environment

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| : | /

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0x00800000 |- - - - - - - -:- - - - - - - -+- - u-boot _start()

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0x00800000 ---8-------------4|3-------------0-

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===============================================================================

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R E F E R E N C E S

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===============================================================================

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[1] http://www.altera.com/literature/manual/mnl_nios_board_stratix_1s10.pdf

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[2] http://www.altera.com/literature/ds/ds_nios_uart.pdf

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[3] http://www.altera.com/literature/ds/ds_nios_timer.pdf

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[4] http://www.altera.com/literature/ds/ds_nios_pio.pdf

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[5] http://www.opencores.org/projects/ata/

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http://www.t13.org/index.html

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===============================================================================

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Stephan Linz <linz@li-pro.net>