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Magnus Lilja6eeb6f72009-07-01 01:07:55 +02001/*
2 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
3 *
4 * (C) Copyright 2004
5 * Texas Instruments.
6 * Richard Woodruff <r-woodruff2@ti.com>
7 * Kshitij Gupta <kshitij@ti.com>
8 *
9 * Configuration settings for the Freescale i.MX31 PDK board.
10 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +020011 * SPDX-License-Identifier: GPL-2.0+
Magnus Lilja6eeb6f72009-07-01 01:07:55 +020012 */
13
14#ifndef __CONFIG_H
15#define __CONFIG_H
16
Stefano Babic78129d92011-03-14 15:43:56 +010017#include <asm/arch/imx-regs.h>
Magnus Lilja9828d352010-01-17 17:46:11 +010018
Magnus Lilja6eeb6f72009-07-01 01:07:55 +020019/* High Level Configuration Options */
Masahiro Yamadaa8b4c8c2014-11-06 14:59:37 +090020#define CONFIG_MX31 /* This is a mx31 */
Magnus Lilja6eeb6f72009-07-01 01:07:55 +020021
Fabio Estevam7fa7df32011-04-26 11:04:37 +000022#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
23#define CONFIG_SETUP_MEMORY_TAGS
24#define CONFIG_INITRD_TAG
Magnus Lilja6eeb6f72009-07-01 01:07:55 +020025
Fabio Estevam01bc4b42011-09-22 08:07:14 +000026#define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS
27
Benoît Thébaudeauefb7c002013-04-11 09:35:51 +000028#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
29#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
30#define CONFIG_SPL_MAX_SIZE 2048
Benoît Thébaudeauefb7c002013-04-11 09:35:51 +000031
32#define CONFIG_SPL_TEXT_BASE 0x87dc0000
33#define CONFIG_SYS_TEXT_BASE 0x87e00000
34
35#ifndef CONFIG_SPL_BUILD
Magnus Lilja6eeb6f72009-07-01 01:07:55 +020036#define CONFIG_SKIP_LOWLEVEL_INIT
Magnus Lilja24f8b412009-07-04 10:31:24 +020037#endif
Magnus Lilja6eeb6f72009-07-01 01:07:55 +020038
39/*
40 * Size of malloc() pool
41 */
Magnus Lilja9828d352010-01-17 17:46:11 +010042#define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024)
Magnus Lilja6eeb6f72009-07-01 01:07:55 +020043
44/*
45 * Hardware drivers
46 */
47
Fabio Estevam7fa7df32011-04-26 11:04:37 +000048#define CONFIG_MXC_UART
Stefano Babic1ca47d92011-11-22 15:22:39 +010049#define CONFIG_MXC_UART_BASE UART1_BASE
Stefano Babic5fed0b82011-09-07 10:51:43 +000050#define CONFIG_MXC_GPIO
Magnus Lilja6eeb6f72009-07-01 01:07:55 +020051
Fabio Estevam7fa7df32011-04-26 11:04:37 +000052#define CONFIG_HARD_SPI
53#define CONFIG_MXC_SPI
Magnus Lilja6eeb6f72009-07-01 01:07:55 +020054#define CONFIG_DEFAULT_SPI_BUS 1
Stefano Babic4c596992010-08-23 20:41:19 +020055#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
Magnus Lilja6eeb6f72009-07-01 01:07:55 +020056
Stefano Babic3d4088e2011-10-08 11:04:22 +020057/* PMIC Controller */
Łukasz Majewski1b6d9ed2012-11-13 03:22:14 +000058#define CONFIG_POWER
59#define CONFIG_POWER_SPI
60#define CONFIG_POWER_FSL
Stefano Babice0432032010-04-16 17:11:19 +020061#define CONFIG_FSL_PMIC_BUS 1
62#define CONFIG_FSL_PMIC_CS 2
63#define CONFIG_FSL_PMIC_CLK 1000000
Stefano Babic4c596992010-08-23 20:41:19 +020064#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
Stefano Babic3d4088e2011-10-08 11:04:22 +020065#define CONFIG_FSL_PMIC_BITLEN 32
Fabio Estevam3f8d1782011-10-24 06:44:15 +000066#define CONFIG_RTC_MC13XXX
Magnus Lilja6eeb6f72009-07-01 01:07:55 +020067
Magnus Lilja6eeb6f72009-07-01 01:07:55 +020068/* allow to overwrite serial and ethaddr */
69#define CONFIG_ENV_OVERWRITE
70#define CONFIG_CONS_INDEX 1
Magnus Lilja6eeb6f72009-07-01 01:07:55 +020071
72/***********************************************************
73 * Command definition
74 ***********************************************************/
Magnus Lilja6eeb6f72009-07-01 01:07:55 +020075#define CONFIG_CMD_DATE
Magnus Lilja9828d352010-01-17 17:46:11 +010076#define CONFIG_CMD_NAND
Magnus Lilja6eeb6f72009-07-01 01:07:55 +020077
Magnus Lilja6eeb6f72009-07-01 01:07:55 +020078
79#define CONFIG_EXTRA_ENV_SETTINGS \
80 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
81 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
82 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
83 "bootcmd=run bootcmd_net\0" \
84 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
Magnus Lilja9828d352010-01-17 17:46:11 +010085 "tftpboot 0x81000000 uImage-mx31; bootm\0" \
Benoît Thébaudeauefb7c002013-04-11 09:35:51 +000086 "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \
Magnus Lilja9828d352010-01-17 17:46:11 +010087 "nand erase 0x0 0x40000; " \
88 "nand write 0x81000000 0x0 0x40000\0"
Magnus Lilja6eeb6f72009-07-01 01:07:55 +020089
Fabio Estevam7fa7df32011-04-26 11:04:37 +000090#define CONFIG_SMC911X
Ben Warrenfbfdd3a2009-07-20 22:01:11 -070091#define CONFIG_SMC911X_BASE 0xB6000000
Fabio Estevam7fa7df32011-04-26 11:04:37 +000092#define CONFIG_SMC911X_32_BIT
Magnus Lilja6eeb6f72009-07-01 01:07:55 +020093
94/*
95 * Miscellaneous configurable options
96 */
97#define CONFIG_SYS_LONGHELP /* undef to save memory */
Magnus Lilja6eeb6f72009-07-01 01:07:55 +020098#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Magnus Lilja6eeb6f72009-07-01 01:07:55 +020099/* max number of command args */
100#define CONFIG_SYS_MAXARGS 16
101/* Boot Argument Buffer Size */
102#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
103
104/* memtest works on */
105#define CONFIG_SYS_MEMTEST_START 0x80000000
Fabio Estevam4fc03742012-02-09 14:25:07 +0000106#define CONFIG_SYS_MEMTEST_END 0x80010000
Magnus Lilja6eeb6f72009-07-01 01:07:55 +0200107
108/* default load address */
109#define CONFIG_SYS_LOAD_ADDR 0x81000000
110
Fabio Estevam7fa7df32011-04-26 11:04:37 +0000111#define CONFIG_CMDLINE_EDITING
Magnus Lilja6eeb6f72009-07-01 01:07:55 +0200112
113/*-----------------------------------------------------------------------
Magnus Lilja6eeb6f72009-07-01 01:07:55 +0200114 * Physical Memory Map
115 */
116#define CONFIG_NR_DRAM_BANKS 1
117#define PHYS_SDRAM_1 CSD0_BASE
118#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
119
Fabio Estevam66a8b4d2011-02-09 01:17:55 +0000120#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
121#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
122#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
Fabio Estevame072a8a2011-07-04 09:29:46 +0000123#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
124 GENERATED_GBL_DATA_SIZE)
125#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
Benoît Thébaudeauefb7c002013-04-11 09:35:51 +0000126 CONFIG_SYS_INIT_RAM_SIZE)
Fabio Estevam66a8b4d2011-02-09 01:17:55 +0000127
Masahiro Yamada8cea9b52017-02-11 22:43:54 +0900128/*
129 * environment organization
Magnus Lilja6eeb6f72009-07-01 01:07:55 +0200130 */
Fabio Estevam7fa7df32011-04-26 11:04:37 +0000131#define CONFIG_ENV_IS_IN_NAND
Magnus Lilja9828d352010-01-17 17:46:11 +0100132#define CONFIG_ENV_OFFSET 0x40000
133#define CONFIG_ENV_OFFSET_REDUND 0x60000
134#define CONFIG_ENV_SIZE (128 * 1024)
Magnus Lilja6eeb6f72009-07-01 01:07:55 +0200135
Magnus Lilja9828d352010-01-17 17:46:11 +0100136/*
137 * NAND driver
138 */
139#define CONFIG_NAND_MXC
140#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
141#define CONFIG_SYS_MAX_NAND_DEVICE 1
142#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
143#define CONFIG_MXC_NAND_HWECC
144#define CONFIG_SYS_NAND_LARGEPAGE
Magnus Lilja6eeb6f72009-07-01 01:07:55 +0200145
Magnus Lilja24f8b412009-07-04 10:31:24 +0200146/* NAND configuration for the NAND_SPL */
147
Bin Meng75574052016-02-05 19:30:11 -0800148/* Start copying real U-Boot from the second page */
Benoît Thébaudeauefb7c002013-04-11 09:35:51 +0000149#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
150#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800
Magnus Lilja24f8b412009-07-04 10:31:24 +0200151/* Load U-Boot to this address */
Benoît Thébaudeauefb7c002013-04-11 09:35:51 +0000152#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
Magnus Lilja24f8b412009-07-04 10:31:24 +0200153#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
154
155#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
156#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
157#define CONFIG_SYS_NAND_PAGE_COUNT 64
158#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
159#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
160
Magnus Lilja24f8b412009-07-04 10:31:24 +0200161/* Configuration of lowlevel_init.S (clocks and SDRAM) */
162#define CCM_CCMR_SETUP 0x074B0BF5
Benoît Thébaudeaua83d2a92012-08-14 08:43:07 +0000163#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
164 PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \
165 PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \
166 PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0))
167#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \
Magnus Lilja24f8b412009-07-04 10:31:24 +0200168 PLL_MFN(12))
169
170#define ESDMISC_MDDR_SETUP 0x00000004
171#define ESDMISC_MDDR_RESET_DL 0x0000000c
172#define ESDCFG0_MDDR_SETUP 0x006ac73a
173
174#define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
175#define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
176 ESDCTL_DSIZ(2) | ESDCTL_BL(1))
177#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
178#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
179#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
180#define ESDCTL_RW ESDCTL_SETTINGS
181
Magnus Lilja6eeb6f72009-07-01 01:07:55 +0200182#endif /* __CONFIG_H */