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wdenkf4675562002-10-02 14:20:15 +00001/*
Wolfgang Denk3edb6202014-10-24 15:31:26 +02002 * (C) Copyright 2000-2014
wdenkf4675562002-10-02 14:20:15 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkf4675562002-10-02 14:20:15 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
21#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */
22
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020023#define CONFIG_SYS_TEXT_BASE 0x40000000
24
wdenkf4675562002-10-02 14:20:15 +000025#ifdef CONFIG_LCD /* with LCD controller ? */
Jeroen Hofstee62844892013-01-22 10:44:09 +000026#define CONFIG_MPC8XX_LCD
Wolfgang Denk82ccfde2008-07-07 01:22:29 +020027#define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */
28#define CONFIG_LCD_INFO 1 /* ... and some board info */
wdenk874ac262003-07-24 23:38:38 +000029#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
wdenkf4675562002-10-02 14:20:15 +000030#endif
31
32#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denkf0d526a2009-07-28 22:13:52 +020033#define CONFIG_SYS_SMC_RXBUFLEN 128
34#define CONFIG_SYS_MAXIDLE 10
wdenkf4675562002-10-02 14:20:15 +000035
wdenkfb229ae2003-08-07 22:18:11 +000036#define CONFIG_BOOTCOUNT_LIMIT
37
wdenkf4675562002-10-02 14:20:15 +000038
39#define CONFIG_BOARD_TYPES 1 /* support board types */
40
Wolfgang Denk1baed662008-03-03 12:16:44 +010041#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
wdenkf4675562002-10-02 14:20:15 +000042
43#undef CONFIG_BOOTARGS
wdenk34b613e2002-12-17 01:51:00 +000044
45#define CONFIG_EXTRA_ENV_SETTINGS \
wdenkfb229ae2003-08-07 22:18:11 +000046 "netdev=eth0\0" \
wdenk34b613e2002-12-17 01:51:00 +000047 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010048 "nfsroot=${serverip}:${rootpath}\0" \
wdenk34b613e2002-12-17 01:51:00 +000049 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010050 "addip=setenv bootargs ${bootargs} " \
51 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
52 ":${hostname}:${netdev}:off panic=1\0" \
wdenk34b613e2002-12-17 01:51:00 +000053 "flash_nfs=run nfsargs addip;" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010054 "bootm ${kernel_addr}\0" \
wdenk34b613e2002-12-17 01:51:00 +000055 "flash_self=run ramargs addip;" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +010056 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
57 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk34b613e2002-12-17 01:51:00 +000058 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denkdae5bfd2008-08-09 23:17:32 +020059 "hostname=TQM823L\0" \
60 "bootfile=TQM823L/uImage\0" \
Wolfgang Denk64ab5182007-09-16 02:39:35 +020061 "fdt_addr=40040000\0" \
62 "kernel_addr=40060000\0" \
63 "ramdisk_addr=40200000\0" \
Wolfgang Denkdae5bfd2008-08-09 23:17:32 +020064 "u-boot=TQM823L/u-image.bin\0" \
65 "load=tftp 200000 ${u-boot}\0" \
66 "update=prot off 40000000 +${filesize};" \
67 "era 40000000 +${filesize};" \
68 "cp.b 200000 40000000 ${filesize};" \
69 "sete filesize;save\0" \
wdenk34b613e2002-12-17 01:51:00 +000070 ""
71#define CONFIG_BOOTCOMMAND "run flash_self"
wdenkf4675562002-10-02 14:20:15 +000072
73#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020074#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkf4675562002-10-02 14:20:15 +000075
76#undef CONFIG_WATCHDOG /* watchdog disabled */
77
wdenk2f99a692004-01-04 22:51:12 +000078#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
wdenkf4675562002-10-02 14:20:15 +000079
Jon Loeliger530ca672007-07-09 21:38:02 -050080/*
81 * BOOTP options
82 */
83#define CONFIG_BOOTP_SUBNETMASK
84#define CONFIG_BOOTP_GATEWAY
85#define CONFIG_BOOTP_HOSTNAME
86#define CONFIG_BOOTP_BOOTPATH
87#define CONFIG_BOOTP_BOOTFILESIZE
88
wdenkf4675562002-10-02 14:20:15 +000089#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
90
Jon Loeligeredccb462007-07-04 22:30:50 -050091/*
92 * Command line configuration.
93 */
Jon Loeligeredccb462007-07-04 22:30:50 -050094#define CONFIG_CMD_DATE
Jon Loeligeredccb462007-07-04 22:30:50 -050095#define CONFIG_CMD_IDE
Wolfgang Denkdae5bfd2008-08-09 23:17:32 +020096#define CONFIG_CMD_JFFS2
Jon Loeligeredccb462007-07-04 22:30:50 -050097
wdenk874ac262003-07-24 23:38:38 +000098#ifdef CONFIG_SPLASH_SCREEN
Jon Loeligeredccb462007-07-04 22:30:50 -050099 #define CONFIG_CMD_BMP
wdenk874ac262003-07-24 23:38:38 +0000100#endif
wdenkf4675562002-10-02 14:20:15 +0000101
Wolfgang Denkdae5bfd2008-08-09 23:17:32 +0200102#define CONFIG_NETCONSOLE
103
wdenkf4675562002-10-02 14:20:15 +0000104/*
105 * Miscellaneous configurable options
106 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200107#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenk34b613e2002-12-17 01:51:00 +0000108
Wolfgang Denk274bac52006-10-28 02:29:14 +0200109#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
wdenk34b613e2002-12-17 01:51:00 +0000110
Jon Loeligeredccb462007-07-04 22:30:50 -0500111#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200112#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000113#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200114#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000115#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200116#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
117#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
118#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000119
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200120#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
121#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkf4675562002-10-02 14:20:15 +0000122
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200123#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkf4675562002-10-02 14:20:15 +0000124
wdenkf4675562002-10-02 14:20:15 +0000125/*
126 * Low Level Configuration Settings
127 * (address mappings, register initial values, etc.)
128 * You should know what you are doing if you make changes here.
129 */
130/*-----------------------------------------------------------------------
131 * Internal Memory Mapped Register
132 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200133#define CONFIG_SYS_IMMR 0xFFF00000
wdenkf4675562002-10-02 14:20:15 +0000134
135/*-----------------------------------------------------------------------
136 * Definitions for initial stack pointer and data area (in DPRAM)
137 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200138#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200139#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk0191e472010-10-26 14:34:52 +0200140#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200141#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkf4675562002-10-02 14:20:15 +0000142
143/*-----------------------------------------------------------------------
144 * Start addresses for the final memory configuration
145 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200146 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkf4675562002-10-02 14:20:15 +0000147 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200148#define CONFIG_SYS_SDRAM_BASE 0x00000000
149#define CONFIG_SYS_FLASH_BASE 0x40000000
150#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
151#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
152#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkf4675562002-10-02 14:20:15 +0000153
154/*
155 * For booting Linux, the board info and command line data
156 * have to be in the first 8 MB of memory, since this is
157 * the maximum mapped by the Linux kernel during initialization.
158 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200159#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkf4675562002-10-02 14:20:15 +0000160
161/*-----------------------------------------------------------------------
162 * FLASH organization
163 */
wdenkf4675562002-10-02 14:20:15 +0000164
Martin Krausec098b0e2007-09-27 11:10:08 +0200165/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200166#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200167#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200168#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
169#define CONFIG_SYS_FLASH_EMPTY_INFO
170#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
171#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
172#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
wdenkf4675562002-10-02 14:20:15 +0000173
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200174#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200175#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
176#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
wdenkf4675562002-10-02 14:20:15 +0000177
178/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200179#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
180#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkf4675562002-10-02 14:20:15 +0000181
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200182#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk4ed40bb2007-09-16 17:10:04 +0200183
Wolfgang Denk8d82cc02008-09-16 18:02:19 +0200184#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
185
wdenkf4675562002-10-02 14:20:15 +0000186/*-----------------------------------------------------------------------
Wolfgang Denkdae5bfd2008-08-09 23:17:32 +0200187 * Dynamic MTD partition support
188 */
Stefan Roeseb1423dd2009-03-19 13:30:36 +0100189#define CONFIG_CMD_MTDPARTS
Stefan Roese5dc958f2009-05-12 14:32:58 +0200190#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
191#define CONFIG_FLASH_CFI_MTD
Wolfgang Denkdae5bfd2008-08-09 23:17:32 +0200192#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
193
194#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
195 "128k(dtb)," \
196 "1664k(kernel)," \
197 "2m(rootfs)," \
Wolfgang Denk1ec16772008-08-12 16:08:38 +0200198 "4m(data)"
Wolfgang Denkdae5bfd2008-08-09 23:17:32 +0200199
200/*-----------------------------------------------------------------------
wdenkf4675562002-10-02 14:20:15 +0000201 * Hardware Information Block
202 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200203#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
204#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
205#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenkf4675562002-10-02 14:20:15 +0000206
207/*-----------------------------------------------------------------------
208 * Cache Configuration
209 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200210#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeligeredccb462007-07-04 22:30:50 -0500211#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200212#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkf4675562002-10-02 14:20:15 +0000213#endif
214
215/*-----------------------------------------------------------------------
216 * SYPCR - System Protection Control 11-9
217 * SYPCR can only be written once after reset!
218 *-----------------------------------------------------------------------
219 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
220 */
221#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200222#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkf4675562002-10-02 14:20:15 +0000223 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
224#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200225#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkf4675562002-10-02 14:20:15 +0000226#endif
227
228/*-----------------------------------------------------------------------
229 * SIUMCR - SIU Module Configuration 11-6
230 *-----------------------------------------------------------------------
231 * PCMCIA config., multi-function pin tri-state
232 */
233#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200234#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf4675562002-10-02 14:20:15 +0000235#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200236#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf4675562002-10-02 14:20:15 +0000237#endif /* CONFIG_CAN_DRIVER */
238
239/*-----------------------------------------------------------------------
240 * TBSCR - Time Base Status and Control 11-26
241 *-----------------------------------------------------------------------
242 * Clear Reference Interrupt Status, Timebase freezing enabled
243 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200244#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkf4675562002-10-02 14:20:15 +0000245
246/*-----------------------------------------------------------------------
247 * RTCSC - Real-Time Clock Status and Control Register 11-27
248 *-----------------------------------------------------------------------
249 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200250#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenkf4675562002-10-02 14:20:15 +0000251
252/*-----------------------------------------------------------------------
253 * PISCR - Periodic Interrupt Status and Control 11-31
254 *-----------------------------------------------------------------------
255 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
256 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200257#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkf4675562002-10-02 14:20:15 +0000258
259/*-----------------------------------------------------------------------
260 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
261 *-----------------------------------------------------------------------
262 * Reset PLL lock status sticky bit, timer expired status bit and timer
263 * interrupt status bit
wdenkf4675562002-10-02 14:20:15 +0000264 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200265#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkf4675562002-10-02 14:20:15 +0000266
267/*-----------------------------------------------------------------------
268 * SCCR - System Clock and reset Control Register 15-27
269 *-----------------------------------------------------------------------
270 * Set clock output, timebase and RTC source and divider,
271 * power management and some other internal clocks
272 */
273#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200274#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkf4675562002-10-02 14:20:15 +0000275 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
276 SCCR_DFALCD00)
wdenkf4675562002-10-02 14:20:15 +0000277
278/*-----------------------------------------------------------------------
279 * PCMCIA stuff
280 *-----------------------------------------------------------------------
281 *
282 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200283#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
284#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
285#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
286#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
287#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
288#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
289#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
290#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkf4675562002-10-02 14:20:15 +0000291
292/*-----------------------------------------------------------------------
293 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
294 *-----------------------------------------------------------------------
295 */
296
Pavel Herrmann2c13c4a2012-10-09 07:01:56 +0000297#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
wdenkf4675562002-10-02 14:20:15 +0000298#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
299
300#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
301#undef CONFIG_IDE_LED /* LED for ide not supported */
302#undef CONFIG_IDE_RESET /* reset for ide not supported */
303
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200304#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
305#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenkf4675562002-10-02 14:20:15 +0000306
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200307#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkf4675562002-10-02 14:20:15 +0000308
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200309#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenkf4675562002-10-02 14:20:15 +0000310
311/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200312#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf4675562002-10-02 14:20:15 +0000313
314/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200315#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf4675562002-10-02 14:20:15 +0000316
317/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200318#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkf4675562002-10-02 14:20:15 +0000319
320/*-----------------------------------------------------------------------
321 *
322 *-----------------------------------------------------------------------
323 *
324 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200325#define CONFIG_SYS_DER 0
wdenkf4675562002-10-02 14:20:15 +0000326
327/*
328 * Init Memory Controller:
329 *
330 * BR0/1 and OR0/1 (FLASH)
331 */
332
333#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
334#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
335
336/* used to re-map FLASH both when starting from SRAM or FLASH:
337 * restrict access enough to keep SRAM working (if any)
338 * but not too much to meddle with FLASH accesses
339 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200340#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
341#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenkf4675562002-10-02 14:20:15 +0000342
343/*
344 * FLASH timing:
345 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200346#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenkf4675562002-10-02 14:20:15 +0000347 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkf4675562002-10-02 14:20:15 +0000348
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200349#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
350#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
351#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000352
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200353#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
354#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
355#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000356
357/*
358 * BR2/3 and OR2/3 (SDRAM)
359 *
360 */
361#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
362#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
363#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
364
365/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200366#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenkf4675562002-10-02 14:20:15 +0000367
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200368#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
369#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000370
371#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200372#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
373#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000374#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200375#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
376#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
377#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
378#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenkf4675562002-10-02 14:20:15 +0000379 BR_PS_8 | BR_MS_UPMB | BR_V )
380#endif /* CONFIG_CAN_DRIVER */
381
382/*
383 * Memory Periodic Timer Prescaler
384 *
385 * The Divider for PTA (refresh timer) configuration is based on an
386 * example SDRAM configuration (64 MBit, one bank). The adjustment to
387 * the number of chip selects (NCS) and the actually needed refresh
388 * rate is done by setting MPTPR.
389 *
390 * PTA is calculated from
391 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
392 *
393 * gclk CPU clock (not bus clock!)
394 * Trefresh Refresh cycle * 4 (four word bursts used)
395 *
396 * 4096 Rows from SDRAM example configuration
397 * 1000 factor s -> ms
398 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
399 * 4 Number of refresh cycles per period
400 * 64 Refresh cycle in ms per number of rows
401 * --------------------------------------------
402 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
403 *
404 * 50 MHz => 50.000.000 / Divider = 98
405 * 66 Mhz => 66.000.000 / Divider = 129
406 * 80 Mhz => 80.000.000 / Divider = 156
407 */
wdenkc78bf132004-04-24 23:23:30 +0000408
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200409#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
410#define CONFIG_SYS_MAMR_PTA 98
wdenkf4675562002-10-02 14:20:15 +0000411
412/*
413 * For 16 MBit, refresh rates could be 31.3 us
414 * (= 64 ms / 2K = 125 / quad bursts).
415 * For a simpler initialization, 15.6 us is used instead.
416 *
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200417 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
418 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenkf4675562002-10-02 14:20:15 +0000419 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200420#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
421#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenkf4675562002-10-02 14:20:15 +0000422
423/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200424#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
425#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenkf4675562002-10-02 14:20:15 +0000426
427/*
428 * MAMR settings for SDRAM
429 */
430
431/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200432#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf4675562002-10-02 14:20:15 +0000433 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
434 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
435/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200436#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf4675562002-10-02 14:20:15 +0000437 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
438 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
439
Heiko Schocherc95fa8b2010-02-09 15:50:27 +0100440#define CONFIG_HWCONFIG 1
441
wdenkf4675562002-10-02 14:20:15 +0000442#endif /* __CONFIG_H */