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git01.mediatek.com / filogic / uboot / a29160c3fd481ee5183ba670f91ba2d8e7f48145 / . / configs / chromebit_mickey_defconfig
blob: e1f96dce12d10ea88e4a62621cc74e09ed81a85a [file] [log] [blame]
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_ROCKCHIP=y
3CONFIG_SYS_MALLOC_F_LEN=0x2000
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]4CONFIG_ROCKCHIP_RK3288=y
Tom Rini9834b902017-03-13 13:48:42 -0400[diff] [blame]5# CONFIG_SPL_MMC_SUPPORT is not set
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]6CONFIG_TARGET_CHROMEBIT_MICKEY=y
7CONFIG_SPL_SPI_FLASH_SUPPORT=y
8CONFIG_SPL_SPI_SUPPORT=y
9CONFIG_SPL_STACK_R_ADDR=0x80000
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]10CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey"
11# CONFIG_DISPLAY_CPUINFO is not set
12CONFIG_SPL_STACK_R=y
13CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]14# CONFIG_CMD_IMLS is not set
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]15CONFIG_CMD_GPT=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]16CONFIG_CMD_MMC=y
17CONFIG_CMD_SF=y
18CONFIG_CMD_SPI=y
19CONFIG_CMD_I2C=y
20CONFIG_CMD_GPIO=y
21# CONFIG_CMD_SETEXPR is not set
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]22CONFIG_CMD_CACHE=y
23CONFIG_CMD_TIME=y
24CONFIG_CMD_PMIC=y
25CONFIG_CMD_REGULATOR=y
Patrick Delaunayf7e07722017-01-27 11:00:37 +0100[diff] [blame]26# CONFIG_SPL_DOS_PARTITION is not set
Patrick Delaunay21d3bce2017-01-27 11:00:38 +0100[diff] [blame]27# CONFIG_SPL_ISO_PARTITION is not set
Patrick Delaunay8a4f2bd2017-01-27 11:00:41 +0100[diff] [blame]28# CONFIG_SPL_EFI_PARTITION is not set
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]29CONFIG_SPL_PARTITION_UUIDS=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]30CONFIG_SPL_OF_CONTROL=y
31CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Masahiro Yamada74f09b82016-12-07 22:10:25 +0900[diff] [blame]32CONFIG_SPL_OF_PLATDATA=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]33CONFIG_REGMAP=y
34CONFIG_SPL_REGMAP=y
35CONFIG_SYSCON=y
36CONFIG_SPL_SYSCON=y
37# CONFIG_SPL_SIMPLE_BUS is not set
38CONFIG_CLK=y
39CONFIG_SPL_CLK=y
40CONFIG_ROCKCHIP_GPIO=y
41CONFIG_I2C_CROS_EC_TUNNEL=y
42CONFIG_SYS_I2C_ROCKCHIP=y
43CONFIG_I2C_MUX=y
Masahiro Yamada74f09b82016-12-07 22:10:25 +0900[diff] [blame]44CONFIG_DM_KEYBOARD=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]45CONFIG_CROS_EC_KEYB=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]46CONFIG_CROS_EC=y
47CONFIG_CROS_EC_SPI=y
48CONFIG_PWRSEQ=y
Masahiro Yamada7942e912017-01-10 13:32:04 +0900[diff] [blame]49CONFIG_MMC_DW=y
Masahiro Yamadadc607f82017-01-10 13:32:03 +0900[diff] [blame]50CONFIG_MMC_DW_ROCKCHIP=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]51CONFIG_PINCTRL=y
52CONFIG_SPL_PINCTRL=y
53# CONFIG_SPL_PINCTRL_FULL is not set
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200[diff] [blame]54CONFIG_PINCTRL_ROCKCHIP_RK3288=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]55CONFIG_DM_PMIC=y
56# CONFIG_SPL_PMIC_CHILDREN is not set
57CONFIG_PMIC_RK808=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]58CONFIG_SPL_DM_REGULATOR=y
59CONFIG_DM_REGULATOR_FIXED=y
60CONFIG_REGULATOR_RK808=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]61CONFIG_PWM_ROCKCHIP=y
62CONFIG_RAM=y
63CONFIG_SPL_RAM=y
64CONFIG_DEBUG_UART=y
65CONFIG_DEBUG_UART_BASE=0xff690000
66CONFIG_DEBUG_UART_CLOCK=24000000
67CONFIG_DEBUG_UART_SHIFT=2
68CONFIG_SYS_NS16550=y
69CONFIG_ROCKCHIP_SERIAL=y
70CONFIG_ROCKCHIP_SPI=y
71CONFIG_SYSRESET=y
72CONFIG_DM_VIDEO=y
73CONFIG_DISPLAY=y
74CONFIG_VIDEO_ROCKCHIP=y
75CONFIG_USE_TINY_PRINTF=y
76CONFIG_CMD_DHRYSTONE=y
77CONFIG_ERRNO_STR=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]78# CONFIG_SPL_OF_LIBFDT is not set