Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 1 | /* |
Stefan Roese | c769864 | 2007-06-01 15:19:29 +0200 | [diff] [blame] | 2 | * (C) Copyright 2005-2007 |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 4 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <asm/processor.h> |
Stefan Roese | de21eab | 2010-09-16 14:30:37 +0200 | [diff] [blame] | 10 | #include <asm/ppc4xx-gpio.h> |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 11 | #include <spd_sdram.h> |
Stefan Roese | 247e9d7 | 2010-09-09 19:18:00 +0200 | [diff] [blame] | 12 | #include <asm/ppc440.h> |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 13 | #include "bamboo.h" |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 14 | |
Simon Glass | 39f90ba | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 15 | DECLARE_GLOBAL_DATA_PTR; |
| 16 | |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 17 | void ext_bus_cntlr_init(void); |
| 18 | void configure_ppc440ep_pins(void); |
Stefan Roese | 797d857 | 2005-08-11 17:56:56 +0200 | [diff] [blame] | 19 | int is_nand_selected(void); |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 20 | |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 21 | /************************************************************************* |
| 22 | * |
| 23 | * Bamboo has one bank onboard sdram (plus DIMM) |
| 24 | * |
| 25 | * Fixed memory is composed of : |
| 26 | * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266, |
| 27 | * 13 row add bits, 10 column add bits (but 12 row used only). |
| 28 | * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266, |
| 29 | * 12 row add bits, 10 column add bits. |
| 30 | * Prepare a subset (only the used ones) of SPD data |
| 31 | * |
| 32 | * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of |
| 33 | * the corresponding bank is divided by 2 due to number of Row addresses |
| 34 | * 12 in the ECC module |
| 35 | * |
| 36 | * Assumes: 64 MB, ECC, non-registered |
| 37 | * PLB @ 133 MHz |
| 38 | * |
| 39 | ************************************************************************/ |
| 40 | const unsigned char cfg_simulate_spd_eeprom[128] = { |
| 41 | 0x80, /* number of SPD bytes used: 128 */ |
| 42 | 0x08, /* total number bytes in SPD device = 256 */ |
| 43 | 0x07, /* DDR ram */ |
| 44 | #ifdef CONFIG_DDR_ECC |
| 45 | 0x0C, /* num Row Addr: 12 */ |
| 46 | #else |
| 47 | 0x0D, /* num Row Addr: 13 */ |
| 48 | #endif |
| 49 | 0x09, /* numColAddr: 9 */ |
| 50 | 0x01, /* numBanks: 1 */ |
| 51 | 0x20, /* Module data width: 32 bits */ |
| 52 | 0x00, /* Module data width continued: +0 */ |
| 53 | 0x04, /* 2.5 Volt */ |
| 54 | 0x75, /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */ |
Eugene O'Brien | c8fd200 | 2007-10-23 08:29:10 +0200 | [diff] [blame] | 55 | 0x00, /* SDRAM Access from clock */ |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 56 | #ifdef CONFIG_DDR_ECC |
| 57 | 0x02, /* ECC ON : 02 OFF : 00 */ |
| 58 | #else |
| 59 | 0x00, /* ECC ON : 02 OFF : 00 */ |
| 60 | #endif |
Eugene O'Brien | c8fd200 | 2007-10-23 08:29:10 +0200 | [diff] [blame] | 61 | 0x82, /* refresh Rate Type: Normal (7.8us) + Self refresh */ |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 62 | 0, |
| 63 | 0, |
| 64 | 0x01, /* wcsbc = 1 */ |
| 65 | 0, |
| 66 | 0, |
| 67 | 0x0C, /* casBit (2,2.5) */ |
| 68 | 0, |
| 69 | 0, |
| 70 | 0x00, /* not registered: 0 registered : 0x02*/ |
| 71 | 0, |
| 72 | 0xA0, /* SDRAM Cycle Time (cas latency 2) = 10 ns */ |
| 73 | 0, |
| 74 | 0x00, /* SDRAM Cycle Time (cas latency 1.5) = N.A */ |
| 75 | 0, |
| 76 | 0x50, /* tRpNs = 20 ns */ |
| 77 | 0, |
| 78 | 0x50, /* tRcdNs = 20 ns */ |
| 79 | 45, /* tRasNs */ |
| 80 | #ifdef CONFIG_DDR_ECC |
| 81 | 0x08, /* bankSizeID: 32MB */ |
| 82 | #else |
| 83 | 0x10, /* bankSizeID: 64MB */ |
| 84 | #endif |
| 85 | 0, |
| 86 | 0, |
| 87 | 0, |
| 88 | 0, |
| 89 | 0, |
| 90 | 0, |
| 91 | 0, |
| 92 | 0, |
| 93 | 0, |
| 94 | 0, |
| 95 | 0, |
| 96 | 0, |
| 97 | 0, |
| 98 | 0, |
| 99 | 0, |
| 100 | 0, |
| 101 | 0, |
| 102 | 0, |
| 103 | 0, |
| 104 | 0, |
| 105 | 0, |
| 106 | 0, |
| 107 | 0, |
| 108 | 0, |
| 109 | 0, |
| 110 | 0, |
| 111 | 0, |
| 112 | 0, |
| 113 | 0, |
| 114 | 0, |
| 115 | 0, |
| 116 | 0, |
| 117 | 0, |
| 118 | 0, |
| 119 | 0, |
| 120 | 0, |
| 121 | 0, |
| 122 | 0, |
| 123 | 0, |
| 124 | 0, |
| 125 | 0, |
| 126 | 0, |
| 127 | 0, |
| 128 | 0, |
| 129 | 0, |
| 130 | 0, |
| 131 | 0, |
| 132 | 0, |
| 133 | 0, |
| 134 | 0, |
| 135 | 0, |
| 136 | 0, |
| 137 | 0, |
| 138 | 0, |
| 139 | 0, |
| 140 | 0, |
| 141 | 0, |
| 142 | 0, |
| 143 | 0, |
| 144 | 0, |
| 145 | 0, |
| 146 | 0, |
| 147 | 0, |
| 148 | 0, |
| 149 | 0, |
| 150 | 0, |
| 151 | 0, |
| 152 | 0, |
| 153 | 0, |
| 154 | 0, |
| 155 | 0, |
| 156 | 0, |
| 157 | 0, |
| 158 | 0, |
| 159 | 0, |
| 160 | 0, |
| 161 | 0, |
| 162 | 0, |
| 163 | 0, |
| 164 | 0, |
| 165 | 0, |
| 166 | 0, |
| 167 | 0, |
| 168 | 0, |
| 169 | 0, |
| 170 | 0, |
| 171 | 0, |
| 172 | 0, |
| 173 | 0, |
| 174 | 0, |
| 175 | 0, |
| 176 | 0, |
| 177 | 0, |
| 178 | 0, |
| 179 | 0, |
| 180 | 0 |
| 181 | }; |
Stefan Roese | c45d1e3 | 2005-11-15 16:04:58 +0100 | [diff] [blame] | 182 | |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 183 | #if 0 |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 184 | { /* GPIO Alternate1 Alternate2 Alternate3 */ |
| 185 | { |
| 186 | /* GPIO Core 0 */ |
| 187 | { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */ |
| 188 | { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */ |
| 189 | { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */ |
| 190 | { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */ |
| 191 | { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */ |
| 192 | { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */ |
| 193 | { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */ |
| 194 | { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */ |
| 195 | { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */ |
| 196 | { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */ |
| 197 | { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */ |
| 198 | { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */ |
| 199 | { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */ |
| 200 | { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */ |
| 201 | { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */ |
| 202 | { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */ |
| 203 | { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */ |
| 204 | { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */ |
| 205 | { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */ |
| 206 | { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */ |
| 207 | { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */ |
| 208 | { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */ |
| 209 | { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */ |
| 210 | { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */ |
| 211 | { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */ |
| 212 | { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */ |
| 213 | { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */ |
| 214 | { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */ |
| 215 | { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */ |
| 216 | { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ |
| 217 | { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */ |
| 218 | { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */ |
| 219 | }, |
| 220 | { |
| 221 | /* GPIO Core 1 */ |
| 222 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */ |
| 223 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */ |
| 224 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */ |
| 225 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */ |
| 226 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */ |
| 227 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */ |
| 228 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */ |
| 229 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */ |
| 230 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */ |
| 231 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */ |
| 232 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */ |
| 233 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */ |
| 234 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */ |
| 235 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */ |
| 236 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */ |
| 237 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */ |
| 238 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */ |
| 239 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */ |
| 240 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */ |
| 241 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */ |
| 242 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */ |
| 243 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */ |
| 244 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */ |
| 245 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */ |
| 246 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */ |
| 247 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */ |
| 248 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */ |
| 249 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */ |
| 250 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */ |
| 251 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */ |
| 252 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */ |
| 253 | { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */ |
| 254 | } |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 255 | }; |
| 256 | #endif |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 257 | |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 258 | /*----------------------------------------------------------------------------+ |
| 259 | | EBC Devices Characteristics |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 260 | | Peripheral Bank Access Parameters - EBC0_BnAP |
| 261 | | Peripheral Bank Configuration Register - EBC0_BnCR |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 262 | +----------------------------------------------------------------------------*/ |
| 263 | /* Small Flash */ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 264 | #define EBC0_BNAP_SMALL_FLASH \ |
| 265 | EBC0_BNAP_BME_DISABLED | \ |
| 266 | EBC0_BNAP_TWT_ENCODE(6) | \ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 267 | EBC0_BNAP_CSN_ENCODE(0) | \ |
| 268 | EBC0_BNAP_OEN_ENCODE(1) | \ |
| 269 | EBC0_BNAP_WBN_ENCODE(1) | \ |
| 270 | EBC0_BNAP_WBF_ENCODE(3) | \ |
| 271 | EBC0_BNAP_TH_ENCODE(1) | \ |
| 272 | EBC0_BNAP_RE_ENABLED | \ |
| 273 | EBC0_BNAP_SOR_DELAYED | \ |
| 274 | EBC0_BNAP_BEM_WRITEONLY | \ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 275 | EBC0_BNAP_PEN_DISABLED |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 276 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 277 | #define EBC0_BNCR_SMALL_FLASH_CS0 \ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 278 | EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \ |
| 279 | EBC0_BNCR_BS_1MB | \ |
| 280 | EBC0_BNCR_BU_RW | \ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 281 | EBC0_BNCR_BW_8BIT |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 282 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 283 | #define EBC0_BNCR_SMALL_FLASH_CS4 \ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 284 | EBC0_BNCR_BAS_ENCODE(0x87F00000) | \ |
| 285 | EBC0_BNCR_BS_1MB | \ |
| 286 | EBC0_BNCR_BU_RW | \ |
Stefan Roese | 797d857 | 2005-08-11 17:56:56 +0200 | [diff] [blame] | 287 | EBC0_BNCR_BW_8BIT |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 288 | |
| 289 | /* Large Flash or SRAM */ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 290 | #define EBC0_BNAP_LARGE_FLASH_OR_SRAM \ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 291 | EBC0_BNAP_BME_DISABLED | \ |
| 292 | EBC0_BNAP_TWT_ENCODE(8) | \ |
| 293 | EBC0_BNAP_CSN_ENCODE(0) | \ |
| 294 | EBC0_BNAP_OEN_ENCODE(1) | \ |
| 295 | EBC0_BNAP_WBN_ENCODE(1) | \ |
| 296 | EBC0_BNAP_WBF_ENCODE(1) | \ |
| 297 | EBC0_BNAP_TH_ENCODE(2) | \ |
| 298 | EBC0_BNAP_SOR_DELAYED | \ |
| 299 | EBC0_BNAP_BEM_RW | \ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 300 | EBC0_BNAP_PEN_DISABLED |
| 301 | |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 302 | #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \ |
| 303 | EBC0_BNCR_BAS_ENCODE(0xFF800000) | \ |
| 304 | EBC0_BNCR_BS_8MB | \ |
| 305 | EBC0_BNCR_BU_RW | \ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 306 | EBC0_BNCR_BW_16BIT |
| 307 | |
| 308 | |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 309 | #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \ |
| 310 | EBC0_BNCR_BAS_ENCODE(0x87800000) | \ |
| 311 | EBC0_BNCR_BS_8MB | \ |
| 312 | EBC0_BNCR_BU_RW | \ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 313 | EBC0_BNCR_BW_16BIT |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 314 | |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 315 | /* NVRAM - FPGA */ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 316 | #define EBC0_BNAP_NVRAM_FPGA \ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 317 | EBC0_BNAP_BME_DISABLED | \ |
| 318 | EBC0_BNAP_TWT_ENCODE(9) | \ |
| 319 | EBC0_BNAP_CSN_ENCODE(0) | \ |
| 320 | EBC0_BNAP_OEN_ENCODE(1) | \ |
| 321 | EBC0_BNAP_WBN_ENCODE(1) | \ |
| 322 | EBC0_BNAP_WBF_ENCODE(0) | \ |
| 323 | EBC0_BNAP_TH_ENCODE(2) | \ |
| 324 | EBC0_BNAP_RE_ENABLED | \ |
| 325 | EBC0_BNAP_SOR_DELAYED | \ |
| 326 | EBC0_BNAP_BEM_WRITEONLY | \ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 327 | EBC0_BNAP_PEN_DISABLED |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 328 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 329 | #define EBC0_BNCR_NVRAM_FPGA_CS5 \ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 330 | EBC0_BNCR_BAS_ENCODE(0x80000000) | \ |
| 331 | EBC0_BNCR_BS_1MB | \ |
| 332 | EBC0_BNCR_BU_RW | \ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 333 | EBC0_BNCR_BW_8BIT |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 334 | |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 335 | /* Nand Flash */ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 336 | #define EBC0_BNAP_NAND_FLASH \ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 337 | EBC0_BNAP_BME_DISABLED | \ |
| 338 | EBC0_BNAP_TWT_ENCODE(3) | \ |
| 339 | EBC0_BNAP_CSN_ENCODE(0) | \ |
| 340 | EBC0_BNAP_OEN_ENCODE(0) | \ |
| 341 | EBC0_BNAP_WBN_ENCODE(0) | \ |
| 342 | EBC0_BNAP_WBF_ENCODE(0) | \ |
| 343 | EBC0_BNAP_TH_ENCODE(1) | \ |
| 344 | EBC0_BNAP_RE_ENABLED | \ |
| 345 | EBC0_BNAP_SOR_NOT_DELAYED | \ |
| 346 | EBC0_BNAP_BEM_RW | \ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 347 | EBC0_BNAP_PEN_DISABLED |
| 348 | |
| 349 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 350 | #define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000 |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 351 | |
| 352 | /* NAND0 */ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 353 | #define EBC0_BNCR_NAND_FLASH_CS1 \ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 354 | EBC0_BNCR_BAS_ENCODE(0x90000000) | \ |
| 355 | EBC0_BNCR_BS_1MB | \ |
| 356 | EBC0_BNCR_BU_RW | \ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 357 | EBC0_BNCR_BW_32BIT |
| 358 | /* NAND1 - Bank2 */ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 359 | #define EBC0_BNCR_NAND_FLASH_CS2 \ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 360 | EBC0_BNCR_BAS_ENCODE(0x94000000) | \ |
| 361 | EBC0_BNCR_BS_1MB | \ |
| 362 | EBC0_BNCR_BU_RW | \ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 363 | EBC0_BNCR_BW_32BIT |
| 364 | |
| 365 | /* NAND1 - Bank3 */ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 366 | #define EBC0_BNCR_NAND_FLASH_CS3 \ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 367 | EBC0_BNCR_BAS_ENCODE(0x94000000) | \ |
| 368 | EBC0_BNCR_BS_1MB | \ |
| 369 | EBC0_BNCR_BU_RW | \ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 370 | EBC0_BNCR_BW_32BIT |
| 371 | |
| 372 | int board_early_init_f(void) |
| 373 | { |
| 374 | ext_bus_cntlr_init(); |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 375 | |
| 376 | /*-------------------------------------------------------------------- |
| 377 | * Setup the interrupt controller polarities, triggers, etc. |
| 378 | *-------------------------------------------------------------------*/ |
Stefan Roese | 707fd36 | 2009-09-24 09:55:50 +0200 | [diff] [blame] | 379 | mtdcr(UIC0SR, 0xffffffff); /* clear all */ |
| 380 | mtdcr(UIC0ER, 0x00000000); /* disable all */ |
| 381 | mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */ |
| 382 | mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */ |
| 383 | mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */ |
| 384 | mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */ |
| 385 | mtdcr(UIC0SR, 0xffffffff); /* clear all */ |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 386 | |
Stefan Roese | 707fd36 | 2009-09-24 09:55:50 +0200 | [diff] [blame] | 387 | mtdcr(UIC1SR, 0xffffffff); /* clear all */ |
| 388 | mtdcr(UIC1ER, 0x00000000); /* disable all */ |
| 389 | mtdcr(UIC1CR, 0x00000000); /* all non-critical */ |
| 390 | mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */ |
| 391 | mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */ |
| 392 | mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ |
| 393 | mtdcr(UIC1SR, 0xffffffff); /* clear all */ |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 394 | |
| 395 | /*-------------------------------------------------------------------- |
| 396 | * Setup the GPIO pins |
| 397 | *-------------------------------------------------------------------*/ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 398 | out32(GPIO0_OSRL, 0x00000400); |
| 399 | out32(GPIO0_OSRH, 0x00000000); |
| 400 | out32(GPIO0_TSRL, 0x00000400); |
| 401 | out32(GPIO0_TSRH, 0x00000000); |
| 402 | out32(GPIO0_ISR1L, 0x00000000); |
| 403 | out32(GPIO0_ISR1H, 0x00000000); |
| 404 | out32(GPIO0_ISR2L, 0x00000000); |
| 405 | out32(GPIO0_ISR2H, 0x00000000); |
| 406 | out32(GPIO0_ISR3L, 0x00000000); |
| 407 | out32(GPIO0_ISR3H, 0x00000000); |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 408 | |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 409 | out32(GPIO1_OSRL, 0x0C380000); |
| 410 | out32(GPIO1_OSRH, 0x00000000); |
| 411 | out32(GPIO1_TSRL, 0x0C380000); |
| 412 | out32(GPIO1_TSRH, 0x00000000); |
| 413 | out32(GPIO1_ISR1L, 0x0FC30000); |
| 414 | out32(GPIO1_ISR1H, 0x00000000); |
| 415 | out32(GPIO1_ISR2L, 0x0C010000); |
| 416 | out32(GPIO1_ISR2H, 0x00000000); |
| 417 | out32(GPIO1_ISR3L, 0x01400000); |
| 418 | out32(GPIO1_ISR3H, 0x00000000); |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 419 | |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 420 | configure_ppc440ep_pins(); |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 421 | |
| 422 | return 0; |
| 423 | } |
Stefan Roese | 797d857 | 2005-08-11 17:56:56 +0200 | [diff] [blame] | 424 | |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 425 | int checkboard(void) |
| 426 | { |
Wolfgang Denk | 5c1cfee | 2011-05-04 10:32:28 +0000 | [diff] [blame] | 427 | char buf[64]; |
| 428 | int i = getenv_f("serial#", buf, sizeof(buf)); |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 429 | |
| 430 | printf("Board: Bamboo - AMCC PPC440EP Evaluation Board"); |
Wolfgang Denk | 5c1cfee | 2011-05-04 10:32:28 +0000 | [diff] [blame] | 431 | if (i > 0) { |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 432 | puts(", serial# "); |
Wolfgang Denk | 5c1cfee | 2011-05-04 10:32:28 +0000 | [diff] [blame] | 433 | puts(buf); |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 434 | } |
| 435 | putc('\n'); |
| 436 | |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 437 | return (0); |
| 438 | } |
| 439 | |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 440 | |
Simon Glass | d35f338 | 2017-04-06 12:47:05 -0600 | [diff] [blame] | 441 | int dram_init(void) |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 442 | { |
Simon Glass | 39f90ba | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 443 | gd->ram_size = spd_sdram(); |
| 444 | |
| 445 | return 0; |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 446 | } |
| 447 | |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 448 | /*----------------------------------------------------------------------------+ |
| 449 | | is_powerpc440ep_pass1. |
| 450 | +----------------------------------------------------------------------------*/ |
| 451 | int is_powerpc440ep_pass1(void) |
| 452 | { |
| 453 | unsigned long pvr; |
| 454 | |
| 455 | pvr = get_pvr(); |
| 456 | |
| 457 | if (pvr == PVR_POWERPC_440EP_PASS1) |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 458 | return true; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 459 | else if (pvr == PVR_POWERPC_440EP_PASS2) |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 460 | return false; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 461 | else { |
| 462 | printf("brdutil error 3\n"); |
| 463 | for (;;) |
| 464 | ; |
| 465 | } |
| 466 | |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 467 | return false; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 468 | } |
| 469 | |
| 470 | /*----------------------------------------------------------------------------+ |
| 471 | | is_nand_selected. |
| 472 | +----------------------------------------------------------------------------*/ |
| 473 | int is_nand_selected(void) |
| 474 | { |
Stefan Roese | 797d857 | 2005-08-11 17:56:56 +0200 | [diff] [blame] | 475 | #ifdef CONFIG_BAMBOO_NAND |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 476 | return true; |
Stefan Roese | 797d857 | 2005-08-11 17:56:56 +0200 | [diff] [blame] | 477 | #else |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 478 | return false; |
Stefan Roese | 797d857 | 2005-08-11 17:56:56 +0200 | [diff] [blame] | 479 | #endif |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 480 | } |
| 481 | |
| 482 | /*----------------------------------------------------------------------------+ |
| 483 | | config_on_ebc_cs4_is_small_flash => from EPLD |
| 484 | +----------------------------------------------------------------------------*/ |
| 485 | unsigned char config_on_ebc_cs4_is_small_flash(void) |
| 486 | { |
| 487 | /* Not implemented yet => returns constant value */ |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 488 | return true; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 489 | } |
| 490 | |
| 491 | /*----------------------------------------------------------------------------+ |
| 492 | | Ext_bus_cntlr_init. |
| 493 | | Initialize the external bus controller |
| 494 | +----------------------------------------------------------------------------*/ |
| 495 | void ext_bus_cntlr_init(void) |
| 496 | { |
| 497 | unsigned long sdr0_pstrp0, sdr0_sdstp1; |
| 498 | unsigned long bootstrap_settings, boot_selection, ebc_boot_size; |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 499 | int computed_boot_device = BOOT_DEVICE_UNKNOWN; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 500 | unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0; |
| 501 | unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0; |
| 502 | unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0; |
| 503 | unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0; |
| 504 | unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0; |
| 505 | |
| 506 | |
| 507 | /*-------------------------------------------------------------------------+ |
| 508 | | |
| 509 | | PART 1 : Initialize EBC Bank 5 |
| 510 | | ============================== |
| 511 | | Bank5 is always associated to the NVRAM/EPLD. |
| 512 | | It has to be initialized prior to other banks settings computation since |
| 513 | | some board registers values may be needed |
| 514 | | |
| 515 | +-------------------------------------------------------------------------*/ |
| 516 | /* NVRAM - FPGA */ |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 517 | mtebc(PB5AP, EBC0_BNAP_NVRAM_FPGA); |
| 518 | mtebc(PB5CR, EBC0_BNCR_NVRAM_FPGA_CS5); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 519 | |
| 520 | /*-------------------------------------------------------------------------+ |
| 521 | | |
| 522 | | PART 2 : Determine which boot device was selected |
| 523 | | ========================================= |
| 524 | | |
| 525 | | Read Pin Strap Register in PPC440EP |
| 526 | | In case of boot from IIC, read Serial Device Strap Register1 |
| 527 | | |
| 528 | | Result can either be : |
| 529 | | - Boot from EBC 8bits => SMALL FLASH |
| 530 | | - Boot from EBC 16bits => Large Flash or SRAM |
| 531 | | - Boot from NAND Flash |
| 532 | | - Boot from PCI |
| 533 | | |
| 534 | +-------------------------------------------------------------------------*/ |
| 535 | /* Read Pin Strap Register in PPC440EP */ |
Stefan Roese | 95ca5fa | 2010-09-11 09:31:43 +0200 | [diff] [blame] | 536 | mfsdr(SDR0_PINSTP, sdr0_pstrp0); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 537 | bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK; |
| 538 | |
| 539 | /*-------------------------------------------------------------------------+ |
| 540 | | PPC440EP Pass1 |
| 541 | +-------------------------------------------------------------------------*/ |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 542 | if (is_powerpc440ep_pass1() == true) { |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 543 | switch(bootstrap_settings) { |
| 544 | case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0: |
| 545 | /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */ |
| 546 | /* Boot from Small Flash */ |
| 547 | computed_boot_device = BOOT_FROM_SMALL_FLASH; |
| 548 | break; |
| 549 | case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1: |
| 550 | /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */ |
| 551 | /* Boot from PCI */ |
| 552 | computed_boot_device = BOOT_FROM_PCI; |
| 553 | break; |
| 554 | |
| 555 | case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2: |
| 556 | /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */ |
| 557 | /* Boot from Nand Flash */ |
| 558 | computed_boot_device = BOOT_FROM_NAND_FLASH0; |
| 559 | break; |
| 560 | |
| 561 | case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3: |
| 562 | /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */ |
| 563 | /* Boot from Small Flash */ |
| 564 | computed_boot_device = BOOT_FROM_SMALL_FLASH; |
| 565 | break; |
| 566 | |
| 567 | case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN: |
| 568 | case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN: |
| 569 | /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */ |
| 570 | /* Read Serial Device Strap Register1 in PPC440EP */ |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 571 | mfsdr(SDR0_SDSTP1, sdr0_sdstp1); |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 572 | boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK; |
| 573 | ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 574 | |
| 575 | switch(boot_selection) { |
| 576 | case SDR0_SDSTP1_BOOT_SEL_EBC: |
| 577 | switch(ebc_boot_size) { |
| 578 | case SDR0_SDSTP1_EBC_ROM_BS_16BIT: |
| 579 | computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM; |
| 580 | break; |
| 581 | case SDR0_SDSTP1_EBC_ROM_BS_8BIT: |
| 582 | computed_boot_device = BOOT_FROM_SMALL_FLASH; |
| 583 | break; |
| 584 | } |
| 585 | break; |
| 586 | |
| 587 | case SDR0_SDSTP1_BOOT_SEL_PCI: |
| 588 | computed_boot_device = BOOT_FROM_PCI; |
| 589 | break; |
| 590 | |
| 591 | case SDR0_SDSTP1_BOOT_SEL_NDFC: |
| 592 | computed_boot_device = BOOT_FROM_NAND_FLASH0; |
| 593 | break; |
| 594 | } |
| 595 | break; |
| 596 | } |
| 597 | } |
| 598 | |
| 599 | /*-------------------------------------------------------------------------+ |
| 600 | | PPC440EP Pass2 |
| 601 | +-------------------------------------------------------------------------*/ |
| 602 | else { |
| 603 | switch(bootstrap_settings) { |
| 604 | case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0: |
| 605 | /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */ |
| 606 | /* Boot from Small Flash */ |
| 607 | computed_boot_device = BOOT_FROM_SMALL_FLASH; |
| 608 | break; |
| 609 | case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1: |
| 610 | /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */ |
| 611 | /* Boot from PCI */ |
| 612 | computed_boot_device = BOOT_FROM_PCI; |
| 613 | break; |
| 614 | |
| 615 | case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2: |
| 616 | /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */ |
| 617 | /* Boot from Nand Flash */ |
| 618 | computed_boot_device = BOOT_FROM_NAND_FLASH0; |
| 619 | break; |
| 620 | |
| 621 | case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3: |
| 622 | /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */ |
| 623 | /* Boot from Large Flash or SRAM */ |
| 624 | computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM; |
| 625 | break; |
| 626 | |
| 627 | case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4: |
| 628 | /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */ |
| 629 | /* Boot from Large Flash or SRAM */ |
| 630 | computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM; |
| 631 | break; |
| 632 | |
| 633 | case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6: |
| 634 | /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */ |
| 635 | /* Boot from PCI */ |
| 636 | computed_boot_device = BOOT_FROM_PCI; |
| 637 | break; |
| 638 | |
| 639 | case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN: |
| 640 | case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN: |
| 641 | /* Default Strap Settings 5-7 */ |
| 642 | /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */ |
| 643 | /* Read Serial Device Strap Register1 in PPC440EP */ |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 644 | mfsdr(SDR0_SDSTP1, sdr0_sdstp1); |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 645 | boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK; |
| 646 | ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 647 | |
| 648 | switch(boot_selection) { |
| 649 | case SDR0_SDSTP1_BOOT_SEL_EBC: |
| 650 | switch(ebc_boot_size) { |
| 651 | case SDR0_SDSTP1_EBC_ROM_BS_16BIT: |
| 652 | computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM; |
| 653 | break; |
| 654 | case SDR0_SDSTP1_EBC_ROM_BS_8BIT: |
| 655 | computed_boot_device = BOOT_FROM_SMALL_FLASH; |
| 656 | break; |
| 657 | } |
| 658 | break; |
| 659 | |
| 660 | case SDR0_SDSTP1_BOOT_SEL_PCI: |
| 661 | computed_boot_device = BOOT_FROM_PCI; |
| 662 | break; |
| 663 | |
| 664 | case SDR0_SDSTP1_BOOT_SEL_NDFC: |
| 665 | computed_boot_device = BOOT_FROM_NAND_FLASH0; |
| 666 | break; |
| 667 | } |
| 668 | break; |
| 669 | } |
| 670 | } |
| 671 | |
| 672 | /*-------------------------------------------------------------------------+ |
| 673 | | |
| 674 | | PART 3 : Compute EBC settings depending on selected boot device |
| 675 | | ====== ====================================================== |
| 676 | | |
| 677 | | Resulting EBC init will be among following configurations : |
| 678 | | |
| 679 | | - Boot from EBC 8bits => boot from SMALL FLASH selected |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 680 | | EBC-CS0 = Small Flash |
| 681 | | EBC-CS1,2,3 = NAND Flash or |
| 682 | | Exp.Slot depending on Soft Config |
| 683 | | EBC-CS4 = SRAM/Large Flash or |
| 684 | | Large Flash/SRAM depending on jumpers |
| 685 | | EBC-CS5 = NVRAM / EPLD |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 686 | | |
| 687 | | - Boot from EBC 16bits => boot from Large Flash or SRAM selected |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 688 | | EBC-CS0 = SRAM/Large Flash or |
| 689 | | Large Flash/SRAM depending on jumpers |
| 690 | | EBC-CS1,2,3 = NAND Flash or |
| 691 | | Exp.Slot depending on Software Configuration |
| 692 | | EBC-CS4 = Small Flash |
| 693 | | EBC-CS5 = NVRAM / EPLD |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 694 | | |
| 695 | | - Boot from NAND Flash |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 696 | | EBC-CS0 = NAND Flash0 |
| 697 | | EBC-CS1,2,3 = NAND Flash1 |
| 698 | | EBC-CS4 = SRAM/Large Flash or |
| 699 | | Large Flash/SRAM depending on jumpers |
| 700 | | EBC-CS5 = NVRAM / EPLD |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 701 | | |
| 702 | | - Boot from PCI |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 703 | | EBC-CS0 = ... |
| 704 | | EBC-CS1,2,3 = NAND Flash or |
| 705 | | Exp.Slot depending on Software Configuration |
| 706 | | EBC-CS4 = SRAM/Large Flash or |
| 707 | | Large Flash/SRAM or |
| 708 | | Small Flash depending on jumpers |
| 709 | | EBC-CS5 = NVRAM / EPLD |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 710 | | |
| 711 | +-------------------------------------------------------------------------*/ |
| 712 | |
| 713 | switch(computed_boot_device) { |
| 714 | /*------------------------------------------------------------------------- */ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 715 | case BOOT_FROM_SMALL_FLASH: |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 716 | /*------------------------------------------------------------------------- */ |
| 717 | ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH; |
| 718 | ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0; |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 719 | if ((is_nand_selected()) == true) { |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 720 | /* NAND Flash */ |
| 721 | ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH; |
| 722 | ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1; |
Stefan Roese | 797d857 | 2005-08-11 17:56:56 +0200 | [diff] [blame] | 723 | ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH; |
| 724 | ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 725 | ebc0_cs3_bnap_value = 0; |
| 726 | ebc0_cs3_bncr_value = 0; |
| 727 | } else { |
| 728 | /* Expansion Slot */ |
| 729 | ebc0_cs1_bnap_value = 0; |
| 730 | ebc0_cs1_bncr_value = 0; |
| 731 | ebc0_cs2_bnap_value = 0; |
| 732 | ebc0_cs2_bncr_value = 0; |
| 733 | ebc0_cs3_bnap_value = 0; |
| 734 | ebc0_cs3_bncr_value = 0; |
| 735 | } |
| 736 | ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM; |
| 737 | ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4; |
| 738 | |
| 739 | break; |
| 740 | |
| 741 | /*------------------------------------------------------------------------- */ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 742 | case BOOT_FROM_LARGE_FLASH_OR_SRAM: |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 743 | /*------------------------------------------------------------------------- */ |
| 744 | ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM; |
| 745 | ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0; |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 746 | if ((is_nand_selected()) == true) { |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 747 | /* NAND Flash */ |
| 748 | ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH; |
| 749 | ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1; |
| 750 | ebc0_cs2_bnap_value = 0; |
| 751 | ebc0_cs2_bncr_value = 0; |
| 752 | ebc0_cs3_bnap_value = 0; |
| 753 | ebc0_cs3_bncr_value = 0; |
| 754 | } else { |
| 755 | /* Expansion Slot */ |
| 756 | ebc0_cs1_bnap_value = 0; |
| 757 | ebc0_cs1_bncr_value = 0; |
| 758 | ebc0_cs2_bnap_value = 0; |
| 759 | ebc0_cs2_bncr_value = 0; |
| 760 | ebc0_cs3_bnap_value = 0; |
| 761 | ebc0_cs3_bncr_value = 0; |
| 762 | } |
| 763 | ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH; |
| 764 | ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4; |
| 765 | |
| 766 | break; |
| 767 | |
| 768 | /*------------------------------------------------------------------------- */ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 769 | case BOOT_FROM_NAND_FLASH0: |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 770 | /*------------------------------------------------------------------------- */ |
Stefan Roese | c769864 | 2007-06-01 15:19:29 +0200 | [diff] [blame] | 771 | ebc0_cs0_bnap_value = EBC0_BNAP_NAND_FLASH; |
| 772 | ebc0_cs0_bncr_value = EBC0_BNCR_NAND_FLASH_CS1; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 773 | |
Stefan Roese | c769864 | 2007-06-01 15:19:29 +0200 | [diff] [blame] | 774 | ebc0_cs1_bnap_value = 0; |
| 775 | ebc0_cs1_bncr_value = 0; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 776 | ebc0_cs2_bnap_value = 0; |
| 777 | ebc0_cs2_bncr_value = 0; |
| 778 | ebc0_cs3_bnap_value = 0; |
| 779 | ebc0_cs3_bncr_value = 0; |
| 780 | |
| 781 | /* Large Flash or SRAM */ |
| 782 | ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM; |
| 783 | ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4; |
| 784 | |
| 785 | break; |
| 786 | |
| 787 | /*------------------------------------------------------------------------- */ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 788 | case BOOT_FROM_PCI: |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 789 | /*------------------------------------------------------------------------- */ |
| 790 | ebc0_cs0_bnap_value = 0; |
| 791 | ebc0_cs0_bncr_value = 0; |
| 792 | |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 793 | if ((is_nand_selected()) == true) { |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 794 | /* NAND Flash */ |
| 795 | ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH; |
| 796 | ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1; |
| 797 | ebc0_cs2_bnap_value = 0; |
| 798 | ebc0_cs2_bncr_value = 0; |
| 799 | ebc0_cs3_bnap_value = 0; |
| 800 | ebc0_cs3_bncr_value = 0; |
| 801 | } else { |
| 802 | /* Expansion Slot */ |
| 803 | ebc0_cs1_bnap_value = 0; |
| 804 | ebc0_cs1_bncr_value = 0; |
| 805 | ebc0_cs2_bnap_value = 0; |
| 806 | ebc0_cs2_bncr_value = 0; |
| 807 | ebc0_cs3_bnap_value = 0; |
| 808 | ebc0_cs3_bncr_value = 0; |
| 809 | } |
| 810 | |
York Sun | 4a59809 | 2013-04-01 11:29:11 -0700 | [diff] [blame] | 811 | if ((config_on_ebc_cs4_is_small_flash()) == true) { |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 812 | /* Small Flash */ |
| 813 | ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH; |
| 814 | ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4; |
| 815 | } else { |
| 816 | /* Large Flash or SRAM */ |
| 817 | ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM; |
| 818 | ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4; |
| 819 | } |
| 820 | |
| 821 | break; |
| 822 | |
| 823 | /*------------------------------------------------------------------------- */ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 824 | case BOOT_DEVICE_UNKNOWN: |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 825 | /*------------------------------------------------------------------------- */ |
| 826 | /* Error */ |
| 827 | break; |
| 828 | |
| 829 | } |
| 830 | |
| 831 | |
| 832 | /*-------------------------------------------------------------------------+ |
| 833 | | Initialize EBC CONFIG |
| 834 | +-------------------------------------------------------------------------*/ |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 835 | mtdcr(EBC0_CFGADDR, EBC0_CFG); |
| 836 | mtdcr(EBC0_CFGDATA, EBC0_CFG_EBTC_DRIVEN | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 837 | EBC0_CFG_PTD_ENABLED | |
| 838 | EBC0_CFG_RTC_2048PERCLK | |
| 839 | EBC0_CFG_EMPL_LOW | |
| 840 | EBC0_CFG_EMPH_LOW | |
| 841 | EBC0_CFG_CSTC_DRIVEN | |
| 842 | EBC0_CFG_BPF_ONEDW | |
| 843 | EBC0_CFG_EMS_8BIT | |
| 844 | EBC0_CFG_PME_DISABLED | |
| 845 | EBC0_CFG_PMT_ENCODE(0) ); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 846 | |
| 847 | /*-------------------------------------------------------------------------+ |
| 848 | | Initialize EBC Bank 0-4 |
| 849 | +-------------------------------------------------------------------------*/ |
| 850 | /* EBC Bank0 */ |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 851 | mtebc(PB0AP, ebc0_cs0_bnap_value); |
| 852 | mtebc(PB0CR, ebc0_cs0_bncr_value); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 853 | /* EBC Bank1 */ |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 854 | mtebc(PB1AP, ebc0_cs1_bnap_value); |
| 855 | mtebc(PB1CR, ebc0_cs1_bncr_value); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 856 | /* EBC Bank2 */ |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 857 | mtebc(PB2AP, ebc0_cs2_bnap_value); |
| 858 | mtebc(PB2CR, ebc0_cs2_bncr_value); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 859 | /* EBC Bank3 */ |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 860 | mtebc(PB3AP, ebc0_cs3_bnap_value); |
| 861 | mtebc(PB3CR, ebc0_cs3_bncr_value); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 862 | /* EBC Bank4 */ |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 863 | mtebc(PB4AP, ebc0_cs4_bnap_value); |
| 864 | mtebc(PB4CR, ebc0_cs4_bncr_value); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 865 | |
| 866 | return; |
| 867 | } |
| 868 | |
| 869 | |
| 870 | /*----------------------------------------------------------------------------+ |
| 871 | | get_uart_configuration. |
| 872 | +----------------------------------------------------------------------------*/ |
| 873 | uart_config_nb_t get_uart_configuration(void) |
| 874 | { |
Stefan Roese | 797d857 | 2005-08-11 17:56:56 +0200 | [diff] [blame] | 875 | return (L4); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 876 | } |
| 877 | |
| 878 | /*----------------------------------------------------------------------------+ |
| 879 | | set_phy_configuration_through_fpga => to EPLD |
| 880 | +----------------------------------------------------------------------------*/ |
| 881 | void set_phy_configuration_through_fpga(zmii_config_t config) |
| 882 | { |
| 883 | |
| 884 | unsigned long fpga_selection_reg; |
| 885 | |
| 886 | fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK; |
| 887 | |
| 888 | switch(config) |
| 889 | { |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 890 | case ZMII_CONFIGURATION_IS_MII: |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 891 | fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII; |
| 892 | break; |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 893 | case ZMII_CONFIGURATION_IS_RMII: |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 894 | fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII; |
| 895 | break; |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 896 | case ZMII_CONFIGURATION_IS_SMII: |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 897 | fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII; |
| 898 | break; |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 899 | case ZMII_CONFIGURATION_UNKNOWN: |
| 900 | default: |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 901 | break; |
| 902 | } |
| 903 | out8(FPGA_SELECTION_1_REG,fpga_selection_reg); |
| 904 | |
| 905 | } |
| 906 | |
| 907 | /*----------------------------------------------------------------------------+ |
| 908 | | scp_selection_in_fpga. |
| 909 | +----------------------------------------------------------------------------*/ |
| 910 | void scp_selection_in_fpga(void) |
| 911 | { |
| 912 | unsigned long fpga_selection_2_reg; |
| 913 | |
| 914 | fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK; |
| 915 | fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP; |
| 916 | out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); |
| 917 | } |
| 918 | |
| 919 | /*----------------------------------------------------------------------------+ |
| 920 | | iic1_selection_in_fpga. |
| 921 | +----------------------------------------------------------------------------*/ |
| 922 | void iic1_selection_in_fpga(void) |
| 923 | { |
| 924 | unsigned long fpga_selection_2_reg; |
| 925 | |
| 926 | fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK; |
| 927 | fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1; |
| 928 | out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); |
| 929 | } |
| 930 | |
| 931 | /*----------------------------------------------------------------------------+ |
| 932 | | dma_a_b_selection_in_fpga. |
| 933 | +----------------------------------------------------------------------------*/ |
| 934 | void dma_a_b_selection_in_fpga(void) |
| 935 | { |
| 936 | unsigned long fpga_selection_2_reg; |
| 937 | |
| 938 | fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B; |
| 939 | out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); |
| 940 | } |
| 941 | |
| 942 | /*----------------------------------------------------------------------------+ |
| 943 | | dma_a_b_unselect_in_fpga. |
| 944 | +----------------------------------------------------------------------------*/ |
| 945 | void dma_a_b_unselect_in_fpga(void) |
| 946 | { |
| 947 | unsigned long fpga_selection_2_reg; |
| 948 | |
| 949 | fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B; |
| 950 | out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); |
| 951 | } |
| 952 | |
| 953 | /*----------------------------------------------------------------------------+ |
| 954 | | dma_c_d_selection_in_fpga. |
| 955 | +----------------------------------------------------------------------------*/ |
| 956 | void dma_c_d_selection_in_fpga(void) |
| 957 | { |
| 958 | unsigned long fpga_selection_2_reg; |
| 959 | |
| 960 | fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D; |
| 961 | out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); |
| 962 | } |
| 963 | |
| 964 | /*----------------------------------------------------------------------------+ |
| 965 | | dma_c_d_unselect_in_fpga. |
| 966 | +----------------------------------------------------------------------------*/ |
| 967 | void dma_c_d_unselect_in_fpga(void) |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 968 | { |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 969 | unsigned long fpga_selection_2_reg; |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 970 | |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 971 | fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D; |
| 972 | out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 973 | } |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 974 | |
| 975 | /*----------------------------------------------------------------------------+ |
| 976 | | usb2_device_selection_in_fpga. |
| 977 | +----------------------------------------------------------------------------*/ |
| 978 | void usb2_device_selection_in_fpga(void) |
| 979 | { |
| 980 | unsigned long fpga_selection_1_reg; |
| 981 | |
| 982 | fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL; |
| 983 | out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg); |
| 984 | } |
| 985 | |
| 986 | /*----------------------------------------------------------------------------+ |
| 987 | | usb2_device_reset_through_fpga. |
| 988 | +----------------------------------------------------------------------------*/ |
| 989 | void usb2_device_reset_through_fpga(void) |
| 990 | { |
| 991 | /* Perform soft Reset pulse */ |
| 992 | unsigned long fpga_reset_reg; |
| 993 | int i; |
| 994 | |
| 995 | fpga_reset_reg = in8(FPGA_RESET_REG); |
| 996 | out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV); |
| 997 | for (i=0; i<500; i++) |
| 998 | udelay(1000); |
| 999 | out8(FPGA_RESET_REG,fpga_reset_reg); |
| 1000 | } |
| 1001 | |
| 1002 | /*----------------------------------------------------------------------------+ |
| 1003 | | usb2_host_selection_in_fpga. |
| 1004 | +----------------------------------------------------------------------------*/ |
| 1005 | void usb2_host_selection_in_fpga(void) |
| 1006 | { |
| 1007 | unsigned long fpga_selection_1_reg; |
| 1008 | |
| 1009 | fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL; |
| 1010 | out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg); |
| 1011 | } |
| 1012 | |
| 1013 | /*----------------------------------------------------------------------------+ |
| 1014 | | ndfc_selection_in_fpga. |
| 1015 | +----------------------------------------------------------------------------*/ |
| 1016 | void ndfc_selection_in_fpga(void) |
| 1017 | { |
| 1018 | unsigned long fpga_selection_1_reg; |
| 1019 | |
| 1020 | fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK; |
| 1021 | fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1; |
Stefan Roese | 797d857 | 2005-08-11 17:56:56 +0200 | [diff] [blame] | 1022 | fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1023 | out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg); |
| 1024 | } |
| 1025 | |
| 1026 | /*----------------------------------------------------------------------------+ |
| 1027 | | uart_selection_in_fpga. |
| 1028 | +----------------------------------------------------------------------------*/ |
| 1029 | void uart_selection_in_fpga(uart_config_nb_t uart_config) |
| 1030 | { |
| 1031 | /* FPGA register */ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1032 | unsigned char fpga_selection_3_reg; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1033 | |
| 1034 | /* Read FPGA Reagister */ |
| 1035 | fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG); |
| 1036 | |
| 1037 | switch (uart_config) |
| 1038 | { |
| 1039 | case L1: |
| 1040 | /* ----------------------------------------------------------------------- */ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1041 | /* L1 configuration: UART0 = 8 pins */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1042 | /* ----------------------------------------------------------------------- */ |
| 1043 | /* Configure FPGA */ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1044 | fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; |
| 1045 | fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1046 | out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg); |
| 1047 | |
| 1048 | break; |
| 1049 | |
| 1050 | case L2: |
| 1051 | /* ----------------------------------------------------------------------- */ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1052 | /* L2 configuration: UART0 = 4 pins */ |
| 1053 | /* UART1 = 4 pins */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1054 | /* ----------------------------------------------------------------------- */ |
| 1055 | /* Configure FPGA */ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1056 | fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; |
| 1057 | fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1058 | out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg); |
| 1059 | |
| 1060 | break; |
| 1061 | |
| 1062 | case L3: |
| 1063 | /* ----------------------------------------------------------------------- */ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1064 | /* L3 configuration: UART0 = 4 pins */ |
| 1065 | /* UART1 = 2 pins */ |
| 1066 | /* UART2 = 2 pins */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1067 | /* ----------------------------------------------------------------------- */ |
| 1068 | /* Configure FPGA */ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1069 | fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; |
| 1070 | fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1071 | out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg); |
| 1072 | break; |
| 1073 | |
| 1074 | case L4: |
| 1075 | /* Configure FPGA */ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1076 | fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; |
| 1077 | fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1078 | out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg); |
| 1079 | |
| 1080 | break; |
| 1081 | |
| 1082 | default: |
| 1083 | /* Unsupported UART configuration number */ |
| 1084 | for (;;) |
| 1085 | ; |
| 1086 | break; |
| 1087 | |
| 1088 | } |
| 1089 | } |
| 1090 | |
| 1091 | |
| 1092 | /*----------------------------------------------------------------------------+ |
| 1093 | | init_default_gpio |
| 1094 | +----------------------------------------------------------------------------*/ |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 1095 | void init_default_gpio(gpio_param_s (*gpio_tab)[GPIO_MAX]) |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1096 | { |
| 1097 | int i; |
| 1098 | |
| 1099 | /* Init GPIO0 */ |
| 1100 | for(i=0; i<GPIO_MAX; i++) |
| 1101 | { |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1102 | gpio_tab[GPIO0][i].add = GPIO0_BASE; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1103 | gpio_tab[GPIO0][i].in_out = GPIO_DIS; |
| 1104 | gpio_tab[GPIO0][i].alt_nb = GPIO_SEL; |
| 1105 | } |
| 1106 | |
| 1107 | /* Init GPIO1 */ |
| 1108 | for(i=0; i<GPIO_MAX; i++) |
| 1109 | { |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1110 | gpio_tab[GPIO1][i].add = GPIO1_BASE; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1111 | gpio_tab[GPIO1][i].in_out = GPIO_DIS; |
| 1112 | gpio_tab[GPIO1][i].alt_nb = GPIO_SEL; |
| 1113 | } |
| 1114 | |
| 1115 | /* EBC_CS_N(5) - GPIO0_10 */ |
| 1116 | gpio_tab[GPIO0][10].in_out = GPIO_OUT; |
| 1117 | gpio_tab[GPIO0][10].alt_nb = GPIO_ALT1; |
| 1118 | |
| 1119 | /* EBC_CS_N(4) - GPIO0_9 */ |
| 1120 | gpio_tab[GPIO0][9].in_out = GPIO_OUT; |
| 1121 | gpio_tab[GPIO0][9].alt_nb = GPIO_ALT1; |
| 1122 | } |
| 1123 | |
| 1124 | /*----------------------------------------------------------------------------+ |
| 1125 | | update_uart_ios |
| 1126 | +------------------------------------------------------------------------------ |
| 1127 | | |
| 1128 | | Set UART Configuration in PowerPC440EP |
| 1129 | | |
| 1130 | | +---------------------------------------------------------------------+ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1131 | | | Configuartion | Connector | Nb of pins | Pins | Associated | |
| 1132 | | | Number | Port Name | available | naming | CORE | |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1133 | | +-----------------+---------------+------------+--------+-------------+ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1134 | | | L1 | Port_A | 8 | UART | UART core 0 | |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1135 | | +-----------------+---------------+------------+--------+-------------+ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1136 | | | L2 | Port_A | 4 | UART1 | UART core 0 | |
| 1137 | | | (L2D) | Port_B | 4 | UART2 | UART core 1 | |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1138 | | +-----------------+---------------+------------+--------+-------------+ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1139 | | | L3 | Port_A | 4 | UART1 | UART core 0 | |
| 1140 | | | (L3D) | Port_B | 2 | UART2 | UART core 1 | |
| 1141 | | | | Port_C | 2 | UART3 | UART core 2 | |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1142 | | +-----------------+---------------+------------+--------+-------------+ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1143 | | | | Port_A | 2 | UART1 | UART core 0 | |
| 1144 | | | L4 | Port_B | 2 | UART2 | UART core 1 | |
| 1145 | | | (L4D) | Port_C | 2 | UART3 | UART core 2 | |
| 1146 | | | | Port_D | 2 | UART4 | UART core 3 | |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1147 | | +-----------------+---------------+------------+--------+-------------+ |
| 1148 | | |
| 1149 | | Involved GPIOs |
| 1150 | | |
| 1151 | | +------------------------------------------------------------------------------+ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1152 | | | GPIO | Aternate 1 | I/O | Alternate 2 | I/O | Alternate 3 | I/O | |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1153 | | +---------+------------------+-----+-----------------+-----+-------------+-----+ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1154 | | | GPIO1_2 | UART0_DCD_N | I | UART1_DSR_CTS_N | I | UART2_SOUT | O | |
| 1155 | | | GPIO1_3 | UART0_8PIN_DSR_N | I | UART1_RTS_DTR_N | O | UART2_SIN | I | |
| 1156 | | | GPIO1_4 | UART0_8PIN_CTS_N | I | NA | NA | UART3_SIN | I | |
| 1157 | | | GPIO1_5 | UART0_RTS_N | O | NA | NA | UART3_SOUT | O | |
| 1158 | | | GPIO1_6 | UART0_DTR_N | O | UART1_SOUT | O | NA | NA | |
| 1159 | | | GPIO1_7 | UART0_RI_N | I | UART1_SIN | I | NA | NA | |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1160 | | +------------------------------------------------------------------------------+ |
| 1161 | | |
| 1162 | | |
| 1163 | +----------------------------------------------------------------------------*/ |
| 1164 | |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 1165 | void update_uart_ios(uart_config_nb_t uart_config, gpio_param_s (*gpio_tab)[GPIO_MAX]) |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1166 | { |
| 1167 | switch (uart_config) |
| 1168 | { |
| 1169 | case L1: |
| 1170 | /* ----------------------------------------------------------------------- */ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1171 | /* L1 configuration: UART0 = 8 pins */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1172 | /* ----------------------------------------------------------------------- */ |
| 1173 | /* Update GPIO Configuration Table */ |
| 1174 | gpio_tab[GPIO1][2].in_out = GPIO_IN; |
| 1175 | gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1; |
| 1176 | |
| 1177 | gpio_tab[GPIO1][3].in_out = GPIO_IN; |
| 1178 | gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1; |
| 1179 | |
| 1180 | gpio_tab[GPIO1][4].in_out = GPIO_IN; |
| 1181 | gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1; |
| 1182 | |
| 1183 | gpio_tab[GPIO1][5].in_out = GPIO_OUT; |
| 1184 | gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1; |
| 1185 | |
| 1186 | gpio_tab[GPIO1][6].in_out = GPIO_OUT; |
| 1187 | gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1; |
| 1188 | |
| 1189 | gpio_tab[GPIO1][7].in_out = GPIO_IN; |
| 1190 | gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1; |
| 1191 | |
| 1192 | break; |
| 1193 | |
| 1194 | case L2: |
| 1195 | /* ----------------------------------------------------------------------- */ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1196 | /* L2 configuration: UART0 = 4 pins */ |
| 1197 | /* UART1 = 4 pins */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1198 | /* ----------------------------------------------------------------------- */ |
| 1199 | /* Update GPIO Configuration Table */ |
| 1200 | gpio_tab[GPIO1][2].in_out = GPIO_IN; |
| 1201 | gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2; |
| 1202 | |
| 1203 | gpio_tab[GPIO1][3].in_out = GPIO_OUT; |
| 1204 | gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2; |
| 1205 | |
| 1206 | gpio_tab[GPIO1][4].in_out = GPIO_IN; |
| 1207 | gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1; |
| 1208 | |
| 1209 | gpio_tab[GPIO1][5].in_out = GPIO_OUT; |
| 1210 | gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1; |
| 1211 | |
| 1212 | gpio_tab[GPIO1][6].in_out = GPIO_OUT; |
| 1213 | gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2; |
| 1214 | |
| 1215 | gpio_tab[GPIO1][7].in_out = GPIO_IN; |
| 1216 | gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2; |
| 1217 | |
| 1218 | break; |
| 1219 | |
| 1220 | case L3: |
| 1221 | /* ----------------------------------------------------------------------- */ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1222 | /* L3 configuration: UART0 = 4 pins */ |
| 1223 | /* UART1 = 2 pins */ |
| 1224 | /* UART2 = 2 pins */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1225 | /* ----------------------------------------------------------------------- */ |
| 1226 | /* Update GPIO Configuration Table */ |
| 1227 | gpio_tab[GPIO1][2].in_out = GPIO_OUT; |
| 1228 | gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3; |
| 1229 | |
| 1230 | gpio_tab[GPIO1][3].in_out = GPIO_IN; |
| 1231 | gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3; |
| 1232 | |
| 1233 | gpio_tab[GPIO1][4].in_out = GPIO_IN; |
| 1234 | gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1; |
| 1235 | |
| 1236 | gpio_tab[GPIO1][5].in_out = GPIO_OUT; |
| 1237 | gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1; |
| 1238 | |
| 1239 | gpio_tab[GPIO1][6].in_out = GPIO_OUT; |
| 1240 | gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2; |
| 1241 | |
| 1242 | gpio_tab[GPIO1][7].in_out = GPIO_IN; |
| 1243 | gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2; |
| 1244 | |
| 1245 | break; |
| 1246 | |
| 1247 | case L4: |
| 1248 | /* ----------------------------------------------------------------------- */ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1249 | /* L4 configuration: UART0 = 2 pins */ |
| 1250 | /* UART1 = 2 pins */ |
| 1251 | /* UART2 = 2 pins */ |
| 1252 | /* UART3 = 2 pins */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1253 | /* ----------------------------------------------------------------------- */ |
| 1254 | /* Update GPIO Configuration Table */ |
| 1255 | gpio_tab[GPIO1][2].in_out = GPIO_OUT; |
| 1256 | gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3; |
| 1257 | |
| 1258 | gpio_tab[GPIO1][3].in_out = GPIO_IN; |
| 1259 | gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3; |
| 1260 | |
| 1261 | gpio_tab[GPIO1][4].in_out = GPIO_IN; |
| 1262 | gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3; |
| 1263 | |
| 1264 | gpio_tab[GPIO1][5].in_out = GPIO_OUT; |
| 1265 | gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3; |
| 1266 | |
| 1267 | gpio_tab[GPIO1][6].in_out = GPIO_OUT; |
| 1268 | gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2; |
| 1269 | |
| 1270 | gpio_tab[GPIO1][7].in_out = GPIO_IN; |
| 1271 | gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2; |
| 1272 | |
| 1273 | break; |
| 1274 | |
| 1275 | default: |
| 1276 | /* Unsupported UART configuration number */ |
| 1277 | printf("ERROR - Unsupported UART configuration number.\n\n"); |
| 1278 | for (;;) |
| 1279 | ; |
| 1280 | break; |
| 1281 | |
| 1282 | } |
| 1283 | |
| 1284 | /* Set input Selection Register on Alt_Receive for UART Input Core */ |
| 1285 | out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000)); |
| 1286 | out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000)); |
| 1287 | out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000)); |
| 1288 | } |
| 1289 | |
| 1290 | /*----------------------------------------------------------------------------+ |
| 1291 | | update_ndfc_ios(void). |
| 1292 | +----------------------------------------------------------------------------*/ |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 1293 | void update_ndfc_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1294 | { |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1295 | /* Update GPIO Configuration Table */ |
| 1296 | gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */ |
| 1297 | gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1298 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1299 | gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(2) */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1300 | gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1; |
| 1301 | |
Stefan Roese | c769864 | 2007-06-01 15:19:29 +0200 | [diff] [blame] | 1302 | #if 0 |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1303 | gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(3) */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1304 | gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1; |
Stefan Roese | 3e1f1b3 | 2005-08-01 16:49:12 +0200 | [diff] [blame] | 1305 | #endif |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1306 | } |
| 1307 | |
| 1308 | /*----------------------------------------------------------------------------+ |
| 1309 | | update_zii_ios(void). |
| 1310 | +----------------------------------------------------------------------------*/ |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 1311 | void update_zii_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1312 | { |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1313 | /* Update GPIO Configuration Table */ |
| 1314 | gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */ |
| 1315 | gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1316 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1317 | gpio_tab[GPIO0][13].in_out = GPIO_IN; /* ZII_p0Rxd(1) */ |
| 1318 | gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1319 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1320 | gpio_tab[GPIO0][14].in_out = GPIO_IN; /* ZII_p0Rxd(2) */ |
| 1321 | gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1322 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1323 | gpio_tab[GPIO0][15].in_out = GPIO_IN; /* ZII_p0Rxd(3) */ |
| 1324 | gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1325 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1326 | gpio_tab[GPIO0][16].in_out = GPIO_OUT; /* ZII_p0Txd(0) */ |
| 1327 | gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1328 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1329 | gpio_tab[GPIO0][17].in_out = GPIO_OUT; /* ZII_p0Txd(1) */ |
| 1330 | gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1331 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1332 | gpio_tab[GPIO0][18].in_out = GPIO_OUT; /* ZII_p0Txd(2) */ |
| 1333 | gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1334 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1335 | gpio_tab[GPIO0][19].in_out = GPIO_OUT; /* ZII_p0Txd(3) */ |
| 1336 | gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1337 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1338 | gpio_tab[GPIO0][20].in_out = GPIO_IN; /* ZII_p0Rx_er */ |
| 1339 | gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1340 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1341 | gpio_tab[GPIO0][21].in_out = GPIO_IN; /* ZII_p0Rx_dv */ |
| 1342 | gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1343 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1344 | gpio_tab[GPIO0][22].in_out = GPIO_IN; /* ZII_p0Crs */ |
| 1345 | gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1346 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1347 | gpio_tab[GPIO0][23].in_out = GPIO_OUT; /* ZII_p0Tx_er */ |
| 1348 | gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1349 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1350 | gpio_tab[GPIO0][24].in_out = GPIO_OUT; /* ZII_p0Tx_en */ |
| 1351 | gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1352 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1353 | gpio_tab[GPIO0][25].in_out = GPIO_IN; /* ZII_p0Col */ |
| 1354 | gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1355 | |
| 1356 | } |
| 1357 | |
| 1358 | /*----------------------------------------------------------------------------+ |
| 1359 | | update_uic_0_3_irq_ios(). |
| 1360 | +----------------------------------------------------------------------------*/ |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 1361 | void update_uic_0_3_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1362 | { |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1363 | gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1364 | gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1; |
| 1365 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1366 | gpio_tab[GPIO1][9].in_out = GPIO_IN; /* UIC_IRQ(1) */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1367 | gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1; |
| 1368 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1369 | gpio_tab[GPIO1][10].in_out = GPIO_IN; /* UIC_IRQ(2) */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1370 | gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1; |
| 1371 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1372 | gpio_tab[GPIO1][11].in_out = GPIO_IN; /* UIC_IRQ(3) */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1373 | gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1; |
| 1374 | } |
| 1375 | |
| 1376 | /*----------------------------------------------------------------------------+ |
| 1377 | | update_uic_4_9_irq_ios(). |
| 1378 | +----------------------------------------------------------------------------*/ |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 1379 | void update_uic_4_9_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1380 | { |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1381 | gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1382 | gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1; |
| 1383 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1384 | gpio_tab[GPIO1][13].in_out = GPIO_IN; /* UIC_IRQ(6) */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1385 | gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1; |
| 1386 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1387 | gpio_tab[GPIO1][14].in_out = GPIO_IN; /* UIC_IRQ(7) */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1388 | gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1; |
| 1389 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1390 | gpio_tab[GPIO1][15].in_out = GPIO_IN; /* UIC_IRQ(8) */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1391 | gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1; |
| 1392 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1393 | gpio_tab[GPIO1][16].in_out = GPIO_IN; /* UIC_IRQ(9) */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1394 | gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1; |
| 1395 | } |
| 1396 | |
| 1397 | /*----------------------------------------------------------------------------+ |
| 1398 | | update_dma_a_b_ios(). |
| 1399 | +----------------------------------------------------------------------------*/ |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 1400 | void update_dma_a_b_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1401 | { |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1402 | gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1403 | gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2; |
| 1404 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1405 | gpio_tab[GPIO1][13].in_out = GPIO_BI; /* DMA_EOT/TC(1) */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1406 | gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2; |
| 1407 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1408 | gpio_tab[GPIO1][14].in_out = GPIO_IN; /* DMA_REQ(0) */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1409 | gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2; |
| 1410 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1411 | gpio_tab[GPIO1][15].in_out = GPIO_OUT; /* DMA_ACK(0) */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1412 | gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2; |
| 1413 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1414 | gpio_tab[GPIO1][16].in_out = GPIO_BI; /* DMA_EOT/TC(0) */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1415 | gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2; |
| 1416 | } |
| 1417 | |
| 1418 | /*----------------------------------------------------------------------------+ |
| 1419 | | update_dma_c_d_ios(). |
| 1420 | +----------------------------------------------------------------------------*/ |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 1421 | void update_dma_c_d_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1422 | { |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1423 | gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1424 | gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2; |
| 1425 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1426 | gpio_tab[GPIO0][1].in_out = GPIO_OUT; /* DMA_ACK(2) */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1427 | gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2; |
| 1428 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1429 | gpio_tab[GPIO0][2].in_out = GPIO_BI; /* DMA_EOT/TC(2) */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1430 | gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2; |
| 1431 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1432 | gpio_tab[GPIO0][3].in_out = GPIO_IN; /* DMA_REQ(3) */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1433 | gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2; |
| 1434 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1435 | gpio_tab[GPIO0][4].in_out = GPIO_OUT; /* DMA_ACK(3) */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1436 | gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2; |
| 1437 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1438 | gpio_tab[GPIO0][5].in_out = GPIO_BI; /* DMA_EOT/TC(3) */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1439 | gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2; |
| 1440 | |
| 1441 | } |
| 1442 | |
| 1443 | /*----------------------------------------------------------------------------+ |
| 1444 | | update_ebc_master_ios(). |
| 1445 | +----------------------------------------------------------------------------*/ |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 1446 | void update_ebc_master_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1447 | { |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1448 | gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1449 | gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1; |
| 1450 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1451 | gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1452 | gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1; |
| 1453 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1454 | gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* EBC_EXT_ACK */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1455 | gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1; |
| 1456 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1457 | gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* EBC_EXR_BUSREQ */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1458 | gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1; |
| 1459 | } |
| 1460 | |
| 1461 | /*----------------------------------------------------------------------------+ |
| 1462 | | update_usb2_device_ios(). |
| 1463 | +----------------------------------------------------------------------------*/ |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 1464 | void update_usb2_device_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1465 | { |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1466 | gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1467 | gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2; |
| 1468 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1469 | gpio_tab[GPIO0][27].in_out = GPIO_IN; /* USB2D_RXERROR */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1470 | gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2; |
| 1471 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1472 | gpio_tab[GPIO0][28].in_out = GPIO_OUT; /* USB2D_TXVALID */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1473 | gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2; |
| 1474 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1475 | gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* USB2D_PAD_SUSPNDM */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1476 | gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2; |
| 1477 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1478 | gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* USB2D_XCVRSELECT */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1479 | gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2; |
| 1480 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1481 | gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* USB2D_TERMSELECT */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1482 | gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2; |
| 1483 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1484 | gpio_tab[GPIO1][0].in_out = GPIO_OUT; /* USB2D_OPMODE0 */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1485 | gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1; |
| 1486 | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1487 | gpio_tab[GPIO1][1].in_out = GPIO_OUT; /* USB2D_OPMODE1 */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1488 | gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1; |
| 1489 | |
| 1490 | } |
| 1491 | |
| 1492 | /*----------------------------------------------------------------------------+ |
| 1493 | | update_pci_patch_ios(). |
| 1494 | +----------------------------------------------------------------------------*/ |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 1495 | void update_pci_patch_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1496 | { |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1497 | gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1498 | gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1; |
| 1499 | } |
| 1500 | |
| 1501 | /*----------------------------------------------------------------------------+ |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 1502 | | set_chip_gpio_configuration(unsigned char gpio_core, |
| 1503 | | gpio_param_s (*gpio_tab)[GPIO_MAX]) |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1504 | | Put the core impacted by clock modification and sharing in reset. |
| 1505 | | Config the select registers to resolve the sharing depending of the config. |
| 1506 | | Configure the GPIO registers. |
| 1507 | | |
| 1508 | +----------------------------------------------------------------------------*/ |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 1509 | void set_chip_gpio_configuration(unsigned char gpio_core, gpio_param_s (*gpio_tab)[GPIO_MAX]) |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1510 | { |
| 1511 | unsigned char i=0, j=0, reg_offset = 0; |
| 1512 | unsigned long gpio_reg, gpio_core_add; |
| 1513 | |
| 1514 | /* GPIO config of the GPIOs 0 to 31 */ |
| 1515 | for (i=0; i<GPIO_MAX; i++, j++) |
| 1516 | { |
| 1517 | if (i == GPIO_MAX/2) |
| 1518 | { |
| 1519 | reg_offset = 4; |
| 1520 | j = i-16; |
| 1521 | } |
| 1522 | |
| 1523 | gpio_core_add = gpio_tab[gpio_core][i].add; |
| 1524 | |
| 1525 | if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) || |
| 1526 | (gpio_tab[gpio_core][i].in_out == GPIO_BI )) |
| 1527 | { |
| 1528 | switch (gpio_tab[gpio_core][i].alt_nb) |
| 1529 | { |
| 1530 | case GPIO_SEL: |
| 1531 | break; |
| 1532 | |
| 1533 | case GPIO_ALT1: |
| 1534 | gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); |
| 1535 | gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); |
| 1536 | out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg); |
| 1537 | break; |
| 1538 | |
| 1539 | case GPIO_ALT2: |
| 1540 | gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); |
| 1541 | gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); |
| 1542 | out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg); |
| 1543 | break; |
| 1544 | |
| 1545 | case GPIO_ALT3: |
| 1546 | gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); |
| 1547 | gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); |
| 1548 | out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg); |
| 1549 | break; |
| 1550 | } |
| 1551 | } |
| 1552 | if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) || |
| 1553 | (gpio_tab[gpio_core][i].in_out == GPIO_BI )) |
| 1554 | { |
| 1555 | |
| 1556 | switch (gpio_tab[gpio_core][i].alt_nb) |
| 1557 | { |
| 1558 | case GPIO_SEL: |
| 1559 | break; |
| 1560 | case GPIO_ALT1: |
| 1561 | gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); |
| 1562 | gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2)); |
| 1563 | out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); |
| 1564 | gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); |
| 1565 | gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2)); |
| 1566 | out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); |
| 1567 | break; |
| 1568 | case GPIO_ALT2: |
| 1569 | gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); |
| 1570 | gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2)); |
| 1571 | out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); |
| 1572 | gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); |
| 1573 | gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2)); |
| 1574 | out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); |
| 1575 | break; |
| 1576 | case GPIO_ALT3: |
| 1577 | gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); |
| 1578 | gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2)); |
| 1579 | out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); |
| 1580 | gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); |
| 1581 | gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2)); |
| 1582 | out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); |
| 1583 | break; |
| 1584 | } |
| 1585 | } |
| 1586 | } |
| 1587 | } |
| 1588 | |
| 1589 | /*----------------------------------------------------------------------------+ |
| 1590 | | force_bup_core_selection. |
| 1591 | +----------------------------------------------------------------------------*/ |
| 1592 | void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P) |
| 1593 | { |
| 1594 | /* Pointer invalid */ |
| 1595 | if (core_select_P == NULL) |
| 1596 | { |
| 1597 | printf("Configuration invalid pointer 1\n"); |
| 1598 | for (;;) |
| 1599 | ; |
| 1600 | } |
| 1601 | |
| 1602 | /* L4 Selection */ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1603 | *(core_select_P+UART_CORE0) = CORE_SELECTED; |
| 1604 | *(core_select_P+UART_CORE1) = CORE_SELECTED; |
| 1605 | *(core_select_P+UART_CORE2) = CORE_SELECTED; |
| 1606 | *(core_select_P+UART_CORE3) = CORE_SELECTED; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1607 | |
| 1608 | /* RMII Selection */ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1609 | *(core_select_P+RMII_SEL) = CORE_SELECTED; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1610 | |
| 1611 | /* External Interrupt 0-9 selection */ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1612 | *(core_select_P+UIC_0_3) = CORE_SELECTED; |
| 1613 | *(core_select_P+UIC_4_9) = CORE_SELECTED; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1614 | |
Stefan Roese | 797d857 | 2005-08-11 17:56:56 +0200 | [diff] [blame] | 1615 | *(core_select_P+SCP_CORE) = CORE_SELECTED; |
| 1616 | *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED; |
| 1617 | *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED; |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1618 | *(core_select_P+USB1_DEVICE) = CORE_SELECTED; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1619 | |
Stefan Roese | 797d857 | 2005-08-11 17:56:56 +0200 | [diff] [blame] | 1620 | if (is_nand_selected()) { |
| 1621 | *(core_select_P+NAND_FLASH) = CORE_SELECTED; |
| 1622 | } |
| 1623 | |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1624 | *config_val_P = CONFIG_IS_VALID; |
| 1625 | |
| 1626 | } |
| 1627 | |
| 1628 | /*----------------------------------------------------------------------------+ |
| 1629 | | configure_ppc440ep_pins. |
| 1630 | +----------------------------------------------------------------------------*/ |
| 1631 | void configure_ppc440ep_pins(void) |
| 1632 | { |
| 1633 | uart_config_nb_t uart_configuration; |
| 1634 | config_validity_t config_val = CONFIG_IS_INVALID; |
| 1635 | |
| 1636 | /* Create Core Selection Table */ |
| 1637 | core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] = |
| 1638 | { |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1639 | CORE_NOT_SELECTED, /* IIC_CORE, */ |
| 1640 | CORE_NOT_SELECTED, /* SPC_CORE, */ |
| 1641 | CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */ |
| 1642 | CORE_NOT_SELECTED, /* UIC_4_9, */ |
| 1643 | CORE_NOT_SELECTED, /* USB2_HOST, */ |
| 1644 | CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */ |
| 1645 | CORE_NOT_SELECTED, /* USB2_DEVICE, */ |
| 1646 | CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */ |
| 1647 | CORE_NOT_SELECTED, /* USB1_DEVICE, */ |
| 1648 | CORE_NOT_SELECTED, /* EBC_MASTER, */ |
| 1649 | CORE_NOT_SELECTED, /* NAND_FLASH, */ |
| 1650 | CORE_NOT_SELECTED, /* UART_CORE0, */ |
| 1651 | CORE_NOT_SELECTED, /* UART_CORE1, */ |
| 1652 | CORE_NOT_SELECTED, /* UART_CORE2, */ |
| 1653 | CORE_NOT_SELECTED, /* UART_CORE3, */ |
| 1654 | CORE_NOT_SELECTED, /* MII_SEL, */ |
| 1655 | CORE_NOT_SELECTED, /* RMII_SEL, */ |
| 1656 | CORE_NOT_SELECTED, /* SMII_SEL, */ |
| 1657 | CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */ |
| 1658 | CORE_NOT_SELECTED, /* UIC_0_3 */ |
| 1659 | CORE_NOT_SELECTED, /* USB1_HOST */ |
| 1660 | CORE_NOT_SELECTED /* PCI_PATCH */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1661 | }; |
| 1662 | |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 1663 | gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX]; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1664 | |
| 1665 | /* Table Default Initialisation + FPGA Access */ |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 1666 | init_default_gpio(gpio_tab); |
| 1667 | set_chip_gpio_configuration(GPIO0, gpio_tab); |
| 1668 | set_chip_gpio_configuration(GPIO1, gpio_tab); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1669 | |
| 1670 | /* Update Table */ |
| 1671 | force_bup_core_selection(ppc440ep_core_selection, &config_val); |
| 1672 | #if 0 /* test-only */ |
| 1673 | /* If we are running PIBS 1, force known configuration */ |
| 1674 | update_core_selection_table(ppc440ep_core_selection, &config_val); |
| 1675 | #endif |
| 1676 | |
| 1677 | /*----------------------------------------------------------------------------+ |
| 1678 | | SDR + ios table update + fpga initialization |
| 1679 | +----------------------------------------------------------------------------*/ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1680 | unsigned long sdr0_pfc1 = 0; |
| 1681 | unsigned long sdr0_usb0 = 0; |
| 1682 | unsigned long sdr0_mfr = 0; |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1683 | |
| 1684 | /* PCI Always selected */ |
| 1685 | |
| 1686 | /* I2C Selection */ |
| 1687 | if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED) |
| 1688 | { |
| 1689 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL; |
| 1690 | iic1_selection_in_fpga(); |
| 1691 | } |
| 1692 | |
| 1693 | /* SCP Selection */ |
| 1694 | if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED) |
| 1695 | { |
| 1696 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL; |
| 1697 | scp_selection_in_fpga(); |
| 1698 | } |
| 1699 | |
| 1700 | /* UIC 0:3 Selection */ |
| 1701 | if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED) |
| 1702 | { |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 1703 | update_uic_0_3_irq_ios(gpio_tab); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1704 | dma_a_b_unselect_in_fpga(); |
| 1705 | } |
| 1706 | |
| 1707 | /* UIC 4:9 Selection */ |
| 1708 | if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED) |
| 1709 | { |
| 1710 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL; |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 1711 | update_uic_4_9_irq_ios(gpio_tab); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1712 | } |
| 1713 | |
| 1714 | /* DMA AB Selection */ |
| 1715 | if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED) |
| 1716 | { |
| 1717 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL; |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 1718 | update_dma_a_b_ios(gpio_tab); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1719 | dma_a_b_selection_in_fpga(); |
| 1720 | } |
| 1721 | |
| 1722 | /* DMA CD Selection */ |
| 1723 | if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED) |
| 1724 | { |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 1725 | update_dma_c_d_ios(gpio_tab); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1726 | dma_c_d_selection_in_fpga(); |
| 1727 | } |
| 1728 | |
| 1729 | /* EBC Master Selection */ |
| 1730 | if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED) |
| 1731 | { |
| 1732 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL; |
| 1733 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL; |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 1734 | update_ebc_master_ios(gpio_tab); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1735 | } |
| 1736 | |
| 1737 | /* PCI Patch Enable */ |
| 1738 | if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED) |
| 1739 | { |
| 1740 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL; |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 1741 | update_pci_patch_ios(gpio_tab); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1742 | } |
| 1743 | |
| 1744 | /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */ |
| 1745 | if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED) |
| 1746 | { |
| 1747 | /* Not Implemented in PowerPC 440EP Pass1-Pass2 */ |
| 1748 | printf("Invalid configuration => USB2 Host selected\n"); |
| 1749 | for (;;) |
| 1750 | ; |
| 1751 | /*usb2_host_selection_in_fpga(); */ |
| 1752 | } |
| 1753 | |
| 1754 | /* USB2.0 Device Selection */ |
| 1755 | if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED) |
| 1756 | { |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 1757 | update_usb2_device_ios(gpio_tab); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1758 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL; |
| 1759 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE; |
| 1760 | |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 1761 | mfsdr(SDR0_USB0, sdr0_usb0); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1762 | sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK; |
| 1763 | sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL; |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 1764 | mtsdr(SDR0_USB0, sdr0_usb0); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1765 | |
| 1766 | usb2_device_selection_in_fpga(); |
| 1767 | } |
| 1768 | |
| 1769 | /* USB1.1 Device Selection */ |
| 1770 | if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED) |
| 1771 | { |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 1772 | mfsdr(SDR0_USB0, sdr0_usb0); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1773 | sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK; |
| 1774 | sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL; |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 1775 | mtsdr(SDR0_USB0, sdr0_usb0); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1776 | } |
| 1777 | |
| 1778 | /* USB1.1 Host Selection */ |
| 1779 | if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED) |
| 1780 | { |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 1781 | mfsdr(SDR0_USB0, sdr0_usb0); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1782 | sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK; |
| 1783 | sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE; |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 1784 | mtsdr(SDR0_USB0, sdr0_usb0); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1785 | } |
| 1786 | |
| 1787 | /* NAND Flash Selection */ |
| 1788 | if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED) |
| 1789 | { |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 1790 | update_ndfc_ios(gpio_tab); |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 1791 | mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL | |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1792 | SDR0_CUST0_NDFC_ENABLE | |
| 1793 | SDR0_CUST0_NDFC_BW_8_BIT | |
| 1794 | SDR0_CUST0_NDFC_ARE_MASK | |
Stefan Roese | 797d857 | 2005-08-11 17:56:56 +0200 | [diff] [blame] | 1795 | SDR0_CUST0_CHIPSELGAT_EN1 | |
| 1796 | SDR0_CUST0_CHIPSELGAT_EN2); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1797 | ndfc_selection_in_fpga(); |
| 1798 | } |
| 1799 | else |
| 1800 | { |
| 1801 | /* Set Mux on EMAC */ |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 1802 | mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_EMAC_SEL); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1803 | } |
| 1804 | |
| 1805 | /* MII Selection */ |
| 1806 | if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED) |
| 1807 | { |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 1808 | update_zii_ios(gpio_tab); |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 1809 | mfsdr(SDR0_MFR, sdr0_mfr); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1810 | sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII; |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 1811 | mtsdr(SDR0_MFR, sdr0_mfr); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1812 | |
| 1813 | set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII); |
| 1814 | } |
| 1815 | |
| 1816 | /* RMII Selection */ |
| 1817 | if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED) |
| 1818 | { |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 1819 | update_zii_ios(gpio_tab); |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 1820 | mfsdr(SDR0_MFR, sdr0_mfr); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1821 | sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M; |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 1822 | mtsdr(SDR0_MFR, sdr0_mfr); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1823 | |
| 1824 | set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII); |
| 1825 | } |
| 1826 | |
| 1827 | /* SMII Selection */ |
| 1828 | if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED) |
| 1829 | { |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 1830 | update_zii_ios(gpio_tab); |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 1831 | mfsdr(SDR0_MFR, sdr0_mfr); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1832 | sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII; |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 1833 | mtsdr(SDR0_MFR, sdr0_mfr); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1834 | |
| 1835 | set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII); |
| 1836 | } |
| 1837 | |
| 1838 | /* UART Selection */ |
| 1839 | uart_configuration = get_uart_configuration(); |
| 1840 | switch (uart_configuration) |
| 1841 | { |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1842 | case L1: /* L1 Selection */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1843 | /* UART0 8 pins Only */ |
| 1844 | /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */ |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1845 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1846 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS; |
| 1847 | break; |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1848 | case L2: /* L2 Selection */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1849 | /* UART0 and UART1 4 pins */ |
| 1850 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; |
| 1851 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS; |
| 1852 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; |
| 1853 | break; |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1854 | case L3: /* L3 Selection */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1855 | /* UART0 4 pins, UART1 and UART2 2 pins */ |
| 1856 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; |
| 1857 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS; |
| 1858 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; |
| 1859 | break; |
Wolfgang Denk | 8dd4d33 | 2005-08-06 01:42:58 +0200 | [diff] [blame] | 1860 | case L4: /* L4 Selection */ |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1861 | /* UART0, UART1, UART2 and UART3 2 pins */ |
| 1862 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; |
| 1863 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS; |
| 1864 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; |
| 1865 | break; |
| 1866 | } |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 1867 | update_uart_ios(uart_configuration, gpio_tab); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1868 | |
| 1869 | /* UART Selection in all cases */ |
| 1870 | uart_selection_in_fpga(uart_configuration); |
| 1871 | |
| 1872 | /* Packet Reject Function Available */ |
| 1873 | if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED) |
| 1874 | { |
| 1875 | /* Set UPR Bit in SDR0_PFC1 Register */ |
| 1876 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE; |
| 1877 | } |
| 1878 | |
| 1879 | /* Packet Reject Function Enable */ |
| 1880 | if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED) |
| 1881 | { |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 1882 | mfsdr(SDR0_MFR, sdr0_mfr); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1883 | sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;; |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 1884 | mtsdr(SDR0_MFR, sdr0_mfr); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1885 | } |
| 1886 | |
| 1887 | /* Perform effective access to hardware */ |
Stefan Roese | 918010a | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 1888 | mtsdr(SDR0_PFC1, sdr0_pfc1); |
Eugene OBrien | c59d1a0 | 2007-07-31 10:24:56 +0200 | [diff] [blame] | 1889 | set_chip_gpio_configuration(GPIO0, gpio_tab); |
| 1890 | set_chip_gpio_configuration(GPIO1, gpio_tab); |
Stefan Roese | 363330b | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 1891 | |
| 1892 | /* USB2.0 Device Reset must be done after GPIO setting */ |
| 1893 | if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED) |
| 1894 | usb2_device_reset_through_fpga(); |
| 1895 | |
| 1896 | } |