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git01.mediatek.com / filogic / uboot / a28e815c78df8645cc484c63cc70eea91503bf4d / . / configs / evb-rk3288_defconfig
blob: 0d2831158dac57f888a9add4db56e123edef1805 [file] [log] [blame]
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_ROCKCHIP=y
3CONFIG_SYS_MALLOC_F_LEN=0x2000
4CONFIG_ROCKCHIP_RK3288=y
Masahiro Yamada74f09b82016-12-07 22:10:25 +0900[diff] [blame]5CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]6CONFIG_TARGET_EVB_RK3288=y
7CONFIG_SPL_STACK_R_ADDR=0x80000
8CONFIG_DEFAULT_DEVICE_TREE="rk3288-evb"
Tom Rini256aa742017-06-19 09:47:40 -0400[diff] [blame]9CONFIG_DEBUG_UART=y
Simon Glass4458d3b2016-10-17 20:12:35 -0600[diff] [blame]10CONFIG_SILENT_CONSOLE=y
Simon Glass9fd2a022016-10-17 20:12:37 -0600[diff] [blame]11CONFIG_CONSOLE_MUX=y
12# CONFIG_DISPLAY_CPUINFO is not set
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]13CONFIG_SPL_STACK_R=y
14CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]15# CONFIG_CMD_IMLS is not set
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]16CONFIG_CMD_GPT=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]17CONFIG_CMD_MMC=y
18CONFIG_CMD_SF=y
19CONFIG_CMD_SPI=y
20CONFIG_CMD_I2C=y
21CONFIG_CMD_GPIO=y
22# CONFIG_CMD_SETEXPR is not set
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]23CONFIG_CMD_CACHE=y
24CONFIG_CMD_TIME=y
25CONFIG_CMD_PMIC=y
26CONFIG_CMD_REGULATOR=y
Patrick Delaunayf7e07722017-01-27 11:00:37 +0100[diff] [blame]27# CONFIG_SPL_DOS_PARTITION is not set
Patrick Delaunay21d3bce2017-01-27 11:00:38 +0100[diff] [blame]28# CONFIG_SPL_ISO_PARTITION is not set
Patrick Delaunay8a4f2bd2017-01-27 11:00:41 +0100[diff] [blame]29# CONFIG_SPL_EFI_PARTITION is not set
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]30CONFIG_SPL_PARTITION_UUIDS=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]31CONFIG_SPL_OF_CONTROL=y
32CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
33CONFIG_REGMAP=y
34CONFIG_SPL_REGMAP=y
35CONFIG_SYSCON=y
36CONFIG_SPL_SYSCON=y
37CONFIG_CLK=y
38CONFIG_SPL_CLK=y
39CONFIG_ROCKCHIP_GPIO=y
40CONFIG_SYS_I2C_ROCKCHIP=y
41CONFIG_LED=y
42CONFIG_LED_GPIO=y
Masahiro Yamada7942e912017-01-10 13:32:04 +0900[diff] [blame]43CONFIG_MMC_DW=y
Masahiro Yamadadc607f82017-01-10 13:32:03 +0900[diff] [blame]44CONFIG_MMC_DW_ROCKCHIP=y
Jacob Chen5c3166d2017-02-23 14:20:17 +0800[diff] [blame]45CONFIG_DM_ETH=y
Jacob Chen5c3166d2017-02-23 14:20:17 +0800[diff] [blame]46CONFIG_ETH_DESIGNWARE=y
47CONFIG_GMAC_ROCKCHIP=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]48CONFIG_PINCTRL=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]49CONFIG_SPL_PINCTRL=y
50# CONFIG_SPL_PINCTRL_FULL is not set
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200[diff] [blame]51CONFIG_PINCTRL_ROCKCHIP_RK3288=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]52CONFIG_DM_PMIC=y
53CONFIG_PMIC_ACT8846=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]54CONFIG_REGULATOR_ACT8846=y
55CONFIG_DM_REGULATOR_FIXED=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]56CONFIG_PWM_ROCKCHIP=y
57CONFIG_RAM=y
58CONFIG_SPL_RAM=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]59CONFIG_DEBUG_UART_BASE=0xff690000
60CONFIG_DEBUG_UART_CLOCK=24000000
61CONFIG_DEBUG_UART_SHIFT=2
62CONFIG_SYS_NS16550=y
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]63CONFIG_SYSRESET=y
Xu Ziyuan3da09a82016-07-05 18:06:30 +0800[diff] [blame]64CONFIG_USE_TINY_PRINTF=y
65CONFIG_CMD_DHRYSTONE=y
66CONFIG_ERRNO_STR=y