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git01.mediatek.com / filogic / uboot / a287017af059090dd1a379010f7b01e66d7b042e / . / include / configs / sama5d3xek.h
blob: ccb3842c1c2bc5e49b781fc5ceeba81fec341090 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]2/*
3 * Configuation settings for the SAMA5D3xEK board.
4 *
5 * Copyright (C) 2012 - 2013 Atmel
6 *
7 * based on at91sam9m10g45ek.h by:
8 * Stelian Pop <stelian@popies.net>
9 * Lead Tech Design <www.leadtechdesign.com>
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
Wu, Josh42587542015-03-30 14:51:19 +0800[diff] [blame]15#include "at91-sama5_common.h"
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]16
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]17/*
18 * This needs to be defined for the OHCI code to work but it is defined as
19 * ATMEL_ID_UHPHS in the CPU specific header files.
20 */
Wenyou Yangd19b9012017-09-14 11:07:42 +0800[diff] [blame]21#define ATMEL_ID_UHP 32
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]22
23/*
24 * Specify the clock enable bit in the PMC_SCER register.
25 */
Wenyou Yangd19b9012017-09-14 11:07:42 +0800[diff] [blame]26#define ATMEL_PMC_UHP (1 << 6)
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]27
Bo Shenb15f4f62014-07-18 16:43:08 +0800[diff] [blame]28/* NOR flash */
Masahiro Yamada8cea9b52017-02-11 22:43:54 +0900[diff] [blame]29#ifdef CONFIG_MTD_NOR_FLASH
Bo Shenb15f4f62014-07-18 16:43:08 +0800[diff] [blame]30#define CONFIG_SYS_FLASH_BASE 0x10000000
Bo Shenb15f4f62014-07-18 16:43:08 +0800[diff] [blame]31#endif
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]32
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]33/* SDRAM */
Wenyou Yangd19b9012017-09-14 11:07:42 +0800[diff] [blame]34#define CONFIG_SYS_SDRAM_BASE 0x20000000
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]35#define CONFIG_SYS_SDRAM_SIZE 0x20000000
36
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]37/* SerialFlash */
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]38
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]39/* NAND flash */
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]40#ifdef CONFIG_CMD_NAND
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]41#define CONFIG_SYS_MAX_NAND_DEVICE 1
Wenyou Yangd19b9012017-09-14 11:07:42 +0800[diff] [blame]42#define CONFIG_SYS_NAND_BASE 0x60000000
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]43/* our ALE is AD21 */
44#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
45/* our CLE is AD22 */
46#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Tom Rini00448d22017-07-28 21:31:42 -0400[diff] [blame]47#endif
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]48
Bo Shenf92b2982013-11-15 11:12:38 +0800[diff] [blame]49/* SPL */
Bo Shenf92b2982013-11-15 11:12:38 +0800[diff] [blame]50
Bo Shen37a36b32014-03-03 14:47:15 +0800[diff] [blame]51#define CONFIG_SYS_MONITOR_LEN (512 << 10)
52
Bo Shen60f3dd32013-05-12 22:40:54 +0000[diff] [blame]53#endif