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git01.mediatek.com / filogic / uboot / a285ea6bc124dddc57e66e52d693cae691873cf7 / . / arch / sandbox / dts / test.dts
blob: 9077a82876f277f3dccfa3f7f8e41af2975a90cf [file] [log] [blame]
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]1/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]7 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]8
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]9 aliases {
10 console = &uart0;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]11 eth0 = "/eth@10002000";
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]12 eth3 = &eth_3;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]13 eth5 = &eth_5;
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]14 i2c0 = "/i2c@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +0200[diff] [blame]15 pci0 = &pci;
Nishanth Menonedf85812015-09-17 15:42:41 -0500[diff] [blame]16 remoteproc1 = &rproc_1;
17 remoteproc2 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]18 rtc0 = &rtc_0;
19 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]20 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +0200[diff] [blame]21 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]22 testbus3 = "/some-bus";
23 testfdt0 = "/some-bus/c-test@0";
24 testfdt1 = "/some-bus/c-test@1";
25 testfdt3 = "/b-test";
26 testfdt5 = "/some-bus/c-test@5";
27 testfdt8 = "/a-test";
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]28 usb0 = &usb_0;
29 usb1 = &usb_1;
30 usb2 = &usb_2;
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]31 };
32
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]33 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]34 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]35 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]36 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]37 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]38 u-boot,dm-pre-reloc;
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]39 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
40 <0>, <&gpio_a 12>;
41 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
42 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
43 <&gpio_b 9 0xc 3 2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]44 };
45
46 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]47 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]48 compatible = "not,compatible";
49 };
50
51 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]52 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]53 };
54
55 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]56 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]57 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]58 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]59 ping-add = <3>;
60 };
61
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200[diff] [blame]62 phy_provider0: gen_phy@0 {
63 compatible = "sandbox,phy";
64 #phy-cells = <1>;
65 };
66
67 phy_provider1: gen_phy@1 {
68 compatible = "sandbox,phy";
69 #phy-cells = <0>;
70 broken;
71 };
72
73 gen_phy_user: gen_phy_user {
74 compatible = "simple-bus";
75 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
76 phy-names = "phy1", "phy2", "phy3";
77 };
78
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]79 some-bus {
80 #address-cells = <1>;
81 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]82 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]83 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]84 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]85 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]86 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]87 compatible = "denx,u-boot-fdt-test";
88 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]89 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]90 ping-add = <5>;
91 };
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]92 c-test@0 {
93 compatible = "denx,u-boot-fdt-test";
94 reg = <0>;
95 ping-expect = <6>;
96 ping-add = <6>;
97 };
98 c-test@1 {
99 compatible = "denx,u-boot-fdt-test";
100 reg = <1>;
101 ping-expect = <7>;
102 ping-add = <7>;
103 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]104 };
105
106 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]107 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600[diff] [blame]108 ping-expect = <6>;
109 ping-add = <6>;
110 compatible = "google,another-fdt-test";
111 };
112
113 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]114 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]115 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]116 ping-add = <6>;
117 compatible = "google,another-fdt-test";
118 };
119
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]120 f-test {
121 compatible = "denx,u-boot-fdt-test";
122 };
123
124 g-test {
125 compatible = "denx,u-boot-fdt-test";
126 };
127
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]128 clk_fixed: clk-fixed {
129 compatible = "fixed-clock";
130 #clock-cells = <0>;
131 clock-frequency = <1234>;
132 };
133
134 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]135 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]136 #clock-cells = <1>;
137 };
138
139 clk-test {
140 compatible = "sandbox,clk-test";
141 clocks = <&clk_fixed>,
142 <&clk_sandbox 1>,
143 <&clk_sandbox 0>;
144 clock-names = "fixed", "i2c", "spi";
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]145 };
146
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]147 eth@10002000 {
148 compatible = "sandbox,eth";
149 reg = <0x10002000 0x1000>;
150 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x00>;
151 };
152
153 eth_5: eth@10003000 {
154 compatible = "sandbox,eth";
155 reg = <0x10003000 0x1000>;
156 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x11>;
157 };
158
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]159 eth_3: sbe5 {
160 compatible = "sandbox,eth";
161 reg = <0x10005000 0x1000>;
162 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x33>;
163 };
164
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]165 eth@10004000 {
166 compatible = "sandbox,eth";
167 reg = <0x10004000 0x1000>;
168 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x22>;
169 };
170
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]171 gpio_a: base-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]172 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]173 gpio-controller;
174 #gpio-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]175 gpio-bank-name = "a";
176 num-gpios = <20>;
177 };
178
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]179 gpio_b: extra-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]180 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]181 gpio-controller;
182 #gpio-cells = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]183 gpio-bank-name = "b";
184 num-gpios = <10>;
185 };
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]186
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]187 i2c@0 {
188 #address-cells = <1>;
189 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]190 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]191 compatible = "sandbox,i2c";
192 clock-frequency = <100000>;
193 eeprom@2c {
194 reg = <0x2c>;
195 compatible = "i2c-eeprom";
196 emul {
197 compatible = "sandbox,i2c-eeprom";
198 sandbox,filename = "i2c.bin";
199 sandbox,size = <256>;
200 };
201 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]202
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]203 rtc_0: rtc@43 {
204 reg = <0x43>;
205 compatible = "sandbox-rtc";
206 emul {
207 compatible = "sandbox,i2c-rtc";
208 };
209 };
210
211 rtc_1: rtc@61 {
212 reg = <0x61>;
213 compatible = "sandbox-rtc";
214 emul {
215 compatible = "sandbox,i2c-rtc";
216 };
217 };
218
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]219 sandbox_pmic: sandbox_pmic {
220 reg = <0x40>;
221 };
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]222 };
223
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100[diff] [blame]224 adc@0 {
225 compatible = "sandbox,adc";
226 vdd-supply = <&buck2>;
227 vss-microvolts = <0>;
228 };
229
Simon Glass90b6fef2016-01-18 19:52:26 -0700[diff] [blame]230 lcd {
231 u-boot,dm-pre-reloc;
232 compatible = "sandbox,lcd-sdl";
233 xres = <1366>;
234 yres = <768>;
235 };
236
Simon Glassd783eb32015-07-06 12:54:34 -0600[diff] [blame]237 leds {
238 compatible = "gpio-leds";
239
240 iracibble {
241 gpios = <&gpio_a 1 0>;
242 label = "sandbox:red";
243 };
244
245 martinet {
246 gpios = <&gpio_a 2 0>;
247 label = "sandbox:green";
248 };
249 };
250
Stephen Warren62f2c902016-05-16 17:41:37 -0600[diff] [blame]251 mbox: mbox {
252 compatible = "sandbox,mbox";
253 #mbox-cells = <1>;
254 };
255
256 mbox-test {
257 compatible = "sandbox,mbox-test";
258 mboxes = <&mbox 100>, <&mbox 1>;
259 mbox-names = "other", "test";
260 };
261
Simon Glassd3e58e42015-07-06 12:54:32 -0600[diff] [blame]262 mmc {
263 compatible = "sandbox,mmc";
264 };
265
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]266 pci: pci-controller {
267 compatible = "sandbox,pci";
268 device_type = "pci";
269 #address-cells = <3>;
270 #size-cells = <2>;
271 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
272 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
273 pci@1f,0 {
274 compatible = "pci-generic";
275 reg = <0xf800 0 0 0 0>;
276 emul@1f,0 {
277 compatible = "sandbox,swap-case";
278 };
279 };
280 };
281
Stephen Warren92c67fa2016-07-13 13:45:31 -0600[diff] [blame]282 pwrdom: power-domain {
283 compatible = "sandbox,power-domain";
284 #power-domain-cells = <1>;
285 };
286
287 power-domain-test {
288 compatible = "sandbox,power-domain-test";
289 power-domains = <&pwrdom 2>;
290 };
291
Simon Glasse62f4be2017-04-16 21:01:11 -0600[diff] [blame]292 pwm {
293 compatible = "sandbox,pwm";
294 };
295
296 pwm2 {
297 compatible = "sandbox,pwm";
298 };
299
Simon Glass3d355e62015-07-06 12:54:31 -0600[diff] [blame]300 ram {
301 compatible = "sandbox,ram";
302 };
303
Simon Glassd860f222015-07-06 12:54:29 -0600[diff] [blame]304 reset@0 {
305 compatible = "sandbox,warm-reset";
306 };
307
308 reset@1 {
309 compatible = "sandbox,reset";
310 };
311
Stephen Warren6488e642016-06-17 09:43:59 -0600[diff] [blame]312 resetc: reset-ctl {
313 compatible = "sandbox,reset-ctl";
314 #reset-cells = <1>;
315 };
316
317 reset-ctl-test {
318 compatible = "sandbox,reset-ctl-test";
319 resets = <&resetc 100>, <&resetc 2>;
320 reset-names = "other", "test";
321 };
322
Nishanth Menonedf85812015-09-17 15:42:41 -0500[diff] [blame]323 rproc_1: rproc@1 {
324 compatible = "sandbox,test-processor";
325 remoteproc-name = "remoteproc-test-dev1";
326 };
327
328 rproc_2: rproc@2 {
329 compatible = "sandbox,test-processor";
330 internal-memory-mapped;
331 remoteproc-name = "remoteproc-test-dev2";
332 };
333
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]334 spi@0 {
335 #address-cells = <1>;
336 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]337 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]338 compatible = "sandbox,spi";
339 cs-gpios = <0>, <&gpio_a 0>;
340 spi.bin@0 {
341 reg = <0>;
342 compatible = "spansion,m25p16", "spi-flash";
343 spi-max-frequency = <40000000>;
344 sandbox,filename = "spi.bin";
345 };
346 };
347
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]348 syscon@0 {
349 compatible = "sandbox,syscon0";
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]350 reg = <0x10 4>;
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]351 };
352
353 syscon@1 {
354 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]355 reg = <0x20 5
356 0x28 6
357 0x30 7
358 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]359 };
360
Thomas Chou6f2cfbf2015-12-11 16:27:34 +0800[diff] [blame]361 timer {
362 compatible = "sandbox,timer";
363 clock-frequency = <1000000>;
364 };
365
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]366 uart0: serial {
367 compatible = "sandbox,serial";
368 u-boot,dm-pre-reloc;
Joe Hershberger4c197242015-03-22 17:09:15 -0500[diff] [blame]369 };
370
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]371 usb_0: usb@0 {
372 compatible = "sandbox,usb";
373 status = "disabled";
374 hub {
375 compatible = "sandbox,usb-hub";
376 #address-cells = <1>;
377 #size-cells = <0>;
378 flash-stick {
379 reg = <0>;
380 compatible = "sandbox,usb-flash";
381 };
382 };
383 };
384
385 usb_1: usb@1 {
386 compatible = "sandbox,usb";
387 hub {
388 compatible = "usb-hub";
389 usb,device-class = <9>;
390 hub-emul {
391 compatible = "sandbox,usb-hub";
392 #address-cells = <1>;
393 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -0700[diff] [blame]394 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]395 reg = <0>;
396 compatible = "sandbox,usb-flash";
397 sandbox,filepath = "testflash.bin";
398 };
399
Simon Glass4700fe52015-11-08 23:48:01 -0700[diff] [blame]400 flash-stick@1 {
401 reg = <1>;
402 compatible = "sandbox,usb-flash";
403 sandbox,filepath = "testflash1.bin";
404 };
405
406 flash-stick@2 {
407 reg = <2>;
408 compatible = "sandbox,usb-flash";
409 sandbox,filepath = "testflash2.bin";
410 };
411
Simon Glassc0ccc722015-11-08 23:48:08 -0700[diff] [blame]412 keyb@3 {
413 reg = <3>;
414 compatible = "sandbox,usb-keyb";
415 };
416
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]417 };
418 };
419 };
420
421 usb_2: usb@2 {
422 compatible = "sandbox,usb";
423 status = "disabled";
424 };
425
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200[diff] [blame]426 spmi: spmi@0 {
427 compatible = "sandbox,spmi";
428 #address-cells = <0x1>;
429 #size-cells = <0x1>;
430 pm8916@0 {
431 compatible = "qcom,spmi-pmic";
432 reg = <0x0 0x1>;
433 #address-cells = <0x1>;
434 #size-cells = <0x1>;
435
436 spmi_gpios: gpios@c000 {
437 compatible = "qcom,pm8916-gpio";
438 reg = <0xc000 0x400>;
439 gpio-controller;
440 gpio-count = <4>;
441 #gpio-cells = <2>;
442 gpio-bank-name="spmi";
443 };
444 };
445 };
maxims@google.comdaea6d42017-04-17 12:00:21 -0700[diff] [blame]446
447 wdt0: wdt@0 {
448 compatible = "sandbox,wdt";
449 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]450};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]451
452#include "sandbox_pmic.dtsi"