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Rafal Jaworowskid3a02c32007-07-27 14:43:59 +02001/*
2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
Wolfgang Denkf342f862009-05-16 10:47:45 +02004 * Copyright (C) 2000-2009 Wolfgang Denk <wd@denx.de>
Kumar Gala6a6d9482009-07-28 21:49:52 -05005 * Copyright Freescale Semiconductor, Inc. 2004, 2006.
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +02006 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +02008 *
9 * Based on the MPC83xx code.
10 */
11
12/*
13 * U-Boot - Startup Code for MPC512x based Embedded Boards
14 */
15
Wolfgang Denk0191e472010-10-26 14:34:52 +020016#include <asm-offsets.h>
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +020017#include <config.h>
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +020018#include <version.h>
19
20#define CONFIG_521X 1 /* needed for Linux kernel header files*/
21
Wolfgang Denkf342f862009-05-16 10:47:45 +020022#include <asm/immap_512x.h>
23#include "asm-offsets.h"
24
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +020025#include <ppc_asm.tmpl>
26#include <ppc_defs.h>
27
28#include <asm/cache.h>
29#include <asm/mmu.h>
Peter Tyser3a1362d2010-10-14 23:33:24 -050030#include <asm/u-boot.h>
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +020031
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +020032/*
33 * Floating Point enable, Machine Check and Recoverable Interr.
34 */
35#undef MSR_KERNEL
36#ifdef DEBUG
37#define MSR_KERNEL (MSR_FP|MSR_RI)
38#else
39#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
40#endif
41
42/* Macros for manipulating CSx_START/STOP */
43#define START_REG(start) ((start) >> 16)
44#define STOP_REG(start, size) (((start) + (size) - 1) >> 16)
45
46/*
47 * Set up GOT: Global Offset Table
48 *
Joakim Tjernlund3fbaa4d2010-01-19 14:41:56 +010049 * Use r12 to access the GOT
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +020050 */
51 START_GOT
52 GOT_ENTRY(_GOT2_TABLE_)
53 GOT_ENTRY(_FIXUP_TABLE_)
54
55 GOT_ENTRY(_start)
56 GOT_ENTRY(_start_of_vectors)
57 GOT_ENTRY(_end_of_vectors)
58 GOT_ENTRY(transfer_to_handler)
59
60 GOT_ENTRY(__init_end)
Simon Glassed70c8f2013-03-14 06:54:53 +000061 GOT_ENTRY(__bss_end)
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +020062 GOT_ENTRY(__bss_start)
63 END_GOT
64
65/*
66 * Magic number and version string
67 */
68 .long 0x27051956 /* U-Boot Magic Number */
69 .globl version_string
70version_string:
Andreas Bießmann61d01952011-07-18 20:24:04 +020071 .ascii U_BOOT_VERSION_STRING, "\0"
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +020072
73/*
74 * Vector Table
75 */
76 .text
77 . = EXC_OFF_SYS_RESET
78
79 .globl _start
80 /* Start from here after reset/power on */
81_start:
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +020082 b boot_cold
83
84 .globl _start_of_vectors
85_start_of_vectors:
86
87/* Machine check */
88 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
89
90/* Data Storage exception. */
91 STD_EXCEPTION(0x300, DataStorage, UnknownException)
92
93/* Instruction Storage exception. */
94 STD_EXCEPTION(0x400, InstStorage, UnknownException)
95
96/* External Interrupt exception. */
97 STD_EXCEPTION(0x500, ExtInterrupt, UnknownException)
98
99/* Alignment exception. */
100 . = 0x600
101Alignment:
102 EXCEPTION_PROLOG(SRR0, SRR1)
103 mfspr r4,DAR
104 stw r4,_DAR(r21)
105 mfspr r5,DSISR
106 stw r5,_DSISR(r21)
107 addi r3,r1,STACK_FRAME_OVERHEAD
Joakim Tjernlund4ff6bc02010-01-19 14:41:55 +0100108 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200109
110/* Program check exception */
111 . = 0x700
112ProgramCheck:
113 EXCEPTION_PROLOG(SRR0, SRR1)
114 addi r3,r1,STACK_FRAME_OVERHEAD
Joakim Tjernlund4ff6bc02010-01-19 14:41:55 +0100115 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
116 MSR_KERNEL, COPY_EE)
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200117
118/* Floating Point Unit unavailable exception */
119 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
120
121/* Decrementer */
122 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
123
124/* Critical interrupt */
125 STD_EXCEPTION(0xa00, Critical, UnknownException)
126
127/* System Call */
128 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
129
130/* Trace interrupt */
131 STD_EXCEPTION(0xd00, Trace, UnknownException)
132
133/* Performance Monitor interrupt */
134 STD_EXCEPTION(0xf00, PerfMon, UnknownException)
135
136/* Intruction Translation Miss */
137 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
138
139/* Data Load Translation Miss */
140 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
141
142/* Data Store Translation Miss */
143 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
144
145/* Instruction Address Breakpoint */
146 STD_EXCEPTION(0x1300, InstructionAddrBreakpoint, DebugException)
147
148/* System Management interrupt */
149 STD_EXCEPTION(0x1400, SystemMgmtInterrupt, UnknownException)
150
151 .globl _end_of_vectors
152_end_of_vectors:
153
154 . = 0x3000
155boot_cold:
156 /* Save msr contents */
157 mfmsr r5
158
159 /* Set IMMR area to our preferred location */
160 lis r4, CONFIG_DEFAULT_IMMR@h
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200161 lis r3, CONFIG_SYS_IMMR@h
162 ori r3, r3, CONFIG_SYS_IMMR@l
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200163 stw r3, IMMRBAR(r4)
164 mtspr MBAR, r3 /* IMMRBAR is mirrored into the MBAR SPR (311) */
165
166 /* Initialise the machine */
167 bl cpu_early_init
168
169 /*
170 * Set up Local Access Windows:
171 *
172 * 1) Boot/CS0 (boot FLASH)
173 * 2) On-chip SRAM (initial stack purposes)
174 */
175
176 /* Boot CS/CS0 window range */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200177 lis r3, CONFIG_SYS_IMMR@h
178 ori r3, r3, CONFIG_SYS_IMMR@l
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200179
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200180 lis r4, START_REG(CONFIG_SYS_FLASH_BASE)
181 ori r4, r4, STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE)
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200182 stw r4, LPCS0AW(r3)
183
184 /*
185 * The SRAM window has a fixed size (256K), so only the start address
186 * is necessary
187 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200188 lis r4, START_REG(CONFIG_SYS_SRAM_BASE) & 0xff00
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200189 stw r4, SRAMBAR(r3)
190
Wolfgang Denk530181f2007-08-02 21:27:46 +0200191 /*
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200192 * According to MPC5121e RM, configuring local access windows should
Wolfgang Denk530181f2007-08-02 21:27:46 +0200193 * be followed by a dummy read of the config register that was
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200194 * modified last and an isync
Wolfgang Denk530181f2007-08-02 21:27:46 +0200195 */
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200196 lwz r4, SRAMBAR(r3)
197 isync
198
199 /*
200 * Set configuration of the Boot/CS0, the SRAM window does not have a
201 * config register so no params can be set for it
202 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200203 lis r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@h
204 ori r3, r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@l
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200205
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200206 lis r4, CONFIG_SYS_CS0_CFG@h
207 ori r4, r4, CONFIG_SYS_CS0_CFG@l
Wolfgang Denk530181f2007-08-02 21:27:46 +0200208 stw r4, CS0_CONFIG(r3)
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200209
210 /* Master enable all CS's */
211 lis r4, CS_CTRL_ME@h
212 ori r4, r4, CS_CTRL_ME@l
213 stw r4, CS_CTRL(r3)
214
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200215 lis r4, (CONFIG_SYS_MONITOR_BASE)@h
216 ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200217 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
218 mtlr r5
219 blr
220
221in_flash:
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200222 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
223 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200224
225 li r0, 0 /* Make room for stack frame header and */
226 stwu r0, -4(r1) /* clear final stack frame so that */
227 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
228
229 /* let the C-code set up the rest */
230 /* */
231 /* Be careful to keep code relocatable & stack humble */
232 /*------------------------------------------------------*/
233
234 GET_GOT /* initialize GOT access */
Wolfgang Denkb2d36ea2011-04-20 22:11:21 +0200235
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200236 /* r3: IMMR */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200237 lis r3, CONFIG_SYS_IMMR@h
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200238 /* run low-level CPU init code (in Flash) */
239 bl cpu_init_f
240
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200241 /* run 1st part of board init code (in Flash) */
242 bl board_init_f
243
244 /* NOTREACHED - board_init_f() does not return */
245
246/*
247 * This code finishes saving the registers to the exception frame
248 * and jumps to the appropriate handler for the exception.
249 * Register r21 is pointer into trap frame, r1 has new stack pointer.
250 */
251 .globl transfer_to_handler
252transfer_to_handler:
253 stw r22,_NIP(r21)
254 lis r22,MSR_POW@h
255 andc r23,r23,r22
256 stw r23,_MSR(r21)
257 SAVE_GPR(7, r21)
258 SAVE_4GPRS(8, r21)
259 SAVE_8GPRS(12, r21)
260 SAVE_8GPRS(24, r21)
261 mflr r23
262 andi. r24,r23,0x3f00 /* get vector offset */
263 stw r24,TRAP(r21)
264 li r22,0
265 stw r22,RESULT(r21)
266 lwz r24,0(r23) /* virtual address of handler */
267 lwz r23,4(r23) /* where to go when done */
268 mtspr SRR0,r24
269 mtspr SRR1,r20
270 mtlr r23
271 SYNC
272 rfi /* jump to handler, enable MMU */
273
274int_return:
275 mfmsr r28 /* Disable interrupts */
276 li r4,0
277 ori r4,r4,MSR_EE
278 andc r28,r28,r4
279 SYNC /* Some chip revs need this... */
280 mtmsr r28
281 SYNC
282 lwz r2,_CTR(r1)
283 lwz r0,_LINK(r1)
284 mtctr r2
285 mtlr r0
286 lwz r2,_XER(r1)
287 lwz r0,_CCR(r1)
288 mtspr XER,r2
289 mtcrf 0xFF,r0
290 REST_10GPRS(3, r1)
291 REST_10GPRS(13, r1)
292 REST_8GPRS(23, r1)
293 REST_GPR(31, r1)
294 lwz r2,_NIP(r1) /* Restore environment */
295 lwz r0,_MSR(r1)
296 mtspr SRR0,r2
297 mtspr SRR1,r0
298 lwz r0,GPR0(r1)
299 lwz r2,GPR2(r1)
300 lwz r1,GPR1(r1)
301 SYNC
302 rfi
303
304/*
305 * This code initialises the machine, it expects original MSR contents to be in r5.
306 */
307cpu_early_init:
308 /* Initialize machine status; enable machine check interrupt */
309 /*-----------------------------------------------------------*/
310
311 li r3, MSR_KERNEL /* Set ME and RI flags */
312 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit */
313#ifdef DEBUG
314 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE, BE bits */
315#endif
316 mtmsr r3
317 SYNC
318 mtspr SRR1, r3 /* Mirror current MSR state in SRR1 */
319
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200320 lis r3, CONFIG_SYS_IMMR@h
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200321
322#if defined(CONFIG_WATCHDOG)
323 /* Initialise the watchdog and reset it */
324 /*--------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200325 lis r4, CONFIG_SYS_WATCHDOG_VALUE
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200326 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
327 stw r4, SWCRR(r3)
328
329 /* reset */
330 li r4, 0x556C
331 sth r4, SWSRR@l(r3)
332 li r4, 0x0
333 ori r4, r4, 0xAA39
334 sth r4, SWSRR@l(r3)
335#else
336 /* Disable the watchdog */
337 /*----------------------*/
338 lwz r4, SWCRR(r3)
339 /*
340 * Check to see if it's enabled for disabling: once disabled by s/w
341 * it's not possible to re-enable it
342 */
343 andi. r4, r4, 0x4
344 beq 1f
345 xor r4, r4, r4
346 stw r4, SWCRR(r3)
3471:
348#endif /* CONFIG_WATCHDOG */
349
350 /* Initialize the Hardware Implementation-dependent Registers */
351 /* HID0 also contains cache control */
352 /*------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200353 lis r3, CONFIG_SYS_HID0_INIT@h
354 ori r3, r3, CONFIG_SYS_HID0_INIT@l
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200355 SYNC
356 mtspr HID0, r3
357
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200358 lis r3, CONFIG_SYS_HID0_FINAL@h
359 ori r3, r3, CONFIG_SYS_HID0_FINAL@l
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200360 SYNC
361 mtspr HID0, r3
362
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200363 lis r3, CONFIG_SYS_HID2@h
364 ori r3, r3, CONFIG_SYS_HID2@l
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200365 SYNC
366 mtspr HID2, r3
367 sync
368 blr
369
370
371/* Cache functions.
372 *
373 * Note: requires that all cache bits in
374 * HID0 are in the low half word.
375 */
376 .globl icache_enable
377icache_enable:
378 mfspr r3, HID0
379 ori r3, r3, HID0_ICE
380 lis r4, 0
381 ori r4, r4, HID0_ILOCK
382 andc r3, r3, r4
383 ori r4, r3, HID0_ICFI
384 isync
385 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
386 isync
387 mtspr HID0, r3 /* clears invalidate */
388 blr
389
390 .globl icache_disable
391icache_disable:
392 mfspr r3, HID0
393 lis r4, 0
394 ori r4, r4, HID0_ICE|HID0_ILOCK
395 andc r3, r3, r4
396 ori r4, r3, HID0_ICFI
397 isync
398 mtspr HID0, r4 /* sets invalidate, clears enable and lock*/
399 isync
400 mtspr HID0, r3 /* clears invalidate */
401 blr
402
403 .globl icache_status
404icache_status:
405 mfspr r3, HID0
406 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
407 blr
408
409 .globl dcache_enable
410dcache_enable:
411 mfspr r3, HID0
412 li r5, HID0_DCFI|HID0_DLOCK
413 andc r3, r3, r5
414 mtspr HID0, r3 /* no invalidate, unlock */
415 ori r3, r3, HID0_DCE
416 ori r5, r3, HID0_DCFI
417 mtspr HID0, r5 /* enable + invalidate */
418 mtspr HID0, r3 /* enable */
419 sync
420 blr
421
422 .globl dcache_disable
423dcache_disable:
424 mfspr r3, HID0
425 lis r4, 0
426 ori r4, r4, HID0_DCE|HID0_DLOCK
427 andc r3, r3, r4
428 ori r4, r3, HID0_DCI
429 sync
430 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
431 sync
432 mtspr HID0, r3 /* clears invalidate */
433 blr
434
435 .globl dcache_status
436dcache_status:
437 mfspr r3, HID0
438 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
439 blr
440
441 .globl get_pvr
442get_pvr:
443 mfspr r3, PVR
444 blr
445
Sriram Dash3afb1ec2016-10-14 12:03:50 +0530446 .globl get_svr
447get_svr:
448 mfspr r3, SVR
449 blr
450
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200451/*-------------------------------------------------------------------*/
452
453/*
454 * void relocate_code (addr_sp, gd, addr_moni)
455 *
456 * This "function" does not return, instead it continues in RAM
457 * after relocating the monitor code.
458 *
459 * r3 = dest
460 * r4 = src
461 * r5 = length in bytes
462 * r6 = cachelinesize
463 */
464 .globl relocate_code
465relocate_code:
466 mr r1, r3 /* Set new stack pointer */
467 mr r9, r4 /* Save copy of Global Data pointer */
468 mr r10, r5 /* Save copy of Destination Address */
469
Joakim Tjernlund3fbaa4d2010-01-19 14:41:56 +0100470 GET_GOT
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200471 mr r3, r5 /* Destination Address */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200472 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
473 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200474 lwz r5, GOT(__init_end)
475 sub r5, r5, r4
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200476 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200477
478 /*
479 * Fix GOT pointer:
480 *
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200481 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200482 * + Destination Address
483 *
484 * Offset:
485 */
486 sub r15, r10, r4
487
488 /* First our own GOT */
Joakim Tjernlund3fbaa4d2010-01-19 14:41:56 +0100489 add r12, r12, r15
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200490 /* then the one used by the C code */
491 add r30, r30, r15
492
493 /*
494 * Now relocate code
495 */
496 cmplw cr1,r3,r4
497 addi r0,r5,3
498 srwi. r0,r0,2
499 beq cr1,4f /* In place copy is not necessary */
500 beq 7f /* Protect against 0 count */
501 mtctr r0
502 bge cr1,2f
503 la r8,-4(r4)
504 la r7,-4(r3)
505
506 /* copy */
5071: lwzu r0,4(r8)
508 stwu r0,4(r7)
509 bdnz 1b
510
511 addi r0,r5,3
512 srwi. r0,r0,2
513 mtctr r0
514 la r8,-4(r4)
515 la r7,-4(r3)
516
517 /* and compare */
51820: lwzu r20,4(r8)
519 lwzu r21,4(r7)
520 xor. r22, r20, r21
521 bne 30f
522 bdnz 20b
523 b 4f
524
525 /* compare failed */
52630: li r3, 0
527 blr
528
5292: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
530 add r8,r4,r0
531 add r7,r3,r0
5323: lwzu r0,-4(r8)
533 stwu r0,-4(r7)
534 bdnz 3b
535
536/*
537 * Now flush the cache: note that we must start from a cache aligned
538 * address. Otherwise we might miss one cache line.
539 */
5404: cmpwi r6,0
541 add r5,r3,r5
542 beq 7f /* Always flush prefetch queue in any case */
543 subi r0,r6,1
544 andc r3,r3,r0
545 mr r4,r3
5465: dcbst 0,r4
547 add r4,r4,r6
548 cmplw r4,r5
549 blt 5b
550 sync /* Wait for all dcbst to complete on bus */
551 mr r4,r3
5526: icbi 0,r4
553 add r4,r4,r6
554 cmplw r4,r5
555 blt 6b
5567: sync /* Wait for all icbi to complete on bus */
557 isync
558
559/*
560 * We are done. Do not return, instead branch to second part of board
561 * initialization, now running from RAM.
562 */
563 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
564 mtlr r0
565 blr
566
567in_ram:
568 /*
Joakim Tjernlund3fbaa4d2010-01-19 14:41:56 +0100569 * Relocation Function, r12 point to got2+0x8000
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200570 *
571 * Adjust got2 pointers, no need to check for 0, this code
572 * already puts a few entries in the table.
573 */
574 li r0,__got2_entries@sectoff@l
575 la r3,GOT(_GOT2_TABLE_)
576 lwz r11,GOT(_GOT2_TABLE_)
577 mtctr r0
578 sub r11,r3,r11
579 addi r3,r3,-4
5801: lwzu r0,4(r3)
Joakim Tjernlund4f2fdac2009-10-08 02:03:51 +0200581 cmpwi r0,0
582 beq- 2f
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200583 add r0,r0,r11
584 stw r0,0(r3)
Joakim Tjernlund4f2fdac2009-10-08 02:03:51 +02005852: bdnz 1b
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200586
587 /*
588 * Now adjust the fixups and the pointers to the fixups
589 * in case we need to move ourselves again.
590 */
Joakim Tjernlund4f2fdac2009-10-08 02:03:51 +0200591 li r0,__fixup_entries@sectoff@l
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200592 lwz r3,GOT(_FIXUP_TABLE_)
593 cmpwi r0,0
594 mtctr r0
595 addi r3,r3,-4
596 beq 4f
5973: lwzu r4,4(r3)
598 lwzux r0,r4,r11
Joakim Tjernlundc61b25a2010-10-14 11:51:44 +0200599 cmpwi r0,0
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200600 add r0,r0,r11
Joakim Tjernlund401b5922010-11-04 19:02:00 +0100601 stw r4,0(r3)
Joakim Tjernlundc61b25a2010-10-14 11:51:44 +0200602 beq- 5f
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200603 stw r0,0(r4)
Joakim Tjernlundc61b25a2010-10-14 11:51:44 +02006045: bdnz 3b
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +02006054:
606clear_bss:
607 /*
608 * Now clear BSS segment
609 */
610 lwz r3,GOT(__bss_start)
Simon Glassed70c8f2013-03-14 06:54:53 +0000611 lwz r4,GOT(__bss_end)
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200612
613 cmplw 0, r3, r4
614 beq 6f
615
616 li r0, 0
6175:
618 stw r0, 0(r3)
619 addi r3, r3, 4
620 cmplw 0, r3, r4
621 bne 5b
6226:
623 mr r3, r9 /* Global Data pointer */
624 mr r4, r10 /* Destination Address */
625 bl board_init_r
626
627 /*
628 * Copy exception vector code to low memory
629 *
630 * r3: dest_addr
631 * r7: source address, r8: end address, r9: target address
632 */
633 .globl trap_init
634trap_init:
Joakim Tjernlund3fbaa4d2010-01-19 14:41:56 +0100635 mflr r4 /* save link register */
636 GET_GOT
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200637 lwz r7, GOT(_start)
638 lwz r8, GOT(_end_of_vectors)
639
640 li r9, 0x100 /* reset vector at 0x100 */
641
642 cmplw 0, r7, r8
643 bgelr /* return if r7>=r8 - just in case */
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +02006441:
645 lwz r0, 0(r7)
646 stw r0, 0(r9)
647 addi r7, r7, 4
648 addi r9, r9, 4
649 cmplw 0, r7, r8
650 bne 1b
651
652 /*
653 * relocate `hdlr' and `int_return' entries
654 */
655 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
656 li r8, Alignment - _start + EXC_OFF_SYS_RESET
6572:
658 bl trap_reloc
659 addi r7, r7, 0x100 /* next exception vector */
660 cmplw 0, r7, r8
661 blt 2b
662
663 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
664 bl trap_reloc
665
666 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
667 bl trap_reloc
668
669 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
670 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
6713:
672 bl trap_reloc
673 addi r7, r7, 0x100 /* next exception vector */
674 cmplw 0, r7, r8
675 blt 3b
676
677 li r7, .L_Trace - _start + EXC_OFF_SYS_RESET
678 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
6794:
680 bl trap_reloc
681 addi r7, r7, 0x100 /* next exception vector */
682 cmplw 0, r7, r8
683 blt 4b
684
685 mfmsr r3 /* now that the vectors have */
686 lis r7, MSR_IP@h /* relocated into low memory */
687 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
688 andc r3, r3, r7 /* (if it was on) */
689 SYNC /* Some chip revs need this... */
690 mtmsr r3
691 SYNC
692
693 mtlr r4 /* restore link register */
694 blr