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git01.mediatek.com / filogic / uboot / a27d9f692c841082240479c59dfbe9541bb7fe56 / . / arch / arm / dts / am335x-boneblack.dts
blob: e2ee8b8c07bc5ebe41791e39fccf4daab3e1e579 [file] [log] [blame]
Paul Barkera27d9f62021-07-12 21:14:09 +0100[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0-only
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]2/*
Paul Barkera27d9f62021-07-12 21:14:09 +0100[diff] [blame^]3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]4 */
5/dts-v1/;
6
7#include "am33xx.dtsi"
8#include "am335x-bone-common.dtsi"
Paul Barkera27d9f62021-07-12 21:14:09 +0100[diff] [blame^]9#include "am335x-boneblack-common.dtsi"
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]10
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]11/ {
12 model = "TI AM335x BeagleBone Black";
13 compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]14};
15
Paul Barkera27d9f62021-07-12 21:14:09 +0100[diff] [blame^]16&cpu0_opp_table {
17 /*
18 * All PG 2.0 silicon may not support 1GHz but some of the early
19 * BeagleBone Blacks have PG 2.0 silicon which is guaranteed
20 * to support 1GHz OPP so enable it for PG 2.0 on this board.
21 */
22 oppnitro-1000000000 {
23 opp-supported-hw = <0x06 0x0100>;
24 };
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]25};
26
Paul Barkera27d9f62021-07-12 21:14:09 +0100[diff] [blame^]27&gpio0 {
28 gpio-line-names =
29 "[mdio_data]",
30 "[mdio_clk]",
31 "P9_22 [spi0_sclk]",
32 "P9_21 [spi0_d0]",
33 "P9_18 [spi0_d1]",
34 "P9_17 [spi0_cs0]",
35 "[mmc0_cd]",
36 "P8_42A [ecappwm0]",
37 "P8_35 [lcd d12]",
38 "P8_33 [lcd d13]",
39 "P8_31 [lcd d14]",
40 "P8_32 [lcd d15]",
41 "P9_20 [i2c2_sda]",
42 "P9_19 [i2c2_scl]",
43 "P9_26 [uart1_rxd]",
44 "P9_24 [uart1_txd]",
45 "[rmii1_txd3]",
46 "[rmii1_txd2]",
47 "[usb0_drvvbus]",
48 "[hdmi cec]",
49 "P9_41B",
50 "[rmii1_txd1]",
51 "P8_19 [ehrpwm2a]",
52 "P8_13 [ehrpwm2b]",
53 "NC",
54 "NC",
55 "P8_14",
56 "P8_17",
57 "[rmii1_txd0]",
58 "[rmii1_refclk]",
59 "P9_11 [uart4_rxd]",
60 "P9_13 [uart4_txd]";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]61};
62
Paul Barkera27d9f62021-07-12 21:14:09 +0100[diff] [blame^]63&gpio1 {
64 gpio-line-names =
65 "P8_25 [mmc1_dat0]",
66 "[mmc1_dat1]",
67 "P8_5 [mmc1_dat2]",
68 "P8_6 [mmc1_dat3]",
69 "P8_23 [mmc1_dat4]",
70 "P8_22 [mmc1_dat5]",
71 "P8_3 [mmc1_dat6]",
72 "P8_4 [mmc1_dat7]",
73 "NC",
74 "NC",
75 "NC",
76 "NC",
77 "P8_12",
78 "P8_11",
79 "P8_16",
80 "P8_15",
81 "P9_15A",
82 "P9_23",
83 "P9_14 [ehrpwm1a]",
84 "P9_16 [ehrpwm1b]",
85 "[emmc rst]",
86 "[usr0 led]",
87 "[usr1 led]",
88 "[usr2 led]",
89 "[usr3 led]",
90 "[hdmi irq]",
91 "[usb vbus oc]",
92 "[hdmi audio]",
93 "P9_12",
94 "P8_26",
95 "P8_21 [emmc]",
96 "P8_20 [emmc]";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]97};
98
Paul Barkera27d9f62021-07-12 21:14:09 +0100[diff] [blame^]99&gpio2 {
100 gpio-line-names =
101 "P9_15B",
102 "P8_18",
103 "P8_7",
104 "P8_8",
105 "P8_10",
106 "P8_9",
107 "P8_45 [hdmi]",
108 "P8_46 [hdmi]",
109 "P8_43 [hdmi]",
110 "P8_44 [hdmi]",
111 "P8_41 [hdmi]",
112 "P8_42 [hdmi]",
113 "P8_39 [hdmi]",
114 "P8_40 [hdmi]",
115 "P8_37 [hdmi]",
116 "P8_38 [hdmi]",
117 "P8_36 [hdmi]",
118 "P8_34 [hdmi]",
119 "[rmii1_rxd3]",
120 "[rmii1_rxd2]",
121 "[rmii1_rxd1]",
122 "[rmii1_rxd0]",
123 "P8_27 [hdmi]",
124 "P8_29 [hdmi]",
125 "P8_28 [hdmi]",
126 "P8_30 [hdmi]",
127 "[mmc0_dat3]",
128 "[mmc0_dat2]",
129 "[mmc0_dat1]",
130 "[mmc0_dat0]",
131 "[mmc0_clk]",
132 "[mmc0_cmd]";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]133};
134
Paul Barkera27d9f62021-07-12 21:14:09 +0100[diff] [blame^]135&gpio3 {
136 gpio-line-names =
137 "[mii col]",
138 "[mii crs]",
139 "[mii rx err]",
140 "[mii tx en]",
141 "[mii rx dv]",
142 "[i2c0 sda]",
143 "[i2c0 scl]",
144 "[jtag emu0]",
145 "[jtag emu1]",
146 "[mii tx clk]",
147 "[mii rx clk]",
148 "NC",
149 "NC",
150 "[usb vbus en]",
151 "P9_31 [spi1_sclk]",
152 "P9_29 [spi1_d0]",
153 "P9_30 [spi1_d1]",
154 "P9_28 [spi1_cs0]",
155 "P9_42B [ecappwm0]",
156 "P9_27",
157 "P9_41A",
158 "P9_25",
159 "NC",
160 "NC",
161 "NC",
162 "NC",
163 "NC",
164 "NC",
165 "NC",
166 "NC",
167 "NC",
168 "NC";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]169};