Bin Meng | a27264c | 2019-07-10 23:43:12 -0700 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Bin Meng | 055700e | 2018-09-26 06:55:14 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2015 Regents of the University of California |
| 4 | * |
| 5 | * Taken from Linux arch/riscv/include/asm/csr.h |
| 6 | */ |
| 7 | |
| 8 | #ifndef _ASM_RISCV_CSR_H |
| 9 | #define _ASM_RISCV_CSR_H |
| 10 | |
Bin Meng | a27264c | 2019-07-10 23:43:12 -0700 | [diff] [blame^] | 11 | #include <asm/asm.h> |
Baruch Siach | 401885a | 2018-11-11 12:31:01 +0200 | [diff] [blame] | 12 | #include <linux/const.h> |
| 13 | |
Bin Meng | 055700e | 2018-09-26 06:55:14 -0700 | [diff] [blame] | 14 | /* Status register flags */ |
| 15 | #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ |
| 16 | #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ |
| 17 | #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ |
Bin Meng | a27264c | 2019-07-10 23:43:12 -0700 | [diff] [blame^] | 18 | #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ |
Bin Meng | 055700e | 2018-09-26 06:55:14 -0700 | [diff] [blame] | 19 | |
| 20 | #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ |
| 21 | #define SR_FS_OFF _AC(0x00000000, UL) |
| 22 | #define SR_FS_INITIAL _AC(0x00002000, UL) |
| 23 | #define SR_FS_CLEAN _AC(0x00004000, UL) |
| 24 | #define SR_FS_DIRTY _AC(0x00006000, UL) |
| 25 | |
| 26 | #define SR_XS _AC(0x00018000, UL) /* Extension Status */ |
| 27 | #define SR_XS_OFF _AC(0x00000000, UL) |
| 28 | #define SR_XS_INITIAL _AC(0x00008000, UL) |
| 29 | #define SR_XS_CLEAN _AC(0x00010000, UL) |
| 30 | #define SR_XS_DIRTY _AC(0x00018000, UL) |
| 31 | |
| 32 | #ifndef CONFIG_64BIT |
| 33 | #define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ |
| 34 | #else |
| 35 | #define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ |
| 36 | #endif |
| 37 | |
| 38 | /* SATP flags */ |
Bin Meng | a27264c | 2019-07-10 23:43:12 -0700 | [diff] [blame^] | 39 | #ifndef CONFIG_64BIT |
Bin Meng | 055700e | 2018-09-26 06:55:14 -0700 | [diff] [blame] | 40 | #define SATP_PPN _AC(0x003FFFFF, UL) |
| 41 | #define SATP_MODE_32 _AC(0x80000000, UL) |
| 42 | #define SATP_MODE SATP_MODE_32 |
| 43 | #else |
| 44 | #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) |
| 45 | #define SATP_MODE_39 _AC(0x8000000000000000, UL) |
| 46 | #define SATP_MODE SATP_MODE_39 |
| 47 | #endif |
| 48 | |
Bin Meng | a27264c | 2019-07-10 23:43:12 -0700 | [diff] [blame^] | 49 | /* SCAUSE */ |
| 50 | #define SCAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) |
| 51 | |
| 52 | #define IRQ_U_SOFT 0 |
| 53 | #define IRQ_S_SOFT 1 |
| 54 | #define IRQ_M_SOFT 3 |
| 55 | #define IRQ_U_TIMER 4 |
| 56 | #define IRQ_S_TIMER 5 |
| 57 | #define IRQ_M_TIMER 7 |
| 58 | #define IRQ_U_EXT 8 |
| 59 | #define IRQ_S_EXT 9 |
| 60 | #define IRQ_M_EXT 11 |
Bin Meng | 055700e | 2018-09-26 06:55:14 -0700 | [diff] [blame] | 61 | |
| 62 | #define EXC_INST_MISALIGNED 0 |
| 63 | #define EXC_INST_ACCESS 1 |
| 64 | #define EXC_BREAKPOINT 3 |
| 65 | #define EXC_LOAD_ACCESS 5 |
| 66 | #define EXC_STORE_ACCESS 7 |
| 67 | #define EXC_SYSCALL 8 |
| 68 | #define EXC_INST_PAGE_FAULT 12 |
| 69 | #define EXC_LOAD_PAGE_FAULT 13 |
| 70 | #define EXC_STORE_PAGE_FAULT 15 |
| 71 | |
Bin Meng | a27264c | 2019-07-10 23:43:12 -0700 | [diff] [blame^] | 72 | /* SIE (Interrupt Enable) and SIP (Interrupt Pending) flags */ |
| 73 | #define MIE_MSIE (_AC(0x1, UL) << IRQ_M_SOFT) |
| 74 | #define SIE_SSIE (_AC(0x1, UL) << IRQ_S_SOFT) |
| 75 | #define SIE_STIE (_AC(0x1, UL) << IRQ_S_TIMER) |
| 76 | #define SIE_SEIE (_AC(0x1, UL) << IRQ_S_EXT) |
Bin Meng | 055700e | 2018-09-26 06:55:14 -0700 | [diff] [blame] | 77 | |
Bin Meng | a27264c | 2019-07-10 23:43:12 -0700 | [diff] [blame^] | 78 | #define CSR_CYCLE 0xc00 |
| 79 | #define CSR_TIME 0xc01 |
| 80 | #define CSR_INSTRET 0xc02 |
| 81 | #define CSR_SSTATUS 0x100 |
| 82 | #define CSR_SIE 0x104 |
| 83 | #define CSR_STVEC 0x105 |
| 84 | #define CSR_SCOUNTEREN 0x106 |
| 85 | #define CSR_SSCRATCH 0x140 |
| 86 | #define CSR_SEPC 0x141 |
| 87 | #define CSR_SCAUSE 0x142 |
| 88 | #define CSR_STVAL 0x143 |
| 89 | #define CSR_SIP 0x144 |
| 90 | #define CSR_SATP 0x180 |
| 91 | #define CSR_CYCLEH 0xc80 |
| 92 | #define CSR_TIMEH 0xc81 |
| 93 | #define CSR_INSTRETH 0xc82 |
| 94 | |
| 95 | #ifndef __ASSEMBLY__ |
Bin Meng | 9e9e6fe | 2018-12-12 06:12:39 -0800 | [diff] [blame] | 96 | |
Bin Meng | 055700e | 2018-09-26 06:55:14 -0700 | [diff] [blame] | 97 | #define csr_swap(csr, val) \ |
| 98 | ({ \ |
| 99 | unsigned long __v = (unsigned long)(val); \ |
Bin Meng | a27264c | 2019-07-10 23:43:12 -0700 | [diff] [blame^] | 100 | __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\ |
Bin Meng | 055700e | 2018-09-26 06:55:14 -0700 | [diff] [blame] | 101 | : "=r" (__v) : "rK" (__v) \ |
| 102 | : "memory"); \ |
| 103 | __v; \ |
| 104 | }) |
| 105 | |
| 106 | #define csr_read(csr) \ |
| 107 | ({ \ |
| 108 | register unsigned long __v; \ |
Bin Meng | a27264c | 2019-07-10 23:43:12 -0700 | [diff] [blame^] | 109 | __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \ |
Bin Meng | 055700e | 2018-09-26 06:55:14 -0700 | [diff] [blame] | 110 | : "=r" (__v) : \ |
| 111 | : "memory"); \ |
| 112 | __v; \ |
| 113 | }) |
| 114 | |
| 115 | #define csr_write(csr, val) \ |
| 116 | ({ \ |
| 117 | unsigned long __v = (unsigned long)(val); \ |
Bin Meng | a27264c | 2019-07-10 23:43:12 -0700 | [diff] [blame^] | 118 | __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \ |
Bin Meng | 055700e | 2018-09-26 06:55:14 -0700 | [diff] [blame] | 119 | : : "rK" (__v) \ |
| 120 | : "memory"); \ |
| 121 | }) |
| 122 | |
| 123 | #define csr_read_set(csr, val) \ |
| 124 | ({ \ |
| 125 | unsigned long __v = (unsigned long)(val); \ |
Bin Meng | a27264c | 2019-07-10 23:43:12 -0700 | [diff] [blame^] | 126 | __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\ |
Bin Meng | 055700e | 2018-09-26 06:55:14 -0700 | [diff] [blame] | 127 | : "=r" (__v) : "rK" (__v) \ |
| 128 | : "memory"); \ |
| 129 | __v; \ |
| 130 | }) |
| 131 | |
| 132 | #define csr_set(csr, val) \ |
| 133 | ({ \ |
| 134 | unsigned long __v = (unsigned long)(val); \ |
Bin Meng | a27264c | 2019-07-10 23:43:12 -0700 | [diff] [blame^] | 135 | __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \ |
Bin Meng | 055700e | 2018-09-26 06:55:14 -0700 | [diff] [blame] | 136 | : : "rK" (__v) \ |
| 137 | : "memory"); \ |
| 138 | }) |
| 139 | |
| 140 | #define csr_read_clear(csr, val) \ |
| 141 | ({ \ |
| 142 | unsigned long __v = (unsigned long)(val); \ |
Bin Meng | a27264c | 2019-07-10 23:43:12 -0700 | [diff] [blame^] | 143 | __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\ |
Bin Meng | 055700e | 2018-09-26 06:55:14 -0700 | [diff] [blame] | 144 | : "=r" (__v) : "rK" (__v) \ |
| 145 | : "memory"); \ |
| 146 | __v; \ |
| 147 | }) |
| 148 | |
| 149 | #define csr_clear(csr, val) \ |
| 150 | ({ \ |
| 151 | unsigned long __v = (unsigned long)(val); \ |
Bin Meng | a27264c | 2019-07-10 23:43:12 -0700 | [diff] [blame^] | 152 | __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \ |
Bin Meng | 055700e | 2018-09-26 06:55:14 -0700 | [diff] [blame] | 153 | : : "rK" (__v) \ |
| 154 | : "memory"); \ |
| 155 | }) |
| 156 | |
| 157 | #endif /* __ASSEMBLY__ */ |
| 158 | |
| 159 | #endif /* _ASM_RISCV_CSR_H */ |