Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / a2306577cbb7a7bc7f049730ec30ae6267e45301 / . / board / ronetix / pm9263 / lowlevel_init.S
blob: c048c9109606f60df57015d62c46f7870816a264 [file] [log] [blame]
Ilko Iliev8b954a92009-04-16 21:30:48 +0200[diff] [blame]1/*
2 * Memory Setup stuff - taken from blob memsetup.S
3 *
4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
5 * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
6 *
7 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
8 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#include <config.h>
30#include <version.h>
31#include <asm/arch/hardware.h>
32#include <asm/arch/at91_pmc.h>
33#include <asm/arch/at91_pio.h>
34#include <asm/arch/at91_rstc.h>
35#include <asm/arch/at91_wdt.h>
36#include <asm/arch/at91sam9_sdramc.h>
37#include <asm/arch/at91sam9_smc.h>
38#include <asm/arch/at91sam9263_matrix.h>
39
40_TEXT_BASE:
41 .word TEXT_BASE
42
43.globl lowlevel_init
44.type lowlevel_init,function
45lowlevel_init:
46
47 mov r5, pc /* r5 = POS1 + 4 current */
48POS1:
49 ldr r0, =POS1 /* r0 = POS1 compile */
50 ldr r2, _TEXT_BASE
51 sub r0, r0, r2 /* r0 = POS1-_TEXT_BASE (POS1 relative) */
52 sub r5, r5, r0 /* r0 = TEXT_BASE-1 */
53 sub r5, r5, #4 /* r1 = text base - current */
54
55 /* memory control configuration 1 */
56 ldr r0, =SMRDATA
57 ldr r2, =SMRDATA1
58 ldr r1, _TEXT_BASE
59 sub r0, r0, r1
60 sub r2, r2, r1
61 add r0, r0, r5
62 add r2, r2, r5
630:
64 /* the address */
65 ldr r1, [r0], #4
66 /* the value */
67 ldr r3, [r0], #4
68 str r3, [r1]
69 cmp r2, r0
70 bne 0b
71
72/* ----------------------------------------------------------------------------
73 * PMC Init Step 1.
74 * ----------------------------------------------------------------------------
75 * - Check if the PLL is already initialized
76 * ----------------------------------------------------------------------------
77 */
78 ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR)
79 ldr r0, [r1]
80 and r0, r0, #3
81 cmp r0, #0
82 bne PLL_setup_end
83
84/* ---------------------------------------------------------------------------
85 * - Enable the Main Oscillator
86 * ---------------------------------------------------------------------------
87 */
88 ldr r1, =(AT91_BASE_SYS + AT91_CKGR_MOR)
89 ldr r2, =(AT91_BASE_SYS + AT91_PMC_SR)
90 ldr r0, =0x0000FF01
91 str r0, [r1] /* Enable main oscillator, OSCOUNT = 0xFF */
92
93 /* Reading the PMC Status to detect when the Main Oscillator is enabled */
94 mov r4, #AT91_PMC_MOSCS
95MOSCS_Loop:
96 ldr r3, [r2]
97 and r3, r4, r3
98 cmp r3, #AT91_PMC_MOSCS
99 bne MOSCS_Loop
100
101/* ----------------------------------------------------------------------------
102 * PMC Init Step 2.
103 * ----------------------------------------------------------------------------
104 * Setup PLLA
105 * ----------------------------------------------------------------------------
106 */
107 ldr r1, =(AT91_BASE_SYS + AT91_CKGR_PLLAR)
108 ldr r0, =CONFIG_SYS_PLLAR_VAL
109 str r0, [r1]
110
111 /* Reading the PMC Status register to detect when the PLLA is locked */
112 mov r4, #AT91_PMC_LOCKA
113MOSCS_Loop1:
114 ldr r3, [r2]
115 and r3, r4, r3
116 cmp r3, #AT91_PMC_LOCKA
117 bne MOSCS_Loop1
118
119/* ----------------------------------------------------------------------------
120 * PMC Init Step 3.
121 * ----------------------------------------------------------------------------
122 * - Switch on the Main Oscillator 18.432 MHz
123 * ----------------------------------------------------------------------------
124 */
125 ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR)
126
127 /* -Master Clock Controller register PMC_MCKR */
128 ldr r0, =CONFIG_SYS_MCKR1_VAL
129 str r0, [r1]
130
131 /* Reading the PMC Status to detect when the Master clock is ready */
132 mov r4, #AT91_PMC_MCKRDY
133MCKRDY_Loop:
134 ldr r3, [r2]
135 and r3, r4, r3
136 cmp r3, #AT91_PMC_MCKRDY
137 bne MCKRDY_Loop
138
139 ldr r0, =CONFIG_SYS_MCKR2_VAL
140 str r0, [r1]
141
142 /* Reading the PMC Status to detect when the Master clock is ready */
143 mov r4, #AT91_PMC_MCKRDY
144MCKRDY_Loop1:
145 ldr r3, [r2]
146 and r3, r4, r3
147 cmp r3, #AT91_PMC_MCKRDY
148 bne MCKRDY_Loop1
149
150PLL_setup_end:
151
152/* ----------------------------------------------------------------------------
153 * - memory control configuration 2
154 * ----------------------------------------------------------------------------
155 */
156 ldr r0, =(AT91_BASE_SYS + AT91_SDRAMC_TR)
157 ldr r1, [r0]
158 cmp r1, #0
159 bne SDRAM_setup_end
160
161 ldr r0, =SMRDATA1
162 ldr r2, =SMRDATA2
163 ldr r1, _TEXT_BASE
164 sub r0, r0, r1
165 sub r2, r2, r1
166 add r0, r0, r5
167 add r2, r2, r5
168
1692:
170 /* the address */
171 ldr r1, [r0], #4
172 /* the value */
173 ldr r3, [r0], #4
174 str r3, [r1]
175 cmp r2, r0
176 bne 2b
177
178SDRAM_setup_end:
179 /* everything is fine now */
180 mov pc, lr
181
182 .ltorg
183
184SMRDATA:
185 .word (AT91_BASE_SYS + AT91_WDT_MR)
186 .word CONFIG_SYS_WDTC_WDMR_VAL
187
188 .word (AT91_BASE_SYS + AT91_PIOD + PIO_PDR)
189 .word CONFIG_SYS_PIOD_PDR_VAL1
190 .word (AT91_BASE_SYS + AT91_PIOD + PIO_PUDR)
191 .word CONFIG_SYS_PIOD_PPUDR_VAL
192 .word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR)
193 .word CONFIG_SYS_PIOD_PPUDR_VAL
194
195 .word (AT91_BASE_SYS + AT91_MATRIX_EBI0CSA)
196 .word CONFIG_SYS_MATRIX_EBI0CSA_VAL
197 .word (AT91_BASE_SYS + AT91_MATRIX_EBI1CSA)
198 .word CONFIG_SYS_MATRIX_EBI1CSA_VAL
199
200 /* flash */
201 .word (AT91_BASE_SYS + AT91_SMC_MODE(0))
202 .word CONFIG_SYS_SMC0_CTRL0_VAL
203
204 .word (AT91_BASE_SYS + AT91_SMC_CYCLE(0))
205 .word CONFIG_SYS_SMC0_CYCLE0_VAL
206
207 .word (AT91_BASE_SYS + AT91_SMC_PULSE(0))
208 .word CONFIG_SYS_SMC0_PULSE0_VAL
209
210 .word (AT91_BASE_SYS + AT91_SMC_SETUP(0))
211 .word CONFIG_SYS_SMC0_SETUP0_VAL
212
213 /* PSRAM */
214 .word (AT91_BASE_SYS + AT91_SMC1_MODE(0))
215 .word CONFIG_SYS_SMC1_CTRL0_VAL
216
217 .word (AT91_BASE_SYS + AT91_SMC1_CYCLE(0))
218 .word CONFIG_SYS_SMC1_CYCLE0_VAL
219
220 .word (AT91_BASE_SYS + AT91_SMC1_PULSE(0))
221 .word CONFIG_SYS_SMC1_PULSE0_VAL
222
223 .word (AT91_BASE_SYS + AT91_SMC1_SETUP(0))
224 .word CONFIG_SYS_SMC1_SETUP0_VAL
225
226SMRDATA1:
227 .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
228 .word CONFIG_SYS_SDRC_MR_VAL1
229 .word (AT91_BASE_SYS + AT91_SDRAMC_TR)
230 .word CONFIG_SYS_SDRC_TR_VAL1
231 .word (AT91_BASE_SYS + AT91_SDRAMC_CR)
232 .word CONFIG_SYS_SDRC_CR_VAL
233 .word (AT91_BASE_SYS + AT91_SDRAMC_MDR)
234 .word CONFIG_SYS_SDRC_MDR_VAL
235 .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
236 .word CONFIG_SYS_SDRC_MR_VAL2
237 .word AT91_SDRAM_BASE
238 .word CONFIG_SYS_SDRAM_VAL1
239 .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
240 .word CONFIG_SYS_SDRC_MR_VAL3
241 .word AT91_SDRAM_BASE
242 .word CONFIG_SYS_SDRAM_VAL2
243 .word AT91_SDRAM_BASE
244 .word CONFIG_SYS_SDRAM_VAL3
245 .word AT91_SDRAM_BASE
246 .word CONFIG_SYS_SDRAM_VAL4
247 .word AT91_SDRAM_BASE
248 .word CONFIG_SYS_SDRAM_VAL5
249 .word AT91_SDRAM_BASE
250 .word CONFIG_SYS_SDRAM_VAL6
251 .word AT91_SDRAM_BASE
252 .word CONFIG_SYS_SDRAM_VAL7
253 .word AT91_SDRAM_BASE
254 .word CONFIG_SYS_SDRAM_VAL8
255 .word AT91_SDRAM_BASE
256 .word CONFIG_SYS_SDRAM_VAL9
257 .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
258 .word CONFIG_SYS_SDRC_MR_VAL4
259 .word AT91_SDRAM_BASE
260 .word CONFIG_SYS_SDRAM_VAL10
261 .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
262 .word CONFIG_SYS_SDRC_MR_VAL5
263 .word AT91_SDRAM_BASE
264 .word CONFIG_SYS_SDRAM_VAL11
265 .word (AT91_BASE_SYS + AT91_SDRAMC_TR)
266 .word CONFIG_SYS_SDRC_TR_VAL2
267 .word AT91_SDRAM_BASE
268 .word CONFIG_SYS_SDRAM_VAL12
269 /* User reset enable*/
270 .word (AT91_BASE_SYS + AT91_RSTC_MR)
271 .word CONFIG_SYS_RSTC_RMR_VAL
272#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
273 /* MATRIX_MCFG - REMAP all masters */
274 .word (AT91_BASE_SYS + AT91_MATRIX_MCFG0)
275 .word 0x1FF
276#endif
277
278SMRDATA2:
279 .word 0