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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk5b845b62002-08-21 21:57:24 +00002/*
wdenk9b7f3842003-10-09 20:09:04 +00003 * (C) Copyright 2003
4 * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
5 *
wdenk5b845b62002-08-21 21:57:24 +00006 * (C) Copyright 2002
7 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
wdenk5b845b62002-08-21 21:57:24 +00008 */
9
10/*
wdenk5b845b62002-08-21 21:57:24 +000011 * Altera FPGA support
12 */
13#include <common.h>
Marek Vasutb9d4df32014-09-16 20:33:54 +020014#include <errno.h>
wdenk9b7f3842003-10-09 20:09:04 +000015#include <ACEX1K.h>
eran liberty4c373a92008-03-27 00:50:49 +010016#include <stratixII.h>
wdenk5b845b62002-08-21 21:57:24 +000017
Marek Vasut9e3a8442014-09-16 20:21:42 +020018/* Define FPGA_DEBUG to 1 to get debug printf's */
19#define FPGA_DEBUG 0
wdenk5b845b62002-08-21 21:57:24 +000020
Marek Vasutf5d25e42014-09-16 21:17:51 +020021static const struct altera_fpga {
22 enum altera_family family;
23 const char *name;
24 int (*load)(Altera_desc *, const void *, size_t);
25 int (*dump)(Altera_desc *, const void *, size_t);
26 int (*info)(Altera_desc *);
27} altera_fpga[] = {
28#if defined(CONFIG_FPGA_ACEX1K)
29 { Altera_ACEX1K, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info },
30 { Altera_CYC2, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info },
31#elif defined(CONFIG_FPGA_CYCLON2)
32 { Altera_ACEX1K, "CycloneII", CYC2_load, CYC2_dump, CYC2_info },
33 { Altera_CYC2, "CycloneII", CYC2_load, CYC2_dump, CYC2_info },
34#endif
35#if defined(CONFIG_FPGA_STRATIX_II)
36 { Altera_StratixII, "StratixII", StratixII_load,
37 StratixII_dump, StratixII_info },
38#endif
Stefan Roesed919d722016-02-12 13:48:02 +010039#if defined(CONFIG_FPGA_STRATIX_V)
40 { Altera_StratixV, "StratixV", stratixv_load, NULL, NULL },
41#endif
Ang, Chee Hongff14f162018-12-19 18:35:15 -080042#if defined(CONFIG_FPGA_STRATIX10)
43 { Intel_FPGA_Stratix10, "Stratix10", stratix10_load, NULL, NULL },
44#endif
Pavel Machekc7213802014-09-08 14:08:45 +020045#if defined(CONFIG_FPGA_SOCFPGA)
46 { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL },
47#endif
Marek Vasutf5d25e42014-09-16 21:17:51 +020048};
49
Marek Vasutff4072c2014-09-16 20:32:51 +020050static int altera_validate(Altera_desc *desc, const char *fn)
51{
52 if (!desc) {
53 printf("%s: NULL descriptor!\n", fn);
Marek Vasutb9d4df32014-09-16 20:33:54 +020054 return -EINVAL;
Marek Vasutff4072c2014-09-16 20:32:51 +020055 }
56
57 if ((desc->family < min_altera_type) ||
58 (desc->family > max_altera_type)) {
59 printf("%s: Invalid family type, %d\n", fn, desc->family);
Marek Vasutb9d4df32014-09-16 20:33:54 +020060 return -EINVAL;
Marek Vasutff4072c2014-09-16 20:32:51 +020061 }
62
63 if ((desc->iface < min_altera_iface_type) ||
64 (desc->iface > max_altera_iface_type)) {
65 printf("%s: Invalid Interface type, %d\n", fn, desc->iface);
Marek Vasutb9d4df32014-09-16 20:33:54 +020066 return -EINVAL;
Marek Vasutff4072c2014-09-16 20:32:51 +020067 }
68
69 if (!desc->size) {
70 printf("%s: NULL part size\n", fn);
Marek Vasutb9d4df32014-09-16 20:33:54 +020071 return -EINVAL;
Marek Vasutff4072c2014-09-16 20:32:51 +020072 }
73
Marek Vasutb9d4df32014-09-16 20:33:54 +020074 return 0;
Marek Vasutff4072c2014-09-16 20:32:51 +020075}
wdenk9b7f3842003-10-09 20:09:04 +000076
Marek Vasutf5d25e42014-09-16 21:17:51 +020077static const struct altera_fpga *
78altera_desc_to_fpga(Altera_desc *desc, const char *fn)
wdenk5b845b62002-08-21 21:57:24 +000079{
Marek Vasutf5d25e42014-09-16 21:17:51 +020080 int i;
wdenk9b7f3842003-10-09 20:09:04 +000081
Marek Vasutf5d25e42014-09-16 21:17:51 +020082 if (altera_validate(desc, fn)) {
83 printf("%s: Invalid device descriptor\n", fn);
84 return NULL;
Marek Vasut18221352014-09-16 20:29:24 +020085 }
86
Marek Vasutf5d25e42014-09-16 21:17:51 +020087 for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) {
88 if (desc->family == altera_fpga[i].family)
89 break;
90 }
wdenk9b7f3842003-10-09 20:09:04 +000091
Marek Vasutf5d25e42014-09-16 21:17:51 +020092 if (i == ARRAY_SIZE(altera_fpga)) {
93 printf("%s: Unsupported family type, %d\n", fn, desc->family);
94 return NULL;
wdenk9b7f3842003-10-09 20:09:04 +000095 }
96
Marek Vasutf5d25e42014-09-16 21:17:51 +020097 return &altera_fpga[i];
wdenk5b845b62002-08-21 21:57:24 +000098}
99
Marek Vasutf5d25e42014-09-16 21:17:51 +0200100int altera_load(Altera_desc *desc, const void *buf, size_t bsize)
wdenk5b845b62002-08-21 21:57:24 +0000101{
Marek Vasutf5d25e42014-09-16 21:17:51 +0200102 const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
wdenk9b7f3842003-10-09 20:09:04 +0000103
Marek Vasutf5d25e42014-09-16 21:17:51 +0200104 if (!fpga)
Marek Vasut18221352014-09-16 20:29:24 +0200105 return FPGA_FAIL;
Marek Vasut18221352014-09-16 20:29:24 +0200106
Marek Vasutf5d25e42014-09-16 21:17:51 +0200107 debug_cond(FPGA_DEBUG, "%s: Launching the %s Loader...\n",
108 __func__, fpga->name);
109 if (fpga->load)
110 return fpga->load(desc, buf, bsize);
111 return 0;
112}
wdenk9b7f3842003-10-09 20:09:04 +0000113
Marek Vasutf5d25e42014-09-16 21:17:51 +0200114int altera_dump(Altera_desc *desc, const void *buf, size_t bsize)
115{
116 const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
wdenk9b7f3842003-10-09 20:09:04 +0000117
Marek Vasutf5d25e42014-09-16 21:17:51 +0200118 if (!fpga)
119 return FPGA_FAIL;
120
121 debug_cond(FPGA_DEBUG, "%s: Launching the %s Reader...\n",
122 __func__, fpga->name);
123 if (fpga->dump)
124 return fpga->dump(desc, buf, bsize);
125 return 0;
wdenk5b845b62002-08-21 21:57:24 +0000126}
127
Marek Vasut18221352014-09-16 20:29:24 +0200128int altera_info(Altera_desc *desc)
wdenk5b845b62002-08-21 21:57:24 +0000129{
Marek Vasutf5d25e42014-09-16 21:17:51 +0200130 const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
wdenk9b7f3842003-10-09 20:09:04 +0000131
Marek Vasutf5d25e42014-09-16 21:17:51 +0200132 if (!fpga)
Marek Vasut18221352014-09-16 20:29:24 +0200133 return FPGA_FAIL;
wdenk9b7f3842003-10-09 20:09:04 +0000134
Marek Vasutf5d25e42014-09-16 21:17:51 +0200135 printf("Family: \t%s\n", fpga->name);
wdenk9b7f3842003-10-09 20:09:04 +0000136
Marek Vasut18221352014-09-16 20:29:24 +0200137 printf("Interface type:\t");
138 switch (desc->iface) {
139 case passive_serial:
140 printf("Passive Serial (PS)\n");
141 break;
142 case passive_parallel_synchronous:
143 printf("Passive Parallel Synchronous (PPS)\n");
144 break;
145 case passive_parallel_asynchronous:
146 printf("Passive Parallel Asynchronous (PPA)\n");
147 break;
148 case passive_serial_asynchronous:
149 printf("Passive Serial Asynchronous (PSA)\n");
150 break;
151 case altera_jtag_mode: /* Not used */
152 printf("JTAG Mode\n");
153 break;
154 case fast_passive_parallel:
155 printf("Fast Passive Parallel (FPP)\n");
156 break;
157 case fast_passive_parallel_security:
158 printf("Fast Passive Parallel with Security (FPPS)\n");
159 break;
Ang, Chee Hongff14f162018-12-19 18:35:15 -0800160 case secure_device_manager_mailbox:
161 puts("Secure Device Manager (SDM) Mailbox\n");
162 break;
Marek Vasut18221352014-09-16 20:29:24 +0200163 /* Add new interface types here */
164 default:
165 printf("Unsupported interface type, %d\n", desc->iface);
166 }
167
168 printf("Device Size: \t%zd bytes\n"
169 "Cookie: \t0x%x (%d)\n",
170 desc->size, desc->cookie, desc->cookie);
wdenk9b7f3842003-10-09 20:09:04 +0000171
Marek Vasut18221352014-09-16 20:29:24 +0200172 if (desc->iface_fns) {
173 printf("Device Function Table @ 0x%p\n", desc->iface_fns);
Marek Vasutf5d25e42014-09-16 21:17:51 +0200174 if (fpga->info)
175 fpga->info(desc);
wdenk9b7f3842003-10-09 20:09:04 +0000176 } else {
Marek Vasut18221352014-09-16 20:29:24 +0200177 printf("No Device Function Table.\n");
wdenk9b7f3842003-10-09 20:09:04 +0000178 }
179
Marek Vasutf5d25e42014-09-16 21:17:51 +0200180 return FPGA_SUCCESS;
wdenk9b7f3842003-10-09 20:09:04 +0000181}