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Kever Yang162cebd2019-07-01 11:49:10 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019 Rockchip Electronics Co., Ltd
4 */
5
Jagan Tekib22da752020-01-10 00:16:21 +05306#include "rockchip-u-boot.dtsi"
Simon Glass6a50cd12020-07-19 13:56:12 -06007#include "rockchip-optee.dtsi"
Jagan Tekib22da752020-01-10 00:16:21 +05308
Kever Yange5f3c6e2019-07-09 21:58:54 +08009/ {
Johan Jonker8ba3d4062022-04-15 23:21:39 +020010 aliases {
11 gpio0 = &gpio0;
12 gpio1 = &gpio1;
13 gpio2 = &gpio2;
14 gpio3 = &gpio3;
15 gpio4 = &gpio4;
16 gpio5 = &gpio5;
17 gpio6 = &gpio6;
18 gpio7 = &gpio7;
19 gpio8 = &gpio8;
20 mmc0 = &emmc;
21 mmc1 = &sdmmc;
22 mmc2 = &sdio0;
23 mmc3 = &sdio1;
24 };
25
Kever Yange5f3c6e2019-07-09 21:58:54 +080026 chosen {
27 u-boot,spl-boot-order = \
28 "same-as-spl", &emmc, &sdmmc;
29 };
Johan Jonker8ba3d4062022-04-15 23:21:39 +020030
31 dmc: dmc@ff610000 {
32 compatible = "rockchip,rk3288-dmc", "syscon";
33 reg = <0xff610000 0x3fc
34 0xff620000 0x294
35 0xff630000 0x3fc
36 0xff640000 0x294>;
37 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
38 <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
39 <&cru ARMCLK>;
40 clock-names = "pclk_ddrupctl0", "pclk_publ0",
41 "pclk_ddrupctl1", "pclk_publ1",
42 "arm_clk";
43 rockchip,cru = <&cru>;
44 rockchip,grf = <&grf>;
45 rockchip,noc = <&noc>;
46 rockchip,pmu = <&pmu>;
47 rockchip,sgrf = <&sgrf>;
48 rockchip,sram = <&ddr_sram>;
49 u-boot,dm-pre-reloc;
50 };
51
52 noc: syscon@ffac0000 {
53 compatible = "rockchip,rk3288-noc", "syscon";
54 reg = <0xffac0000 0x2000>;
55 u-boot,dm-pre-reloc;
56 };
Kever Yange5f3c6e2019-07-09 21:58:54 +080057};
58
Simon Glass88315f72020-07-19 13:55:57 -060059#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
60&binman {
61 rom {
62 filename = "u-boot.rom";
63 size = <0x400000>;
64 pad-byte = <0xff>;
65
66 mkimage {
67 args = "-n rk3288 -T rkspi";
68 u-boot-spl {
69 };
70 };
71 u-boot-img {
72 offset = <0x20000>;
73 };
74 u-boot {
75 offset = <0x300000>;
76 };
77 fdtmap {
78 };
79 };
80};
81#endif
82
Johan Jonker8ba3d4062022-04-15 23:21:39 +020083&bus_intmem {
84 ddr_sram: ddr-sram@1000 {
85 compatible = "rockchip,rk3288-ddr-sram";
86 reg = <0x1000 0x4000>;
87 };
Kever Yang162cebd2019-07-01 11:49:10 +080088};
89
Johan Jonker8ba3d4062022-04-15 23:21:39 +020090&cru {
Kever Yang162cebd2019-07-01 11:49:10 +080091 u-boot,dm-pre-reloc;
92};
93
Johan Jonker8ba3d4062022-04-15 23:21:39 +020094&gpio7 {
Kever Yang162cebd2019-07-01 11:49:10 +080095 u-boot,dm-pre-reloc;
96};
97
Johan Jonker8ba3d4062022-04-15 23:21:39 +020098&grf {
Kever Yang162cebd2019-07-01 11:49:10 +080099 u-boot,dm-pre-reloc;
100};
101
Johan Jonker8ba3d4062022-04-15 23:21:39 +0200102&pmu {
Kever Yang162cebd2019-07-01 11:49:10 +0800103 u-boot,dm-pre-reloc;
104};
105
Johan Jonker8ba3d4062022-04-15 23:21:39 +0200106&sgrf {
Kever Yang162cebd2019-07-01 11:49:10 +0800107 u-boot,dm-pre-reloc;
108};
109
Johan Jonker8ba3d4062022-04-15 23:21:39 +0200110&uart0 {
111 clock-frequency = <24000000>;
112};
113
114&uart1 {
115 clock-frequency = <24000000>;
Kever Yang162cebd2019-07-01 11:49:10 +0800116};
117
Johan Jonker8ba3d4062022-04-15 23:21:39 +0200118&uart2 {
119 clock-frequency = <24000000>;
120};
121
122&uart3 {
123 clock-frequency = <24000000>;
124};
125
126&vopb {
Kever Yang162cebd2019-07-01 11:49:10 +0800127 u-boot,dm-pre-reloc;
128};
Walter Lozano6dc8d7e2020-06-25 01:10:15 -0300129
Johan Jonker8ba3d4062022-04-15 23:21:39 +0200130&vopl {
Walter Lozano6dc8d7e2020-06-25 01:10:15 -0300131 u-boot,dm-pre-reloc;
132};