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git01.mediatek.com / filogic / uboot / a1fe6aae7540ea1bab9fc984319b5930206507d8 / . / drivers / usb / host / ehci-exynos.c
blob: 9f0ed06a85343e282ed43d44339b1d4078d35477 [file] [log] [blame]
Rajeshwari Shinde9b4ae502012-05-02 19:18:51 +0530[diff] [blame]1/*
Rajeshwari Shindedad39d42012-05-21 16:38:03 +0530[diff] [blame]2 * SAMSUNG EXYNOS USB HOST EHCI Controller
Rajeshwari Shinde9b4ae502012-05-02 19:18:51 +0530[diff] [blame]3 *
4 * Copyright (C) 2012 Samsung Electronics Co.Ltd
5 * Vivek Gautam <gautam.vivek@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 * MA 02110-1301 USA
21 */
22
23#include <common.h>
24#include <usb.h>
25#include <asm/arch/cpu.h>
Rajeshwari Shindedad39d42012-05-21 16:38:03 +0530[diff] [blame]26#include <asm/arch/ehci.h>
Rajeshwari Shinde84448072012-05-14 05:52:02 +0000[diff] [blame]27#include <asm/arch/system.h>
Rajeshwari Shinde21965ac2012-05-14 05:52:03 +0000[diff] [blame]28#include <asm/arch/power.h>
Rajeshwari Shinde9b4ae502012-05-02 19:18:51 +0530[diff] [blame]29#include "ehci.h"
Rajeshwari Shinde9b4ae502012-05-02 19:18:51 +0530[diff] [blame]30
31/* Setup the EHCI host controller. */
Rajeshwari Shindedad39d42012-05-21 16:38:03 +0530[diff] [blame]32static void setup_usb_phy(struct exynos_usb_phy *usb)
Rajeshwari Shinde9b4ae502012-05-02 19:18:51 +0530[diff] [blame]33{
Rajeshwari Shinde84448072012-05-14 05:52:02 +0000[diff] [blame]34 set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
35
Rajeshwari Shinde21965ac2012-05-14 05:52:03 +0000[diff] [blame]36 set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
37
Rajeshwari Shinde9b4ae502012-05-02 19:18:51 +0530[diff] [blame]38 clrbits_le32(&usb->usbphyctrl0,
39 HOST_CTRL0_FSEL_MASK |
40 HOST_CTRL0_COMMONON_N |
41 /* HOST Phy setting */
42 HOST_CTRL0_PHYSWRST |
43 HOST_CTRL0_PHYSWRSTALL |
44 HOST_CTRL0_SIDDQ |
45 HOST_CTRL0_FORCESUSPEND |
46 HOST_CTRL0_FORCESLEEP);
47
48 setbits_le32(&usb->usbphyctrl0,
49 /* Setting up the ref freq */
50 (CLK_24MHZ << 16) |
51 /* HOST Phy setting */
52 HOST_CTRL0_LINKSWRST |
53 HOST_CTRL0_UTMISWRST);
54 udelay(10);
55 clrbits_le32(&usb->usbphyctrl0,
56 HOST_CTRL0_LINKSWRST |
57 HOST_CTRL0_UTMISWRST);
58 udelay(20);
59
60 /* EHCI Ctrl setting */
61 setbits_le32(&usb->ehcictrl,
62 EHCICTRL_ENAINCRXALIGN |
63 EHCICTRL_ENAINCR4 |
64 EHCICTRL_ENAINCR8 |
65 EHCICTRL_ENAINCR16);
66}
67
68/* Reset the EHCI host controller. */
Rajeshwari Shindedad39d42012-05-21 16:38:03 +0530[diff] [blame]69static void reset_usb_phy(struct exynos_usb_phy *usb)
Rajeshwari Shinde9b4ae502012-05-02 19:18:51 +0530[diff] [blame]70{
71 /* HOST_PHY reset */
72 setbits_le32(&usb->usbphyctrl0,
73 HOST_CTRL0_PHYSWRST |
74 HOST_CTRL0_PHYSWRSTALL |
75 HOST_CTRL0_SIDDQ |
76 HOST_CTRL0_FORCESUSPEND |
77 HOST_CTRL0_FORCESLEEP);
Rajeshwari Shinde21965ac2012-05-14 05:52:03 +0000[diff] [blame]78
79 set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE);
Rajeshwari Shinde9b4ae502012-05-02 19:18:51 +0530[diff] [blame]80}
81
82/*
83 * EHCI-initialization
84 * Create the appropriate control structures to manage
85 * a new EHCI host controller.
86 */
Lucas Stach3494a4c2012-09-26 00:14:35 +0200[diff] [blame]87int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
Rajeshwari Shinde9b4ae502012-05-02 19:18:51 +0530[diff] [blame]88{
Rajeshwari Shindedad39d42012-05-21 16:38:03 +0530[diff] [blame]89 struct exynos_usb_phy *usb;
Rajeshwari Shinde9b4ae502012-05-02 19:18:51 +0530[diff] [blame]90
Rajeshwari Shindedad39d42012-05-21 16:38:03 +0530[diff] [blame]91 usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
Rajeshwari Shinde9b4ae502012-05-02 19:18:51 +0530[diff] [blame]92 setup_usb_phy(usb);
93
Lucas Stach3494a4c2012-09-26 00:14:35 +0200[diff] [blame]94 *hccr = (struct ehci_hccr *)samsung_get_base_usb_ehci();
95 *hcor = (struct ehci_hcor *)((uint32_t) *hccr
96 + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
Rajeshwari Shinde9b4ae502012-05-02 19:18:51 +0530[diff] [blame]97
98 debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n",
Lucas Stach3494a4c2012-09-26 00:14:35 +0200[diff] [blame]99 (uint32_t)*hccr, (uint32_t)*hcor,
100 (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
Rajeshwari Shinde9b4ae502012-05-02 19:18:51 +0530[diff] [blame]101
102 return 0;
103}
104
105/*
106 * Destroy the appropriate control structures corresponding
107 * the EHCI host controller.
108 */
Lucas Stach3494a4c2012-09-26 00:14:35 +0200[diff] [blame]109int ehci_hcd_stop(int index)
Rajeshwari Shinde9b4ae502012-05-02 19:18:51 +0530[diff] [blame]110{
Rajeshwari Shindedad39d42012-05-21 16:38:03 +0530[diff] [blame]111 struct exynos_usb_phy *usb;
Rajeshwari Shinde9b4ae502012-05-02 19:18:51 +0530[diff] [blame]112
Rajeshwari Shindedad39d42012-05-21 16:38:03 +0530[diff] [blame]113 usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
Rajeshwari Shinde9b4ae502012-05-02 19:18:51 +0530[diff] [blame]114 reset_usb_phy(usb);
115
116 return 0;
117}