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git01.mediatek.com / filogic / uboot / a1fe6aae7540ea1bab9fc984319b5930206507d8 / . / board / renesas / sh7757lcr / lowlevel_init.S
blob: 5090fd093c47b802f0eb7437463d20e4e108e07a [file] [log] [blame]
Yoshihiro Shimodaa7d382c2011-02-02 10:05:36 +0900[diff] [blame]1/*
2 * Copyright (C) 2011 Renesas Solutions Corp.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 */
19
20#include <config.h>
21#include <version.h>
22#include <asm/processor.h>
23#include <asm/macro.h>
24
25.macro or32, addr, data
26 mov.l \addr, r1
27 mov.l \data, r0
28 mov.l @r1, r2
29 or r2, r0
30 mov.l r0, @r1
31.endm
32
33.macro wait_DBCMD
34 mov.l DBWAIT_A, r0
35 mov.l @r0, r1
36.endm
37
38 .global lowlevel_init
39 .section .spiboot1.text
40 .align 2
41
42lowlevel_init:
43
44 /*------- GPIO -------*/
45 write8 PGDR_A, PGDR_D /* eMMC power off */
46
47 write16 PACR_A, PACR_D
48 write16 PBCR_A, PBCR_D
49 write16 PCCR_A, PCCR_D
50 write16 PDCR_A, PDCR_D
51 write16 PECR_A, PECR_D
52 write16 PFCR_A, PFCR_D
53 write16 PGCR_A, PGCR_D
54 write16 PHCR_A, PHCR_D
55 write16 PICR_A, PICR_D
56 write16 PJCR_A, PJCR_D
57 write16 PKCR_A, PKCR_D
58 write16 PLCR_A, PLCR_D
59 write16 PMCR_A, PMCR_D
60 write16 PNCR_A, PNCR_D
61 write16 POCR_A, POCR_D
62 write16 PQCR_A, PQCR_D
63 write16 PRCR_A, PRCR_D
64 write16 PSCR_A, PSCR_D
65 write16 PTCR_A, PTCR_D
66 write16 PUCR_A, PUCR_D
67 write16 PVCR_A, PVCR_D
68 write16 PWCR_A, PWCR_D
69 write16 PXCR_A, PXCR_D
70 write16 PYCR_A, PYCR_D
71 write16 PZCR_A, PZCR_D
72 write16 PSEL0_A, PSEL0_D
73 write16 PSEL1_A, PSEL1_D
74 write16 PSEL2_A, PSEL2_D
75 write16 PSEL3_A, PSEL3_D
76 write16 PSEL4_A, PSEL4_D
77 write16 PSEL5_A, PSEL5_D
78 write16 PSEL6_A, PSEL6_D
79 write16 PSEL7_A, PSEL7_D
80 write16 PSEL8_A, PSEL8_D
81
82 bra exit_gpio
83 nop
84
85 .align 4
86
87/*------- GPIO -------*/
88PGDR_A: .long 0xffec0040
89PACR_A: .long 0xffec0000
90PBCR_A: .long 0xffec0002
91PCCR_A: .long 0xffec0004
92PDCR_A: .long 0xffec0006
93PECR_A: .long 0xffec0008
94PFCR_A: .long 0xffec000a
95PGCR_A: .long 0xffec000c
96PHCR_A: .long 0xffec000e
97PICR_A: .long 0xffec0010
98PJCR_A: .long 0xffec0012
99PKCR_A: .long 0xffec0014
100PLCR_A: .long 0xffec0016
101PMCR_A: .long 0xffec0018
102PNCR_A: .long 0xffec001a
103POCR_A: .long 0xffec001c
104PQCR_A: .long 0xffec0020
105PRCR_A: .long 0xffec0022
106PSCR_A: .long 0xffec0024
107PTCR_A: .long 0xffec0026
108PUCR_A: .long 0xffec0028
109PVCR_A: .long 0xffec002a
110PWCR_A: .long 0xffec002c
111PXCR_A: .long 0xffec002e
112PYCR_A: .long 0xffec0030
113PZCR_A: .long 0xffec0032
114PSEL0_A: .long 0xffec0070
115PSEL1_A: .long 0xffec0072
116PSEL2_A: .long 0xffec0074
117PSEL3_A: .long 0xffec0076
118PSEL4_A: .long 0xffec0078
119PSEL5_A: .long 0xffec007a
120PSEL6_A: .long 0xffec007c
121PSEL7_A: .long 0xffec0082
122PSEL8_A: .long 0xffec0084
123
124PGDR_D: .long 0x80
125PACR_D: .long 0x0000
126PBCR_D: .long 0x0001
127PCCR_D: .long 0x0000
128PDCR_D: .long 0x0000
129PECR_D: .long 0x0000
130PFCR_D: .long 0x0000
131PGCR_D: .long 0x0000
132PHCR_D: .long 0x0000
133PICR_D: .long 0x0000
134PJCR_D: .long 0x0000
135PKCR_D: .long 0x0003
136PLCR_D: .long 0x0000
137PMCR_D: .long 0x0000
138PNCR_D: .long 0x0000
139POCR_D: .long 0x0000
140PQCR_D: .long 0xc000
141PRCR_D: .long 0x0000
142PSCR_D: .long 0x0000
143PTCR_D: .long 0x0000
144#if defined(CONFIG_SH7757_OFFSET_SPI)
145PUCR_D: .long 0x0055
146#else
147PUCR_D: .long 0x0000
148#endif
149PVCR_D: .long 0x0000
150PWCR_D: .long 0x0000
151PXCR_D: .long 0x0000
152PYCR_D: .long 0x0000
153PZCR_D: .long 0x0000
154PSEL0_D: .long 0xfe00
155PSEL1_D: .long 0x0000
156PSEL2_D: .long 0x3000
157PSEL3_D: .long 0xff00
158PSEL4_D: .long 0x771f
159PSEL5_D: .long 0x0ffc
160PSEL6_D: .long 0x00ff
161PSEL7_D: .long 0xfc00
162PSEL8_D: .long 0x0000
163
164 .align 2
165
166exit_gpio:
167 mov #0, r14
168 mova 2f, r0
169 mov.l PC_MASK, r1
170 tst r0, r1
171 bf 2f
172
173 bra exit_pmb
174 nop
175
176 .align 2
177
178/* If CPU runs on SDRAM, PC is 0x8???????. */
179PC_MASK: .long 0x20000000
180
1812:
182 mov #1, r14
183
184 mov.l EXPEVT_A, r0
185 mov.l @r0, r0
186 mov.l EXPEVT_POWER_ON_RESET, r1
187 cmp/eq r0, r1
188 bt 1f
189
190 /*
191 * If EXPEVT value is manual reset or tlb multipul-hit,
192 * initialization of DDR3IF is not necessary.
193 */
194 bra exit_ddr
195 nop
196
1971:
198 /* For Core Reset */
199 mov.l DBACEN_A, r0
200 mov.l @r0, r0
201 cmp/eq #0, r0
202 bt 3f
203
204 /*
205 * If DBACEN == 1(DBSC was already enabled), we have to avoid the
206 * initialization of DDR3-SDRAM.
207 */
208 bra exit_ddr
209 nop
210
2113:
212 /*------- DDR3IF -------*/
213 /* oscillation stabilization time */
214 wait_timer WAIT_OSC_TIME
215
216 /* step 3 */
217 write32 DBCMD_A, DBCMD_RSTL_VAL
218 wait_timer WAIT_30US
219
220 /* step 4 */
221 write32 DBCMD_A, DBCMD_PDEN_VAL
222
223 /* step 5 */
224 write32 DBKIND_A, DBKIND_D
225
226 /* step 6 */
227 write32 DBCONF_A, DBCONF_D
228 write32 DBTR0_A, DBTR0_D
229 write32 DBTR1_A, DBTR1_D
230 write32 DBTR2_A, DBTR2_D
231 write32 DBTR3_A, DBTR3_D
232 write32 DBTR4_A, DBTR4_D
233 write32 DBTR5_A, DBTR5_D
234 write32 DBTR6_A, DBTR6_D
235 write32 DBTR7_A, DBTR7_D
236 write32 DBTR8_A, DBTR8_D
237 write32 DBTR9_A, DBTR9_D
238 write32 DBTR10_A, DBTR10_D
239 write32 DBTR11_A, DBTR11_D
240 write32 DBTR12_A, DBTR12_D
241 write32 DBTR13_A, DBTR13_D
242 write32 DBTR14_A, DBTR14_D
243 write32 DBTR15_A, DBTR15_D
244 write32 DBTR16_A, DBTR16_D
245 write32 DBTR17_A, DBTR17_D
246 write32 DBTR18_A, DBTR18_D
247 write32 DBTR19_A, DBTR19_D
248 write32 DBRNK0_A, DBRNK0_D
249
250 /* step 7 */
251 write32 DBPDCNT3_A, DBPDCNT3_D
252
253 /* step 8 */
254 write32 DBPDCNT1_A, DBPDCNT1_D
255 write32 DBPDCNT2_A, DBPDCNT2_D
256 write32 DBPDLCK_A, DBPDLCK_D
257 write32 DBPDRGA_A, DBPDRGA_D
258 write32 DBPDRGD_A, DBPDRGD_D
259
260 /* step 9 */
261 wait_timer WAIT_30US
262
263 /* step 10 */
264 write32 DBPDCNT0_A, DBPDCNT0_D
265
266 /* step 11 */
267 wait_timer WAIT_30US
268 wait_timer WAIT_30US
269
270 /* step 12 */
271 write32 DBCMD_A, DBCMD_WAIT_VAL
272 wait_DBCMD
273
274 /* step 13 */
275 write32 DBCMD_A, DBCMD_RSTH_VAL
276 wait_DBCMD
277
278 /* step 14 */
279 write32 DBCMD_A, DBCMD_WAIT_VAL
280 write32 DBCMD_A, DBCMD_WAIT_VAL
281 write32 DBCMD_A, DBCMD_WAIT_VAL
282 write32 DBCMD_A, DBCMD_WAIT_VAL
283
284 /* step 15 */
285 write32 DBCMD_A, DBCMD_PDXT_VAL
286
287 /* step 16 */
288 write32 DBCMD_A, DBCMD_MRS2_VAL
289
290 /* step 17 */
291 write32 DBCMD_A, DBCMD_MRS3_VAL
292
293 /* step 18 */
294 write32 DBCMD_A, DBCMD_MRS1_VAL
295
296 /* step 19 */
297 write32 DBCMD_A, DBCMD_MRS0_VAL
298
299 /* step 20 */
300 write32 DBCMD_A, DBCMD_ZQCL_VAL
301
302 write32 DBCMD_A, DBCMD_REF_VAL
303 write32 DBCMD_A, DBCMD_REF_VAL
304 wait_DBCMD
305
306 /* step 21 */
307 write32 DBADJ0_A, DBADJ0_D
308 write32 DBADJ1_A, DBADJ1_D
309 write32 DBADJ2_A, DBADJ2_D
310
311 /* step 22 */
312 write32 DBRFCNF0_A, DBRFCNF0_D
313 write32 DBRFCNF1_A, DBRFCNF1_D
314 write32 DBRFCNF2_A, DBRFCNF2_D
315
316 /* step 23 */
317 write32 DBCALCNF_A, DBCALCNF_D
318
319 /* step 24 */
320 write32 DBRFEN_A, DBRFEN_D
321 write32 DBCMD_A, DBCMD_SRXT_VAL
322
323 /* step 25 */
324 write32 DBACEN_A, DBACEN_D
325
326 /* step 26 */
327 wait_DBCMD
328
Nobuhiro Iwamatsu67395912011-10-31 13:16:02 +0900[diff] [blame]329#if defined(CONFIG_SH7757LCR_DDR_ECC)
Yoshihiro Shimodaa7d382c2011-02-02 10:05:36 +0900[diff] [blame]330 /* enable DDR-ECC */
331 write32 ECD_ECDEN_A, ECD_ECDEN_D
332 write32 ECD_INTSR_A, ECD_INTSR_D
333 write32 ECD_SPACER_A, ECD_SPACER_D
334 write32 ECD_MCR_A, ECD_MCR_D
Nobuhiro Iwamatsu67395912011-10-31 13:16:02 +0900[diff] [blame]335#endif
Yoshihiro Shimodaa7d382c2011-02-02 10:05:36 +0900[diff] [blame]336 bra exit_ddr
337 nop
338
339 .align 4
340
341EXPEVT_A: .long 0xff000024
342EXPEVT_POWER_ON_RESET: .long 0x00000000
343
344/*------- DDR3IF -------*/
345DBCMD_A: .long 0xfe800018
346DBKIND_A: .long 0xfe800020
347DBCONF_A: .long 0xfe800024
348DBTR0_A: .long 0xfe800040
349DBTR1_A: .long 0xfe800044
350DBTR2_A: .long 0xfe800048
351DBTR3_A: .long 0xfe800050
352DBTR4_A: .long 0xfe800054
353DBTR5_A: .long 0xfe800058
354DBTR6_A: .long 0xfe80005c
355DBTR7_A: .long 0xfe800060
356DBTR8_A: .long 0xfe800064
357DBTR9_A: .long 0xfe800068
358DBTR10_A: .long 0xfe80006c
359DBTR11_A: .long 0xfe800070
360DBTR12_A: .long 0xfe800074
361DBTR13_A: .long 0xfe800078
362DBTR14_A: .long 0xfe80007c
363DBTR15_A: .long 0xfe800080
364DBTR16_A: .long 0xfe800084
365DBTR17_A: .long 0xfe800088
366DBTR18_A: .long 0xfe80008c
367DBTR19_A: .long 0xfe800090
368DBRNK0_A: .long 0xfe800100
369DBPDCNT0_A: .long 0xfe800200
370DBPDCNT1_A: .long 0xfe800204
371DBPDCNT2_A: .long 0xfe800208
372DBPDCNT3_A: .long 0xfe80020c
373DBPDLCK_A: .long 0xfe800280
374DBPDRGA_A: .long 0xfe800290
375DBPDRGD_A: .long 0xfe8002a0
376DBADJ0_A: .long 0xfe8000c0
377DBADJ1_A: .long 0xfe8000c4
378DBADJ2_A: .long 0xfe8000c8
379DBRFCNF0_A: .long 0xfe8000e0
380DBRFCNF1_A: .long 0xfe8000e4
381DBRFCNF2_A: .long 0xfe8000e8
382DBCALCNF_A: .long 0xfe8000f4
383DBRFEN_A: .long 0xfe800014
384DBACEN_A: .long 0xfe800010
385DBWAIT_A: .long 0xfe80001c
386
387WAIT_OSC_TIME: .long 6000
388WAIT_30US: .long 13333
389
390DBCMD_RSTL_VAL: .long 0x20000000
391DBCMD_PDEN_VAL: .long 0x1000d73c
392DBCMD_WAIT_VAL: .long 0x0000d73c
393DBCMD_RSTH_VAL: .long 0x2100d73c
394DBCMD_PDXT_VAL: .long 0x110000c8
395DBCMD_MRS0_VAL: .long 0x28000930
396DBCMD_MRS1_VAL: .long 0x29000004
397DBCMD_MRS2_VAL: .long 0x2a000008
398DBCMD_MRS3_VAL: .long 0x2b000000
399DBCMD_ZQCL_VAL: .long 0x03000200
400DBCMD_REF_VAL: .long 0x0c000000
401DBCMD_SRXT_VAL: .long 0x19000000
402DBKIND_D: .long 0x00000007
403DBCONF_D: .long 0x0f030a01
404DBTR0_D: .long 0x00000007
405DBTR1_D: .long 0x00000006
406DBTR2_D: .long 0x00000000
407DBTR3_D: .long 0x00000007
408DBTR4_D: .long 0x00070007
409DBTR5_D: .long 0x0000001b
410DBTR6_D: .long 0x00000014
411DBTR7_D: .long 0x00000005
412DBTR8_D: .long 0x00000015
413DBTR9_D: .long 0x00000006
414DBTR10_D: .long 0x00000008
415DBTR11_D: .long 0x00000007
416DBTR12_D: .long 0x0000000e
417DBTR13_D: .long 0x00000056
418DBTR14_D: .long 0x00000006
419DBTR15_D: .long 0x00000004
420DBTR16_D: .long 0x00150002
421DBTR17_D: .long 0x000c0017
422DBTR18_D: .long 0x00000200
423DBTR19_D: .long 0x00000040
424DBRNK0_D: .long 0x00000001
425DBPDCNT0_D: .long 0x00000001
426DBPDCNT1_D: .long 0x00000001
427DBPDCNT2_D: .long 0x00000000
428DBPDCNT3_D: .long 0x00004010
429DBPDLCK_D: .long 0x0000a55a
430DBPDRGA_D: .long 0x00000028
431DBPDRGD_D: .long 0x00017100
432
433DBADJ0_D: .long 0x00000000
434DBADJ1_D: .long 0x00000000
435DBADJ2_D: .long 0x18061806
436DBRFCNF0_D: .long 0x000001ff
437DBRFCNF1_D: .long 0x08001000
438DBRFCNF2_D: .long 0x00000000
439DBCALCNF_D: .long 0x0000ffff
440DBRFEN_D: .long 0x00000001
441DBACEN_D: .long 0x00000001
442
443/*------- DDR-ECC -------*/
444ECD_ECDEN_A: .long 0xffc1012c
445ECD_ECDEN_D: .long 0x00000001
446ECD_INTSR_A: .long 0xfe900024
447ECD_INTSR_D: .long 0xffffffff
448ECD_SPACER_A: .long 0xfe900018
449ECD_SPACER_D: .long SH7757LCR_SDRAM_ECC_SETTING
450ECD_MCR_A: .long 0xfe900010
451ECD_MCR_D: .long 0x00000001
452
453 .align 2
454exit_ddr:
455
456#if defined(CONFIG_SH_32BIT)
457 /*------- set PMB -------*/
458 write32 PASCR_A, PASCR_29BIT_D
459 write32 MMUCR_A, MMUCR_D
460
461 /*****************************************************************
462 * ent virt phys v sz c wt
463 * 0 0xa0000000 0x00000000 1 128M 0 1
464 * 1 0xa8000000 0x48000000 1 128M 0 1
465 * 5 0x88000000 0x48000000 1 128M 1 1
466 */
467 write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D
468 write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D
469 write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
470 write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
471 write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
472 write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
473
474 write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D
475 write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D
476 write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D
477 write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D
478 write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D
479 write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D
480 write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D
481 write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D
482 write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D
483 write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D
484 write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D
485 write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D
486 write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D
487
488 write32 PASCR_A, PASCR_INIT
489 mov.l DUMMY_ADDR, r0
490 icbi @r0
491#endif /* if defined(CONFIG_SH_32BIT) */
492
493exit_pmb:
494 /* CPU is running on ILRAM? */
495 mov r14, r0
496 tst #1, r0
497 bt 1f
498
499 mov.l _bss_start, r15
500 mov.l _spiboot_main, r0
501100: bsrf r0
502 nop
503
504 .align 2
505_spiboot_main: .long (spiboot_main - (100b + 4))
506_bss_start: .long bss_start
507
5081:
509
510 write32 CCR_A, CCR_D
511
512 rts
513 nop
514
515 .align 4
516
517#if defined(CONFIG_SH_32BIT)
518/*------- set PMB -------*/
519PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0)
520PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1)
521PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5)
522PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2)
523PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3)
524PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4)
525PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6)
526PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7)
527PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8)
528PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9)
529PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10)
530PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11)
531PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12)
532PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13)
533PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14)
534PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15)
535
536PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0)
537PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
538PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
539PMB_ADDR_NOT_USE_D: .long 0x00000000
540
541PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0)
542PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1)
543PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5)
544
545/* ppn ub v s1 s0 c wt */
546PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
547PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
548PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
549
550PASCR_A: .long 0xff000070
551DUMMY_ADDR: .long 0xa0000000
552PASCR_29BIT_D: .long 0x00000000
553PASCR_INIT: .long 0x80000080
554MMUCR_A: .long 0xff000010
555MMUCR_D: .long 0x00000004 /* clear ITLB */
556#endif /* CONFIG_SH_32BIT */
557
558CCR_A: .long CCR
559CCR_D: .long CCR_CACHE_INIT