Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 1 | /* |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 2 | * Copyright 2008-2012 Freescale Semiconductor, Inc. |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or |
| 5 | * modify it under the terms of the GNU General Public License |
| 6 | * Version 2 as published by the Free Software Foundation. |
| 7 | */ |
| 8 | |
| 9 | #include <common.h> |
| 10 | #include <asm/fsl_law.h> |
Kyle Moffett | e37716a | 2011-03-15 11:23:47 -0400 | [diff] [blame] | 11 | #include <div64.h> |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 12 | |
| 13 | #include "ddr.h" |
| 14 | |
Kyle Moffett | e37716a | 2011-03-15 11:23:47 -0400 | [diff] [blame] | 15 | /* To avoid 64-bit full-divides, we factor this here */ |
Kyle Moffett | 313e827 | 2011-04-14 13:39:30 -0400 | [diff] [blame] | 16 | #define ULL_2E12 2000000000000ULL |
| 17 | #define UL_5POW12 244140625UL |
| 18 | #define UL_2POW13 (1UL << 13) |
Kyle Moffett | e37716a | 2011-03-15 11:23:47 -0400 | [diff] [blame] | 19 | |
Kyle Moffett | 313e827 | 2011-04-14 13:39:30 -0400 | [diff] [blame] | 20 | #define ULL_8FS 0xFFFFFFFFULL |
Kyle Moffett | e37716a | 2011-03-15 11:23:47 -0400 | [diff] [blame] | 21 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 22 | /* |
York Sun | dc4d40c | 2011-08-26 11:32:42 -0700 | [diff] [blame] | 23 | * Round up mclk_ps to nearest 1 ps in memory controller code |
| 24 | * if the error is 0.5ps or more. |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 25 | * |
| 26 | * If an imprecise data rate is too high due to rounding error |
| 27 | * propagation, compute a suitably rounded mclk_ps to compute |
| 28 | * a working memory controller configuration. |
| 29 | */ |
| 30 | unsigned int get_memory_clk_period_ps(void) |
| 31 | { |
Kyle Moffett | e37716a | 2011-03-15 11:23:47 -0400 | [diff] [blame] | 32 | unsigned int data_rate = get_ddr_freq(0); |
| 33 | unsigned int result; |
| 34 | |
| 35 | /* Round to nearest 10ps, being careful about 64-bit multiply/divide */ |
York Sun | dc4d40c | 2011-08-26 11:32:42 -0700 | [diff] [blame] | 36 | unsigned long long rem, mclk_ps = ULL_2E12; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 37 | |
Kyle Moffett | e37716a | 2011-03-15 11:23:47 -0400 | [diff] [blame] | 38 | /* Now perform the big divide, the result fits in 32-bits */ |
York Sun | dc4d40c | 2011-08-26 11:32:42 -0700 | [diff] [blame] | 39 | rem = do_div(mclk_ps, data_rate); |
| 40 | result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps; |
Kyle Moffett | e37716a | 2011-03-15 11:23:47 -0400 | [diff] [blame] | 41 | |
York Sun | dc4d40c | 2011-08-26 11:32:42 -0700 | [diff] [blame] | 42 | return result; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 43 | } |
| 44 | |
| 45 | /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */ |
| 46 | unsigned int picos_to_mclk(unsigned int picos) |
| 47 | { |
Kyle Moffett | e37716a | 2011-03-15 11:23:47 -0400 | [diff] [blame] | 48 | unsigned long long clks, clks_rem; |
York Sun | dc4d40c | 2011-08-26 11:32:42 -0700 | [diff] [blame] | 49 | unsigned long data_rate = get_ddr_freq(0); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 50 | |
Kyle Moffett | e37716a | 2011-03-15 11:23:47 -0400 | [diff] [blame] | 51 | /* Short circuit for zero picos */ |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 52 | if (!picos) |
| 53 | return 0; |
| 54 | |
Kyle Moffett | e37716a | 2011-03-15 11:23:47 -0400 | [diff] [blame] | 55 | /* First multiply the time by the data rate (32x32 => 64) */ |
York Sun | dc4d40c | 2011-08-26 11:32:42 -0700 | [diff] [blame] | 56 | clks = picos * (unsigned long long)data_rate; |
Kyle Moffett | e37716a | 2011-03-15 11:23:47 -0400 | [diff] [blame] | 57 | /* |
| 58 | * Now divide by 5^12 and track the 32-bit remainder, then divide |
| 59 | * by 2*(2^12) using shifts (and updating the remainder). |
| 60 | */ |
Kyle Moffett | 313e827 | 2011-04-14 13:39:30 -0400 | [diff] [blame] | 61 | clks_rem = do_div(clks, UL_5POW12); |
York Sun | dc4d40c | 2011-08-26 11:32:42 -0700 | [diff] [blame] | 62 | clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12; |
Kyle Moffett | e37716a | 2011-03-15 11:23:47 -0400 | [diff] [blame] | 63 | clks >>= 13; |
| 64 | |
York Sun | dc4d40c | 2011-08-26 11:32:42 -0700 | [diff] [blame] | 65 | /* If we had a remainder greater than the 1ps error, then round up */ |
| 66 | if (clks_rem > data_rate) |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 67 | clks++; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 68 | |
Kyle Moffett | e37716a | 2011-03-15 11:23:47 -0400 | [diff] [blame] | 69 | /* Clamp to the maximum representable value */ |
Kyle Moffett | 313e827 | 2011-04-14 13:39:30 -0400 | [diff] [blame] | 70 | if (clks > ULL_8FS) |
| 71 | clks = ULL_8FS; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 72 | return (unsigned int) clks; |
| 73 | } |
| 74 | |
| 75 | unsigned int mclk_to_picos(unsigned int mclk) |
| 76 | { |
| 77 | return get_memory_clk_period_ps() * mclk; |
| 78 | } |
| 79 | |
| 80 | void |
| 81 | __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 82 | unsigned int law_memctl, |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 83 | unsigned int ctrl_num) |
| 84 | { |
Kumar Gala | 68ef4bd | 2009-06-11 23:42:35 -0500 | [diff] [blame] | 85 | unsigned long long base = memctl_common_params->base_address; |
| 86 | unsigned long long size = memctl_common_params->total_mem; |
| 87 | |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 88 | /* |
| 89 | * If no DIMMs on this controller, do not proceed any further. |
| 90 | */ |
| 91 | if (!memctl_common_params->ndimms_present) { |
| 92 | return; |
| 93 | } |
| 94 | |
Kumar Gala | 68ef4bd | 2009-06-11 23:42:35 -0500 | [diff] [blame] | 95 | #if !defined(CONFIG_PHYS_64BIT) |
| 96 | if (base >= CONFIG_MAX_MEM_MAPPED) |
| 97 | return; |
| 98 | if ((base + size) >= CONFIG_MAX_MEM_MAPPED) |
| 99 | size = CONFIG_MAX_MEM_MAPPED - base; |
| 100 | #endif |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 101 | if (set_ddr_laws(base, size, law_memctl) < 0) { |
| 102 | printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num, |
| 103 | law_memctl); |
| 104 | return ; |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 105 | } |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 106 | debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n", |
| 107 | base, size, law_memctl); |
Kumar Gala | 124b082 | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 108 | } |
| 109 | |
| 110 | __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void |
| 111 | fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, |
| 112 | unsigned int memctl_interleaved, |
| 113 | unsigned int ctrl_num); |
Peter Tyser | f4018f9 | 2009-07-17 10:14:48 -0500 | [diff] [blame] | 114 | |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 115 | void fsl_ddr_set_intl3r(const unsigned int granule_size) |
| 116 | { |
| 117 | #ifdef CONFIG_E6500 |
| 118 | u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); |
| 119 | *mcintl3r = 0x80000000 | (granule_size & 0x1f); |
| 120 | debug("Enable MCINTL3R with granule size 0x%x\n", granule_size); |
| 121 | #endif |
| 122 | } |
| 123 | |
York Sun | a28496f | 2012-10-08 07:44:25 +0000 | [diff] [blame] | 124 | u32 fsl_ddr_get_intl3r(void) |
| 125 | { |
| 126 | u32 val = 0; |
| 127 | #ifdef CONFIG_E6500 |
| 128 | u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); |
| 129 | val = *mcintl3r; |
| 130 | #endif |
| 131 | return val; |
| 132 | } |
| 133 | |
Peter Tyser | f4018f9 | 2009-07-17 10:14:48 -0500 | [diff] [blame] | 134 | void board_add_ram_info(int use_default) |
| 135 | { |
York Sun | e12ce98 | 2011-08-26 11:32:44 -0700 | [diff] [blame] | 136 | #if defined(CONFIG_MPC83xx) |
| 137 | immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
| 138 | ccsr_ddr_t *ddr = (void *)&immap->ddr; |
| 139 | #elif defined(CONFIG_MPC85xx) |
| 140 | ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); |
Peter Tyser | f4018f9 | 2009-07-17 10:14:48 -0500 | [diff] [blame] | 141 | #elif defined(CONFIG_MPC86xx) |
York Sun | e12ce98 | 2011-08-26 11:32:44 -0700 | [diff] [blame] | 142 | ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC86xx_DDR_ADDR); |
Peter Tyser | f4018f9 | 2009-07-17 10:14:48 -0500 | [diff] [blame] | 143 | #endif |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 144 | #if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3) |
| 145 | u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); |
| 146 | #endif |
Peter Tyser | f4018f9 | 2009-07-17 10:14:48 -0500 | [diff] [blame] | 147 | #if (CONFIG_NUM_DDR_CONTROLLERS > 1) |
| 148 | uint32_t cs0_config = in_be32(&ddr->cs0_config); |
| 149 | #endif |
| 150 | uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg); |
| 151 | int cas_lat; |
| 152 | |
York Sun | 98df4d1 | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 153 | #if CONFIG_NUM_DDR_CONTROLLERS >= 2 |
| 154 | if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { |
York Sun | 016095d | 2012-10-08 07:44:24 +0000 | [diff] [blame] | 155 | ddr = (void __iomem *)CONFIG_SYS_MPC85xx_DDR2_ADDR; |
York Sun | 98df4d1 | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 156 | sdram_cfg = in_be32(&ddr->sdram_cfg); |
| 157 | } |
| 158 | #endif |
| 159 | #if CONFIG_NUM_DDR_CONTROLLERS >= 3 |
| 160 | if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { |
York Sun | 016095d | 2012-10-08 07:44:24 +0000 | [diff] [blame] | 161 | ddr = (void __iomem *)CONFIG_SYS_MPC85xx_DDR3_ADDR; |
York Sun | 98df4d1 | 2012-10-08 07:44:23 +0000 | [diff] [blame] | 162 | sdram_cfg = in_be32(&ddr->sdram_cfg); |
| 163 | } |
| 164 | #endif |
Peter Tyser | f4018f9 | 2009-07-17 10:14:48 -0500 | [diff] [blame] | 165 | puts(" (DDR"); |
| 166 | switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >> |
| 167 | SDRAM_CFG_SDRAM_TYPE_SHIFT) { |
| 168 | case SDRAM_TYPE_DDR1: |
| 169 | puts("1"); |
| 170 | break; |
| 171 | case SDRAM_TYPE_DDR2: |
| 172 | puts("2"); |
| 173 | break; |
| 174 | case SDRAM_TYPE_DDR3: |
| 175 | puts("3"); |
| 176 | break; |
| 177 | default: |
| 178 | puts("?"); |
| 179 | break; |
| 180 | } |
| 181 | |
| 182 | if (sdram_cfg & SDRAM_CFG_32_BE) |
| 183 | puts(", 32-bit"); |
Poonam Aggrwal | 42d3640 | 2011-02-07 15:09:51 +0530 | [diff] [blame] | 184 | else if (sdram_cfg & SDRAM_CFG_16_BE) |
| 185 | puts(", 16-bit"); |
Peter Tyser | f4018f9 | 2009-07-17 10:14:48 -0500 | [diff] [blame] | 186 | else |
| 187 | puts(", 64-bit"); |
| 188 | |
| 189 | /* Calculate CAS latency based on timing cfg values */ |
| 190 | cas_lat = ((in_be32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1; |
| 191 | if ((in_be32(&ddr->timing_cfg_3) >> 12) & 1) |
| 192 | cas_lat += (8 << 1); |
| 193 | printf(", CL=%d", cas_lat >> 1); |
| 194 | if (cas_lat & 0x1) |
| 195 | puts(".5"); |
| 196 | |
| 197 | if (sdram_cfg & SDRAM_CFG_ECC_EN) |
| 198 | puts(", ECC on)"); |
| 199 | else |
| 200 | puts(", ECC off)"); |
| 201 | |
York Sun | e8dc17b | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 202 | #if (CONFIG_NUM_DDR_CONTROLLERS == 3) |
| 203 | #ifdef CONFIG_E6500 |
| 204 | if (*mcintl3r & 0x80000000) { |
| 205 | puts("\n"); |
| 206 | puts(" DDR Controller Interleaving Mode: "); |
| 207 | switch (*mcintl3r & 0x1f) { |
| 208 | case FSL_DDR_3WAY_1KB_INTERLEAVING: |
| 209 | puts("3-way 1KB"); |
| 210 | break; |
| 211 | case FSL_DDR_3WAY_4KB_INTERLEAVING: |
| 212 | puts("3-way 4KB"); |
| 213 | break; |
| 214 | case FSL_DDR_3WAY_8KB_INTERLEAVING: |
| 215 | puts("3-way 8KB"); |
| 216 | break; |
| 217 | default: |
| 218 | puts("3-way UNKNOWN"); |
| 219 | break; |
| 220 | } |
| 221 | } |
| 222 | #endif |
| 223 | #endif |
| 224 | #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) |
Peter Tyser | f4018f9 | 2009-07-17 10:14:48 -0500 | [diff] [blame] | 225 | if (cs0_config & 0x20000000) { |
| 226 | puts("\n"); |
| 227 | puts(" DDR Controller Interleaving Mode: "); |
| 228 | |
| 229 | switch ((cs0_config >> 24) & 0xf) { |
| 230 | case FSL_DDR_CACHE_LINE_INTERLEAVING: |
| 231 | puts("cache line"); |
| 232 | break; |
| 233 | case FSL_DDR_PAGE_INTERLEAVING: |
| 234 | puts("page"); |
| 235 | break; |
| 236 | case FSL_DDR_BANK_INTERLEAVING: |
| 237 | puts("bank"); |
| 238 | break; |
| 239 | case FSL_DDR_SUPERBANK_INTERLEAVING: |
| 240 | puts("super-bank"); |
| 241 | break; |
| 242 | default: |
| 243 | puts("invalid"); |
| 244 | break; |
| 245 | } |
| 246 | } |
| 247 | #endif |
| 248 | |
| 249 | if ((sdram_cfg >> 8) & 0x7f) { |
| 250 | puts("\n"); |
| 251 | puts(" DDR Chip-Select Interleaving Mode: "); |
| 252 | switch(sdram_cfg >> 8 & 0x7f) { |
| 253 | case FSL_DDR_CS0_CS1_CS2_CS3: |
| 254 | puts("CS0+CS1+CS2+CS3"); |
| 255 | break; |
| 256 | case FSL_DDR_CS0_CS1: |
| 257 | puts("CS0+CS1"); |
| 258 | break; |
| 259 | case FSL_DDR_CS2_CS3: |
| 260 | puts("CS2+CS3"); |
| 261 | break; |
| 262 | case FSL_DDR_CS0_CS1_AND_CS2_CS3: |
| 263 | puts("CS0+CS1 and CS2+CS3"); |
| 264 | break; |
| 265 | default: |
| 266 | puts("invalid"); |
| 267 | break; |
| 268 | } |
| 269 | } |
| 270 | } |