blob: c6b9cd0accf2c07383bc1869c09177335f0ba0cf [file] [log] [blame]
Mingkai Hu5fbc7cf2009-09-22 14:53:21 +08001/*
2 * Copyright 2009 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
Scott Woodfac86242012-08-17 19:46:29 -050024#include <asm/processor.h>
25#include <asm/global_data.h>
Dipen Dudhat9eae0832011-03-22 09:27:39 +053026#include <asm/fsl_ifc.h>
Mingkai Hu5fbc7cf2009-09-22 14:53:21 +080027#include <asm/io.h>
28
Scott Woodfac86242012-08-17 19:46:29 -050029DECLARE_GLOBAL_DATA_PTR;
30
Mingkai Hu5fbc7cf2009-09-22 14:53:21 +080031void cpu_init_f(void)
32{
Scott Wood095b7122012-09-20 19:02:18 -050033#ifdef CONFIG_SYS_INIT_L2_ADDR
Mingkai Hu5fbc7cf2009-09-22 14:53:21 +080034 ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
Mingkai Hu5fbc7cf2009-09-22 14:53:21 +080035
36 out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
37
38 /* set MBECCDIS=1, SBECCDIS=1 */
39 out_be32(&l2cache->l2errdis,
40 (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
41
42 /* set L2E=1 & L2SRAM=001 */
43 out_be32(&l2cache->l2ctl,
44 (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
Mingkai Hu5fbc7cf2009-09-22 14:53:21 +080045#endif
Scott Woodfac86242012-08-17 19:46:29 -050046}
47
48#ifndef CONFIG_SYS_FSL_TBCLK_DIV
49#define CONFIG_SYS_FSL_TBCLK_DIV 8
50#endif
51
52void udelay(unsigned long usec)
53{
54 u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000);
55 u32 ticks = ticks_per_usec * usec;
56 u32 s = mfspr(SPRN_TBRL);
57
58 while ((mfspr(SPRN_TBRL) - s) < ticks);
Mingkai Hu5fbc7cf2009-09-22 14:53:21 +080059}