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TsiChungLiew8999e6b2008-01-15 13:37:34 -06001/*
2 *
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
Alison Wang027f76f2012-03-26 21:49:07 +00006 * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
TsiChungLiew8999e6b2008-01-15 13:37:34 -06007 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29#include <MCD_dma.h>
30#include <asm/immap.h>
Alison Wang027f76f2012-03-26 21:49:07 +000031#include <asm/io.h>
TsiChungLiew8999e6b2008-01-15 13:37:34 -060032
TsiChung Liew69b17572008-10-21 13:47:54 +000033#if defined(CONFIG_CMD_NET)
34#include <config.h>
35#include <net.h>
36#include <asm/fsl_mcdmafec.h>
37#endif
38
TsiChungLiew8999e6b2008-01-15 13:37:34 -060039/*
40 * Breath some life into the CPU...
41 *
42 * Set up the memory map,
43 * initialize a bunch of registers,
44 * initialize the UPM's
45 */
46void cpu_init_f(void)
47{
Alison Wang027f76f2012-03-26 21:49:07 +000048 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
49 fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
50 xlbarb_t *xlbarb = (xlbarb_t *) MMAP_XARB;
TsiChungLiew8999e6b2008-01-15 13:37:34 -060051
Alison Wang027f76f2012-03-26 21:49:07 +000052 out_be32(&xlbarb->adrto, 0x2000);
53 out_be32(&xlbarb->datto, 0x2500);
54 out_be32(&xlbarb->busto, 0x3000);
TsiChungLiew8999e6b2008-01-15 13:37:34 -060055
Alison Wang027f76f2012-03-26 21:49:07 +000056 out_be32(&xlbarb->cfg, XARB_CFG_AT | XARB_CFG_DT);
TsiChungLiew8999e6b2008-01-15 13:37:34 -060057
58 /* Master Priority Enable */
Alison Wang027f76f2012-03-26 21:49:07 +000059 out_be32(&xlbarb->prien, 0xff);
60 out_be32(&xlbarb->pri, 0);
TsiChungLiew8999e6b2008-01-15 13:37:34 -060061
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020062#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
Alison Wang027f76f2012-03-26 21:49:07 +000063 out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
64 out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
65 out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
TsiChungLiew8999e6b2008-01-15 13:37:34 -060066#endif
67
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020068#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
Alison Wang027f76f2012-03-26 21:49:07 +000069 out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
70 out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
71 out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
TsiChungLiew8999e6b2008-01-15 13:37:34 -060072#endif
73
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020074#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
Alison Wang027f76f2012-03-26 21:49:07 +000075 out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
76 out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
77 out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
TsiChungLiew8999e6b2008-01-15 13:37:34 -060078#endif
79
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020080#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
Alison Wang027f76f2012-03-26 21:49:07 +000081 out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
82 out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
83 out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
TsiChungLiew8999e6b2008-01-15 13:37:34 -060084#endif
85
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020086#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
Alison Wang027f76f2012-03-26 21:49:07 +000087 out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
88 out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
89 out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
TsiChungLiew8999e6b2008-01-15 13:37:34 -060090#endif
91
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020092#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
Alison Wang027f76f2012-03-26 21:49:07 +000093 out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
94 out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
95 out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
TsiChungLiew8999e6b2008-01-15 13:37:34 -060096#endif
97
98#ifdef CONFIG_FSL_I2C
Alison Wang027f76f2012-03-26 21:49:07 +000099 out_be16(&gpio->par_feci2cirq,
100 GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA);
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600101#endif
102
103 icache_enable();
104}
105
106/*
107 * initialize higher level parts of CPU like timers
108 */
109int cpu_init_r(void)
110{
111#if defined(CONFIG_CMD_NET) && defined(CONFIG_FSLDMAFEC)
112 MCD_initDma((dmaRegs *) (MMAP_MCDMA), (void *)(MMAP_SRAM + 512),
113 MCD_RELOC_TASKS);
114#endif
115 return (0);
116}
117
TsiChung Liewf9556a72010-03-09 19:17:52 -0600118void uart_port_conf(int port)
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600119{
Alison Wang027f76f2012-03-26 21:49:07 +0000120 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
121 u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40);
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600122
123 /* Setup Ports: */
TsiChung Liewf9556a72010-03-09 19:17:52 -0600124 switch (port) {
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600125 case 0:
Alison Wang027f76f2012-03-26 21:49:07 +0000126 out_8(&gpio->par_psc0, GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0);
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600127 break;
128 case 1:
Alison Wang027f76f2012-03-26 21:49:07 +0000129 out_8(&gpio->par_psc1, GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1);
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600130 break;
131 case 2:
Alison Wang027f76f2012-03-26 21:49:07 +0000132 out_8(&gpio->par_psc2, GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2);
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600133 break;
134 case 3:
Alison Wang027f76f2012-03-26 21:49:07 +0000135 out_8(&gpio->par_psc3, GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3);
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600136 break;
137 }
138
Alison Wang027f76f2012-03-26 21:49:07 +0000139 clrbits_8(pscsicr, 0x07);
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600140}
TsiChung Liew69b17572008-10-21 13:47:54 +0000141
142#if defined(CONFIG_CMD_NET)
143int fecpin_setclear(struct eth_device *dev, int setclear)
144{
Alison Wang027f76f2012-03-26 21:49:07 +0000145 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
TsiChung Liew69b17572008-10-21 13:47:54 +0000146 struct fec_info_dma *info = (struct fec_info_dma *)dev->priv;
147
148 if (setclear) {
149 if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
Alison Wang027f76f2012-03-26 21:49:07 +0000150 setbits_be16(&gpio->par_feci2cirq, 0xf000);
TsiChung Liew69b17572008-10-21 13:47:54 +0000151 else
Alison Wang027f76f2012-03-26 21:49:07 +0000152 setbits_be16(&gpio->par_feci2cirq, 0x0fc0);
TsiChung Liew69b17572008-10-21 13:47:54 +0000153 } else {
154 if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
Alison Wang027f76f2012-03-26 21:49:07 +0000155 clrbits_be16(&gpio->par_feci2cirq, 0xf000);
TsiChung Liew69b17572008-10-21 13:47:54 +0000156 else
Alison Wang027f76f2012-03-26 21:49:07 +0000157 clrbits_be16(&gpio->par_feci2cirq, 0x0fc0);
TsiChung Liew69b17572008-10-21 13:47:54 +0000158 }
159 return 0;
160}
161#endif