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git01.mediatek.com / filogic / uboot / a1fa5cbbc00b663f074408045fc0460b0d04603d / . / arch / riscv / dts / th1520.dtsi
blob: cbe3481fadd10cf0f8e146abce94c0c5c09acf3b [file] [log] [blame]
Yixun Lane3a02bd2023-07-08 19:24:33 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021 Alibaba Group Holding Limited.
4 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8
9/ {
10 compatible = "thead,th1520";
11 #address-cells = <2>;
12 #size-cells = <2>;
13
14 cpus: cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17 timebase-frequency = <3000000>;
18
19 c910_0: cpu@0 {
20 compatible = "thead,c910", "riscv";
21 device_type = "cpu";
22 riscv,isa = "rv64imafdc";
23 reg = <0>;
24 i-cache-block-size = <64>;
25 i-cache-size = <65536>;
26 i-cache-sets = <512>;
27 d-cache-block-size = <64>;
28 d-cache-size = <65536>;
29 d-cache-sets = <512>;
30 next-level-cache = <&l2_cache>;
31 mmu-type = "riscv,sv39";
32
33 cpu0_intc: interrupt-controller {
34 compatible = "riscv,cpu-intc";
35 interrupt-controller;
36 #interrupt-cells = <1>;
37 };
38 };
39
40 c910_1: cpu@1 {
41 compatible = "thead,c910", "riscv";
42 device_type = "cpu";
43 riscv,isa = "rv64imafdc";
44 reg = <1>;
45 i-cache-block-size = <64>;
46 i-cache-size = <65536>;
47 i-cache-sets = <512>;
48 d-cache-block-size = <64>;
49 d-cache-size = <65536>;
50 d-cache-sets = <512>;
51 next-level-cache = <&l2_cache>;
52 mmu-type = "riscv,sv39";
53
54 cpu1_intc: interrupt-controller {
55 compatible = "riscv,cpu-intc";
56 interrupt-controller;
57 #interrupt-cells = <1>;
58 };
59 };
60
61 c910_2: cpu@2 {
62 compatible = "thead,c910", "riscv";
63 device_type = "cpu";
64 riscv,isa = "rv64imafdc";
65 reg = <2>;
66 i-cache-block-size = <64>;
67 i-cache-size = <65536>;
68 i-cache-sets = <512>;
69 d-cache-block-size = <64>;
70 d-cache-size = <65536>;
71 d-cache-sets = <512>;
72 next-level-cache = <&l2_cache>;
73 mmu-type = "riscv,sv39";
74
75 cpu2_intc: interrupt-controller {
76 compatible = "riscv,cpu-intc";
77 interrupt-controller;
78 #interrupt-cells = <1>;
79 };
80 };
81
82 c910_3: cpu@3 {
83 compatible = "thead,c910", "riscv";
84 device_type = "cpu";
85 riscv,isa = "rv64imafdc";
86 reg = <3>;
87 i-cache-block-size = <64>;
88 i-cache-size = <65536>;
89 i-cache-sets = <512>;
90 d-cache-block-size = <64>;
91 d-cache-size = <65536>;
92 d-cache-sets = <512>;
93 next-level-cache = <&l2_cache>;
94 mmu-type = "riscv,sv39";
95
96 cpu3_intc: interrupt-controller {
97 compatible = "riscv,cpu-intc";
98 interrupt-controller;
99 #interrupt-cells = <1>;
100 };
101 };
102
103 l2_cache: l2-cache {
104 compatible = "cache";
105 cache-block-size = <64>;
106 cache-level = <2>;
107 cache-size = <1048576>;
108 cache-sets = <1024>;
109 cache-unified;
110 };
111 };
112
113 osc: oscillator {
114 compatible = "fixed-clock";
115 clock-output-names = "osc_24m";
116 #clock-cells = <0>;
117 };
118
119 osc_32k: 32k-oscillator {
120 compatible = "fixed-clock";
121 clock-output-names = "osc_32k";
122 #clock-cells = <0>;
123 };
124
125 apb_clk: apb-clk-clock {
126 compatible = "fixed-clock";
127 clock-output-names = "apb_clk";
128 #clock-cells = <0>;
129 };
130
131 uart_sclk: uart-sclk-clock {
132 compatible = "fixed-clock";
133 clock-output-names = "uart_sclk";
134 #clock-cells = <0>;
135 };
136
Maksim Kiselev81f9c3a2024-12-11 23:11:00 +0300[diff] [blame]137 sdhci_clk: sdhci-clock {
138 compatible = "fixed-clock";
139 clock-frequency = <198000000>;
140 clock-output-names = "sdhci_clk";
141 #clock-cells = <0>;
142 };
143
Yixun Lane3a02bd2023-07-08 19:24:33 +0800[diff] [blame]144 soc {
145 compatible = "simple-bus";
146 interrupt-parent = <&plic>;
147 #address-cells = <2>;
148 #size-cells = <2>;
149 ranges;
150
151 plic: interrupt-controller@ffd8000000 {
152 compatible = "thead,th1520-plic", "thead,c900-plic";
153 reg = <0xff 0xd8000000 0x0 0x01000000>;
154 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
155 <&cpu1_intc 11>, <&cpu1_intc 9>,
156 <&cpu2_intc 11>, <&cpu2_intc 9>,
157 <&cpu3_intc 11>, <&cpu3_intc 9>;
158 interrupt-controller;
159 #address-cells = <0>;
160 #interrupt-cells = <2>;
161 riscv,ndev = <240>;
162 };
163
164 clint: timer@ffdc000000 {
165 compatible = "thead,th1520-clint", "thead,c900-clint";
166 reg = <0xff 0xdc000000 0x0 0x00010000>;
167 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
168 <&cpu1_intc 3>, <&cpu1_intc 7>,
169 <&cpu2_intc 3>, <&cpu2_intc 7>,
170 <&cpu3_intc 3>, <&cpu3_intc 7>;
171 };
172
173 uart0: serial@ffe7014000 {
174 compatible = "snps,dw-apb-uart";
175 reg = <0xff 0xe7014000 0x0 0x100>;
176 interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
177 clocks = <&uart_sclk>;
178 reg-shift = <2>;
179 reg-io-width = <4>;
180 status = "disabled";
181 };
182
Maksim Kiselev81f9c3a2024-12-11 23:11:00 +0300[diff] [blame]183 emmc: mmc@ffe7080000 {
184 compatible = "thead,th1520-dwcmshc";
185 reg = <0xff 0xe7080000 0x0 0x10000>;
186 interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&sdhci_clk>;
188 clock-names = "core";
189 status = "disabled";
190 };
191
192 sdio0: mmc@ffe7090000 {
193 compatible = "thead,th1520-dwcmshc";
194 reg = <0xff 0xe7090000 0x0 0x10000>;
195 interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&sdhci_clk>;
197 clock-names = "core";
198 status = "disabled";
199 };
200
201 sdio1: mmc@ffe70a0000 {
202 compatible = "thead,th1520-dwcmshc";
203 reg = <0xff 0xe70a0000 0x0 0x10000>;
204 interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&sdhci_clk>;
206 clock-names = "core";
207 status = "disabled";
208 };
209
Yixun Lane3a02bd2023-07-08 19:24:33 +0800[diff] [blame]210 uart1: serial@ffe7f00000 {
211 compatible = "snps,dw-apb-uart";
212 reg = <0xff 0xe7f00000 0x0 0x100>;
213 interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&uart_sclk>;
215 reg-shift = <2>;
216 reg-io-width = <4>;
217 status = "disabled";
218 };
219
220 uart3: serial@ffe7f04000 {
221 compatible = "snps,dw-apb-uart";
222 reg = <0xff 0xe7f04000 0x0 0x100>;
223 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&uart_sclk>;
225 reg-shift = <2>;
226 reg-io-width = <4>;
227 status = "disabled";
228 };
229
230 gpio2: gpio@ffe7f34000 {
231 compatible = "snps,dw-apb-gpio";
232 reg = <0xff 0xe7f34000 0x0 0x1000>;
233 #address-cells = <1>;
234 #size-cells = <0>;
235
236 portc: gpio-controller@0 {
237 compatible = "snps,dw-apb-gpio-port";
238 gpio-controller;
239 #gpio-cells = <2>;
240 ngpios = <32>;
241 reg = <0>;
242 interrupt-controller;
243 #interrupt-cells = <2>;
244 interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
245 };
246 };
247
248 gpio3: gpio@ffe7f38000 {
249 compatible = "snps,dw-apb-gpio";
250 reg = <0xff 0xe7f38000 0x0 0x1000>;
251 #address-cells = <1>;
252 #size-cells = <0>;
253
254 portd: gpio-controller@0 {
255 compatible = "snps,dw-apb-gpio-port";
256 gpio-controller;
257 #gpio-cells = <2>;
258 ngpios = <32>;
259 reg = <0>;
260 interrupt-controller;
261 #interrupt-cells = <2>;
262 interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
263 };
264 };
265
266 gpio0: gpio@ffec005000 {
267 compatible = "snps,dw-apb-gpio";
268 reg = <0xff 0xec005000 0x0 0x1000>;
269 #address-cells = <1>;
270 #size-cells = <0>;
271
272 porta: gpio-controller@0 {
273 compatible = "snps,dw-apb-gpio-port";
274 gpio-controller;
275 #gpio-cells = <2>;
276 ngpios = <32>;
277 reg = <0>;
278 interrupt-controller;
279 #interrupt-cells = <2>;
280 interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
281 };
282 };
283
284 gpio1: gpio@ffec006000 {
285 compatible = "snps,dw-apb-gpio";
286 reg = <0xff 0xec006000 0x0 0x1000>;
287 #address-cells = <1>;
288 #size-cells = <0>;
289
290 portb: gpio-controller@0 {
291 compatible = "snps,dw-apb-gpio-port";
292 gpio-controller;
293 #gpio-cells = <2>;
294 ngpios = <32>;
295 reg = <0>;
296 interrupt-controller;
297 #interrupt-cells = <2>;
298 interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
299 };
300 };
301
302 uart2: serial@ffec010000 {
303 compatible = "snps,dw-apb-uart";
304 reg = <0xff 0xec010000 0x0 0x4000>;
305 interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&uart_sclk>;
307 reg-shift = <2>;
308 reg-io-width = <4>;
309 status = "disabled";
310 };
311
312 timer0: timer@ffefc32000 {
313 compatible = "snps,dw-apb-timer";
314 reg = <0xff 0xefc32000 0x0 0x14>;
315 clocks = <&apb_clk>;
316 clock-names = "timer";
317 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
318 status = "disabled";
319 };
320
321 timer1: timer@ffefc32014 {
322 compatible = "snps,dw-apb-timer";
323 reg = <0xff 0xefc32014 0x0 0x14>;
324 clocks = <&apb_clk>;
325 clock-names = "timer";
326 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
327 status = "disabled";
328 };
329
330 timer2: timer@ffefc32028 {
331 compatible = "snps,dw-apb-timer";
332 reg = <0xff 0xefc32028 0x0 0x14>;
333 clocks = <&apb_clk>;
334 clock-names = "timer";
335 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
336 status = "disabled";
337 };
338
339 timer3: timer@ffefc3203c {
340 compatible = "snps,dw-apb-timer";
341 reg = <0xff 0xefc3203c 0x0 0x14>;
342 clocks = <&apb_clk>;
343 clock-names = "timer";
344 interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
345 status = "disabled";
346 };
347
348 uart4: serial@fff7f08000 {
349 compatible = "snps,dw-apb-uart";
350 reg = <0xff 0xf7f08000 0x0 0x4000>;
351 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&uart_sclk>;
353 reg-shift = <2>;
354 reg-io-width = <4>;
355 status = "disabled";
356 };
357
358 uart5: serial@fff7f0c000 {
359 compatible = "snps,dw-apb-uart";
360 reg = <0xff 0xf7f0c000 0x0 0x4000>;
361 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&uart_sclk>;
363 reg-shift = <2>;
364 reg-io-width = <4>;
365 status = "disabled";
366 };
367
368 timer4: timer@ffffc33000 {
369 compatible = "snps,dw-apb-timer";
370 reg = <0xff 0xffc33000 0x0 0x14>;
371 clocks = <&apb_clk>;
372 clock-names = "timer";
373 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
374 status = "disabled";
375 };
376
377 timer5: timer@ffffc33014 {
378 compatible = "snps,dw-apb-timer";
379 reg = <0xff 0xffc33014 0x0 0x14>;
380 clocks = <&apb_clk>;
381 clock-names = "timer";
382 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
383 status = "disabled";
384 };
385
386 timer6: timer@ffffc33028 {
387 compatible = "snps,dw-apb-timer";
388 reg = <0xff 0xffc33028 0x0 0x14>;
389 clocks = <&apb_clk>;
390 clock-names = "timer";
391 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
392 status = "disabled";
393 };
394
395 timer7: timer@ffffc3303c {
396 compatible = "snps,dw-apb-timer";
397 reg = <0xff 0xffc3303c 0x0 0x14>;
398 clocks = <&apb_clk>;
399 clock-names = "timer";
400 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
401 status = "disabled";
402 };
403
404 ao_gpio0: gpio@fffff41000 {
405 compatible = "snps,dw-apb-gpio";
406 reg = <0xff 0xfff41000 0x0 0x1000>;
407 #address-cells = <1>;
408 #size-cells = <0>;
409
410 porte: gpio-controller@0 {
411 compatible = "snps,dw-apb-gpio-port";
412 gpio-controller;
413 #gpio-cells = <2>;
414 ngpios = <32>;
415 reg = <0>;
416 interrupt-controller;
417 #interrupt-cells = <2>;
418 interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
419 };
420 };
421
422 ao_gpio1: gpio@fffff52000 {
423 compatible = "snps,dw-apb-gpio";
424 reg = <0xff 0xfff52000 0x0 0x1000>;
425 #address-cells = <1>;
426 #size-cells = <0>;
427
428 portf: gpio-controller@0 {
429 compatible = "snps,dw-apb-gpio-port";
430 gpio-controller;
431 #gpio-cells = <2>;
432 ngpios = <32>;
433 reg = <0>;
434 interrupt-controller;
435 #interrupt-cells = <2>;
436 interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
437 };
438 };
439 };
440};