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git01.mediatek.com / filogic / uboot / a1fa5cbbc00b663f074408045fc0460b0d04603d / . / arch / arm / mach-renesas / include / mach / boot0.h
blob: fc68ffc09456701954b3ef5c155bb2ac50b02a40 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
Marek Vasut1c601052018-04-07 16:16:30 +0200[diff] [blame]2/*
Marek Vasut1de52b92024-12-11 08:30:26 +0100[diff] [blame]3 * Specialty padding for the R-Car Gen2 SPL JTAG loading
Marek Vasut1c601052018-04-07 16:16:30 +0200[diff] [blame]4 */
5
6#ifndef __BOOT0_H
7#define __BOOT0_H
8
Marek Vasutd1687252024-12-12 14:38:29 +0100[diff] [blame]9#if IS_ENABLED(CONFIG_RCAR_GEN2)
Marek Vasut1c601052018-04-07 16:16:30 +0200[diff] [blame]10_start:
11 ARM_VECTORS
12
Simon Glass85ed77d2024-09-29 19:49:46 -0600[diff] [blame]13#ifdef CONFIG_XPL_BUILD
Marek Vasut1c601052018-04-07 16:16:30 +0200[diff] [blame]14 .word 0x0badc0d3;
15 .word 0x0badc0d3;
16 .word 0x0badc0d3;
17 .word 0x0badc0d3;
18 .word 0x0badc0d3;
19 .word 0x0badc0d3;
20 .word 0x0badc0d3;
21 .word 0x0badc0d3;
22#endif
Marek Vasutd1687252024-12-12 14:38:29 +0100[diff] [blame]23#endif
24
25#if IS_ENABLED(CONFIG_R8A779G0)
26
27#ifdef CONFIG_XPL_BUILD
28 /* r1=0xe6170800 */
29 .inst 0xe3a004e6 /* mov r0, #0xe6000000 */
30 .inst 0xe3801817 /* orr r1, r0, #0x170000 */
Marek Vasut15388792024-12-20 01:02:14 +0100[diff] [blame]31 .inst 0xe3814b02 /* orr r4, r1, #0x800 */
Marek Vasutd1687252024-12-12 14:38:29 +0100[diff] [blame]32
33 /* r0=0xe6280000 */
34 .inst 0xe380070a /* orr r0, r0, #0x280000 */
35
36 /* APMU_RVBARPLC0 = (address of 'b reset' below) | CA_CORE0_VLD_RVBARP */
Marek Vasut15388792024-12-20 01:02:14 +0100[diff] [blame]37 .inst 0xe28f3088 /* add r3, pc, #0x88 */
Marek Vasutd1687252024-12-12 14:38:29 +0100[diff] [blame]38 .inst 0xe3833001 /* orr r3, r3, #1 */
Marek Vasut15388792024-12-20 01:02:14 +0100[diff] [blame]39 .inst 0xe5843038 /* str r3, [r4, #56] @ 0x38 */
Marek Vasutd1687252024-12-12 14:38:29 +0100[diff] [blame]40
41 /* APMU_RVBARPHC0 = 0 */
Marek Vasut15388792024-12-20 01:02:14 +0100[diff] [blame]42 .inst 0xe3a05000 /* mov r5, #0 */
43 .inst 0xe584503c /* str r5, [r4, #60] @ 0x3c */
Marek Vasutd1687252024-12-12 14:38:29 +0100[diff] [blame]44
45 /* PRR & 0xff00 ?= 0x5c00, test if this is V4H or V4M */
46 .inst 0xe3a024ff /* mov r2, #0xff000000 */
47 .inst 0xe382260f /* orr r2, r2, #0xf00000 */
48 .inst 0xe5923044 /* ldr r3, [r2, #68] @ 0x44 */
49 .inst 0xe2033cff /* and r3, r3, #0xff00 */
50 .inst 0xe3530b17 /* cmp r3, #0x5c00 */
51 .inst 0x1a00000a /* bne 68 <reset-0x18> */
52 /* if (SoC is V4H) { */
53 /* AP_CORE_APSREG_AP_CLUSTER_N_AUX0 |= AP_CORE_APSREG_AP_CLUSTER_N_AUX0_INIT */
54 .inst 0xe5903010 /* ldr r3, [r0, #16] */
55 .inst 0xe3833003 /* orr r3, r3, #3 */
56 .inst 0xe5803010 /* str r3, [r0, #16] */
57 /* AP_CORE_APSREG_CCI500_AUX |= AP_CORE_APSREG_CCI500_AUX_ACTDIS */
58 .inst 0xe3800a09 /* orr r0, r0, #36864 @ 0x9000 */
59 .inst 0xe5903010 /* ldr r3, [r0, #16] */
60 .inst 0xe3833001 /* orr r3, r3, #1 */
61 .inst 0xe5803010 /* str r3, [r0, #16] */
62 /* AP_CORE_APSREG_P_CCI500_AUX |= AP_CORE_APSREG_P_CCI500_AUX_ASPRTM */
63 .inst 0xe3800802 /* orr r0, r0, #131072 @ 0x20000 */
64 .inst 0xe5903010 /* ldr r3, [r0, #16] */
65 .inst 0xe3833002 /* orr r3, r3, #2 */
66 .inst 0xe5803010 /* str r3, [r0, #16] */
67 /* } */
68 /* APMU_PWRCTRLC0 = CA_CORE0_WUP_REQ */
69 .inst 0xe3a03001 /* mov r3, #1 */
Marek Vasut15388792024-12-20 01:02:14 +0100[diff] [blame]70 .inst 0xe5843000 /* str r3, [r4] */
71 /* Test for APMU_CRBARP valid BAR flags and jump to CR entry point */
72 .inst 0xe3814c03 /* orr r4, r1, #768 @ 0x300 */
73 .inst 0xe584503c /* str r5, [r4, #60] @ 0x3c */
74 .inst 0xe594203c /* ldr r2, [r4, #60] @ 0x3c */
75 .inst 0xe20230ff /* and r3, r2, #255 @ 0xff */
76 .inst 0xe3530011 /* cmp r3, #17 */
77 .inst 0x1afffffb /* bne 78 <reset-0x28> */
78 .inst 0xe1a02922 /* lsr r2, r2, #18 */
79 .inst 0xe1a02902 /* lsl r2, r2, #18 */
80 .inst 0xe1a0f002 /* mov pc, r2 */
81 .inst 0xeafffffe /* b 94 <reset-0xc> */
Marek Vasutd1687252024-12-12 14:38:29 +0100[diff] [blame]82 .inst 0xe1a00000 /* nop @ (mov r0, r0) */
Marek Vasutd1687252024-12-12 14:38:29 +0100[diff] [blame]83 .inst 0xe1a00000 /* nop @ (mov r0, r0) */
Marek Vasut15388792024-12-20 01:02:14 +0100[diff] [blame]84 /* Offset 0xa0 */
Marek Vasutd1687252024-12-12 14:38:29 +0100[diff] [blame]85#endif
86 b reset
87#endif
Marek Vasut1c601052018-04-07 16:16:30 +0200[diff] [blame]88
89#endif /* __BOOT0_H */