blob: ca9d970abc815fc1bfa2bce02fa7c2bf8267fb9a [file] [log] [blame]
Tom Warrene3d95bc2013-01-28 13:32:10 +00001/*
2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
3 *
Tom Rinie2378802016-01-14 22:05:13 -05004 * SPDX-License-Identifier: GPL-2.0
Tom Warrene3d95bc2013-01-28 13:32:10 +00005 */
6
7/* Tegra114 high-level function multiplexing */
8
9#include <common.h>
10#include <asm/arch/clock.h>
11#include <asm/arch/funcmux.h>
12#include <asm/arch/pinmux.h>
13
14int funcmux_select(enum periph_id id, int config)
15{
16 int bad_config = config != FUNCMUX_DEFAULT;
17
18 switch (id) {
19 case PERIPH_ID_UART4:
20 switch (config) {
21 case FUNCMUX_UART4_GMI:
Stephen Warren05617092014-03-21 12:29:00 -060022 pinmux_set_func(PMUX_PINGRP_GMI_A16_PJ7,
23 PMUX_FUNC_UARTD);
24 pinmux_set_func(PMUX_PINGRP_GMI_A17_PB0,
25 PMUX_FUNC_UARTD);
26 pinmux_set_func(PMUX_PINGRP_GMI_A18_PB1,
27 PMUX_FUNC_UARTD);
28 pinmux_set_func(PMUX_PINGRP_GMI_A19_PK7,
29 PMUX_FUNC_UARTD);
Tom Warrene3d95bc2013-01-28 13:32:10 +000030
Stephen Warren05617092014-03-21 12:29:00 -060031 pinmux_set_io(PMUX_PINGRP_GMI_A16_PJ7, PMUX_PIN_OUTPUT);
32 pinmux_set_io(PMUX_PINGRP_GMI_A17_PB0, PMUX_PIN_INPUT);
33 pinmux_set_io(PMUX_PINGRP_GMI_A18_PB1, PMUX_PIN_INPUT);
34 pinmux_set_io(PMUX_PINGRP_GMI_A19_PK7, PMUX_PIN_OUTPUT);
Tom Warrene3d95bc2013-01-28 13:32:10 +000035
Stephen Warren05617092014-03-21 12:29:00 -060036 pinmux_tristate_disable(PMUX_PINGRP_GMI_A16_PJ7);
37 pinmux_tristate_disable(PMUX_PINGRP_GMI_A17_PB0);
38 pinmux_tristate_disable(PMUX_PINGRP_GMI_A18_PB1);
39 pinmux_tristate_disable(PMUX_PINGRP_GMI_A19_PK7);
Tom Warrene3d95bc2013-01-28 13:32:10 +000040 break;
41 }
42 break;
43
44 /* Add other periph IDs here as needed */
45
46 default:
47 debug("%s: invalid periph_id %d", __func__, id);
48 return -1;
49 }
50
51 if (bad_config) {
52 debug("%s: invalid config %d for periph_id %d", __func__,
53 config, id);
54 return -1;
55 }
56 return 0;
57}