| Michal Simek | 962c10a | 2023-11-06 12:56:47 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * dts file for AMD MicroBlaze V |
| 4 | * |
| 5 | * (C) Copyright 2023, Advanced Micro Devices, Inc. |
| 6 | * |
| 7 | * Michal Simek <michal.simek@amd.com> |
| 8 | */ |
| 9 | |
| 10 | /dts-v1/; |
| 11 | / { |
| 12 | #address-cells = <1>; |
| 13 | #size-cells = <1>; |
| 14 | model = "AMD MicroBlaze V 32bit"; |
| Michal Simek | d0f9f3a | 2023-12-20 15:53:28 +0100 | [diff] [blame] | 15 | compatible = "qemu,mbv", "amd,mbv"; |
| Michal Simek | 962c10a | 2023-11-06 12:56:47 +0100 | [diff] [blame] | 16 | |
| 17 | cpus: cpus { |
| 18 | #address-cells = <1>; |
| 19 | #size-cells = <0>; |
| 20 | timebase-frequency = <102000000>; |
| 21 | cpu_0: cpu@0 { |
| 22 | compatible = "amd,mbv32", "riscv"; |
| 23 | device_type = "cpu"; |
| 24 | reg = <0>; |
| 25 | riscv,isa = "rv32imafdc"; |
| 26 | i-cache-size = <32768>; |
| 27 | d-cache-size = <32768>; |
| 28 | clock-frequency = <102000000>; |
| 29 | cpu0_intc: interrupt-controller { |
| 30 | compatible = "riscv,cpu-intc"; |
| 31 | interrupt-controller; |
| 32 | #interrupt-cells = <1>; |
| 33 | }; |
| 34 | }; |
| 35 | }; |
| 36 | |
| 37 | aliases { |
| 38 | serial0 = &uart0; |
| 39 | }; |
| 40 | |
| 41 | chosen { |
| 42 | bootargs = "earlycon"; |
| 43 | stdout-path = "serial0:115200n8"; |
| 44 | }; |
| 45 | |
| 46 | memory@20000000 { |
| 47 | device_type = "memory"; |
| 48 | reg = <0x20000000 0x20000000>; |
| 49 | }; |
| 50 | |
| 51 | clk102: clock { |
| 52 | compatible = "fixed-clock"; |
| 53 | #clock-cells = <0>; |
| 54 | clock-frequency = <102000000>; |
| 55 | }; |
| 56 | |
| 57 | axi: axi { |
| 58 | #address-cells = <1>; |
| 59 | #size-cells = <1>; |
| 60 | compatible = "simple-bus"; |
| 61 | ranges; |
| 62 | bootph-all; |
| 63 | |
| 64 | axi_intc: interrupt-controller@41200000 { |
| 65 | compatible = "xlnx,xps-intc-1.00.a"; |
| 66 | reg = <0x41200000 0x1000>; |
| 67 | interrupt-controller; |
| 68 | interrupt-parent = <&cpu0_intc>; |
| 69 | #interrupt-cells = <2>; |
| 70 | kind-of-intr = <0>; |
| 71 | }; |
| 72 | |
| 73 | xlnx_timer0: timer@41c00000 { |
| 74 | compatible = "xlnx,xps-timer-1.00.a"; |
| 75 | reg = <0x41c00000 0x1000>; |
| 76 | interrupt-parent = <&axi_intc>; |
| 77 | interrupts = <1 2>; |
| 78 | bootph-all; |
| 79 | xlnx,one-timer-only = <0>; |
| 80 | clock-names = "s_axi_aclk"; |
| 81 | clocks = <&clk102>; |
| 82 | }; |
| 83 | |
| 84 | xlnx_timer1: timer@41c20000 { |
| 85 | compatible = "xlnx,xps-timer-1.00.a"; |
| 86 | reg = <0x41c20000 0x1000>; |
| 87 | interrupt-parent = <&axi_intc>; |
| 88 | interrupts = <0 2>; |
| 89 | xlnx,one-timer-only = <0>; |
| 90 | clock-names = "s_axi_aclk"; |
| 91 | clocks = <&clk102>; |
| 92 | }; |
| 93 | |
| 94 | uart0: serial@40600000 { |
| 95 | compatible = "xlnx,xps-uartlite-1.00.a"; |
| 96 | reg = <0x40600000 0x1000>; |
| 97 | interrupt-parent = <&axi_intc>; |
| 98 | interrupts = <2 2>; |
| 99 | bootph-all; |
| 100 | clocks = <&clk102>; |
| 101 | current-speed = <115200>; |
| 102 | xlnx,data-bits = <8>; |
| 103 | xlnx,use-parity = <0>; |
| 104 | }; |
| 105 | }; |
| 106 | }; |