Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / a1b1fd1730d3208da2e7bf5485e47296d8f311b3 / . / arch / riscv / dts / th1520.dtsi
blob: f7bfa4224395b1d5733fe5ca7829944a3f286493 [file] [log] [blame]
Yixun Lane3a02bd2023-07-08 19:24:33 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021 Alibaba Group Holding Limited.
4 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8
9/ {
10 compatible = "thead,th1520";
11 #address-cells = <2>;
12 #size-cells = <2>;
13
14 cpus: cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17 timebase-frequency = <3000000>;
18
19 c910_0: cpu@0 {
20 compatible = "thead,c910", "riscv";
21 device_type = "cpu";
22 riscv,isa = "rv64imafdc";
23 reg = <0>;
24 i-cache-block-size = <64>;
25 i-cache-size = <65536>;
26 i-cache-sets = <512>;
27 d-cache-block-size = <64>;
28 d-cache-size = <65536>;
29 d-cache-sets = <512>;
30 next-level-cache = <&l2_cache>;
31 mmu-type = "riscv,sv39";
32
33 cpu0_intc: interrupt-controller {
34 compatible = "riscv,cpu-intc";
35 interrupt-controller;
36 #interrupt-cells = <1>;
37 };
38 };
39
40 c910_1: cpu@1 {
41 compatible = "thead,c910", "riscv";
42 device_type = "cpu";
43 riscv,isa = "rv64imafdc";
44 reg = <1>;
45 i-cache-block-size = <64>;
46 i-cache-size = <65536>;
47 i-cache-sets = <512>;
48 d-cache-block-size = <64>;
49 d-cache-size = <65536>;
50 d-cache-sets = <512>;
51 next-level-cache = <&l2_cache>;
52 mmu-type = "riscv,sv39";
53
54 cpu1_intc: interrupt-controller {
55 compatible = "riscv,cpu-intc";
56 interrupt-controller;
57 #interrupt-cells = <1>;
58 };
59 };
60
61 c910_2: cpu@2 {
62 compatible = "thead,c910", "riscv";
63 device_type = "cpu";
64 riscv,isa = "rv64imafdc";
65 reg = <2>;
66 i-cache-block-size = <64>;
67 i-cache-size = <65536>;
68 i-cache-sets = <512>;
69 d-cache-block-size = <64>;
70 d-cache-size = <65536>;
71 d-cache-sets = <512>;
72 next-level-cache = <&l2_cache>;
73 mmu-type = "riscv,sv39";
74
75 cpu2_intc: interrupt-controller {
76 compatible = "riscv,cpu-intc";
77 interrupt-controller;
78 #interrupt-cells = <1>;
79 };
80 };
81
82 c910_3: cpu@3 {
83 compatible = "thead,c910", "riscv";
84 device_type = "cpu";
85 riscv,isa = "rv64imafdc";
86 reg = <3>;
87 i-cache-block-size = <64>;
88 i-cache-size = <65536>;
89 i-cache-sets = <512>;
90 d-cache-block-size = <64>;
91 d-cache-size = <65536>;
92 d-cache-sets = <512>;
93 next-level-cache = <&l2_cache>;
94 mmu-type = "riscv,sv39";
95
96 cpu3_intc: interrupt-controller {
97 compatible = "riscv,cpu-intc";
98 interrupt-controller;
99 #interrupt-cells = <1>;
100 };
101 };
102
103 l2_cache: l2-cache {
104 compatible = "cache";
105 cache-block-size = <64>;
106 cache-level = <2>;
107 cache-size = <1048576>;
108 cache-sets = <1024>;
109 cache-unified;
110 };
111 };
112
113 osc: oscillator {
114 compatible = "fixed-clock";
115 clock-output-names = "osc_24m";
116 #clock-cells = <0>;
117 };
118
119 osc_32k: 32k-oscillator {
120 compatible = "fixed-clock";
121 clock-output-names = "osc_32k";
122 #clock-cells = <0>;
123 };
124
125 apb_clk: apb-clk-clock {
126 compatible = "fixed-clock";
127 clock-output-names = "apb_clk";
128 #clock-cells = <0>;
129 };
130
131 uart_sclk: uart-sclk-clock {
132 compatible = "fixed-clock";
133 clock-output-names = "uart_sclk";
134 #clock-cells = <0>;
135 };
136
137 soc {
138 compatible = "simple-bus";
139 interrupt-parent = <&plic>;
140 #address-cells = <2>;
141 #size-cells = <2>;
142 ranges;
143
144 plic: interrupt-controller@ffd8000000 {
145 compatible = "thead,th1520-plic", "thead,c900-plic";
146 reg = <0xff 0xd8000000 0x0 0x01000000>;
147 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
148 <&cpu1_intc 11>, <&cpu1_intc 9>,
149 <&cpu2_intc 11>, <&cpu2_intc 9>,
150 <&cpu3_intc 11>, <&cpu3_intc 9>;
151 interrupt-controller;
152 #address-cells = <0>;
153 #interrupt-cells = <2>;
154 riscv,ndev = <240>;
155 };
156
157 clint: timer@ffdc000000 {
158 compatible = "thead,th1520-clint", "thead,c900-clint";
159 reg = <0xff 0xdc000000 0x0 0x00010000>;
160 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
161 <&cpu1_intc 3>, <&cpu1_intc 7>,
162 <&cpu2_intc 3>, <&cpu2_intc 7>,
163 <&cpu3_intc 3>, <&cpu3_intc 7>;
164 };
165
166 uart0: serial@ffe7014000 {
167 compatible = "snps,dw-apb-uart";
168 reg = <0xff 0xe7014000 0x0 0x100>;
169 interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
170 clocks = <&uart_sclk>;
171 reg-shift = <2>;
172 reg-io-width = <4>;
173 status = "disabled";
174 };
175
176 uart1: serial@ffe7f00000 {
177 compatible = "snps,dw-apb-uart";
178 reg = <0xff 0xe7f00000 0x0 0x100>;
179 interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
180 clocks = <&uart_sclk>;
181 reg-shift = <2>;
182 reg-io-width = <4>;
183 status = "disabled";
184 };
185
186 uart3: serial@ffe7f04000 {
187 compatible = "snps,dw-apb-uart";
188 reg = <0xff 0xe7f04000 0x0 0x100>;
189 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&uart_sclk>;
191 reg-shift = <2>;
192 reg-io-width = <4>;
193 status = "disabled";
194 };
195
196 gpio2: gpio@ffe7f34000 {
197 compatible = "snps,dw-apb-gpio";
198 reg = <0xff 0xe7f34000 0x0 0x1000>;
199 #address-cells = <1>;
200 #size-cells = <0>;
201
202 portc: gpio-controller@0 {
203 compatible = "snps,dw-apb-gpio-port";
204 gpio-controller;
205 #gpio-cells = <2>;
206 ngpios = <32>;
207 reg = <0>;
208 interrupt-controller;
209 #interrupt-cells = <2>;
210 interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
211 };
212 };
213
214 gpio3: gpio@ffe7f38000 {
215 compatible = "snps,dw-apb-gpio";
216 reg = <0xff 0xe7f38000 0x0 0x1000>;
217 #address-cells = <1>;
218 #size-cells = <0>;
219
220 portd: gpio-controller@0 {
221 compatible = "snps,dw-apb-gpio-port";
222 gpio-controller;
223 #gpio-cells = <2>;
224 ngpios = <32>;
225 reg = <0>;
226 interrupt-controller;
227 #interrupt-cells = <2>;
228 interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
229 };
230 };
231
232 gpio0: gpio@ffec005000 {
233 compatible = "snps,dw-apb-gpio";
234 reg = <0xff 0xec005000 0x0 0x1000>;
235 #address-cells = <1>;
236 #size-cells = <0>;
237
238 porta: gpio-controller@0 {
239 compatible = "snps,dw-apb-gpio-port";
240 gpio-controller;
241 #gpio-cells = <2>;
242 ngpios = <32>;
243 reg = <0>;
244 interrupt-controller;
245 #interrupt-cells = <2>;
246 interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
247 };
248 };
249
250 gpio1: gpio@ffec006000 {
251 compatible = "snps,dw-apb-gpio";
252 reg = <0xff 0xec006000 0x0 0x1000>;
253 #address-cells = <1>;
254 #size-cells = <0>;
255
256 portb: gpio-controller@0 {
257 compatible = "snps,dw-apb-gpio-port";
258 gpio-controller;
259 #gpio-cells = <2>;
260 ngpios = <32>;
261 reg = <0>;
262 interrupt-controller;
263 #interrupt-cells = <2>;
264 interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
265 };
266 };
267
268 uart2: serial@ffec010000 {
269 compatible = "snps,dw-apb-uart";
270 reg = <0xff 0xec010000 0x0 0x4000>;
271 interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
272 clocks = <&uart_sclk>;
273 reg-shift = <2>;
274 reg-io-width = <4>;
275 status = "disabled";
276 };
277
278 timer0: timer@ffefc32000 {
279 compatible = "snps,dw-apb-timer";
280 reg = <0xff 0xefc32000 0x0 0x14>;
281 clocks = <&apb_clk>;
282 clock-names = "timer";
283 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
284 status = "disabled";
285 };
286
287 timer1: timer@ffefc32014 {
288 compatible = "snps,dw-apb-timer";
289 reg = <0xff 0xefc32014 0x0 0x14>;
290 clocks = <&apb_clk>;
291 clock-names = "timer";
292 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
293 status = "disabled";
294 };
295
296 timer2: timer@ffefc32028 {
297 compatible = "snps,dw-apb-timer";
298 reg = <0xff 0xefc32028 0x0 0x14>;
299 clocks = <&apb_clk>;
300 clock-names = "timer";
301 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
302 status = "disabled";
303 };
304
305 timer3: timer@ffefc3203c {
306 compatible = "snps,dw-apb-timer";
307 reg = <0xff 0xefc3203c 0x0 0x14>;
308 clocks = <&apb_clk>;
309 clock-names = "timer";
310 interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
311 status = "disabled";
312 };
313
314 uart4: serial@fff7f08000 {
315 compatible = "snps,dw-apb-uart";
316 reg = <0xff 0xf7f08000 0x0 0x4000>;
317 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&uart_sclk>;
319 reg-shift = <2>;
320 reg-io-width = <4>;
321 status = "disabled";
322 };
323
324 uart5: serial@fff7f0c000 {
325 compatible = "snps,dw-apb-uart";
326 reg = <0xff 0xf7f0c000 0x0 0x4000>;
327 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&uart_sclk>;
329 reg-shift = <2>;
330 reg-io-width = <4>;
331 status = "disabled";
332 };
333
334 timer4: timer@ffffc33000 {
335 compatible = "snps,dw-apb-timer";
336 reg = <0xff 0xffc33000 0x0 0x14>;
337 clocks = <&apb_clk>;
338 clock-names = "timer";
339 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
340 status = "disabled";
341 };
342
343 timer5: timer@ffffc33014 {
344 compatible = "snps,dw-apb-timer";
345 reg = <0xff 0xffc33014 0x0 0x14>;
346 clocks = <&apb_clk>;
347 clock-names = "timer";
348 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
349 status = "disabled";
350 };
351
352 timer6: timer@ffffc33028 {
353 compatible = "snps,dw-apb-timer";
354 reg = <0xff 0xffc33028 0x0 0x14>;
355 clocks = <&apb_clk>;
356 clock-names = "timer";
357 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
358 status = "disabled";
359 };
360
361 timer7: timer@ffffc3303c {
362 compatible = "snps,dw-apb-timer";
363 reg = <0xff 0xffc3303c 0x0 0x14>;
364 clocks = <&apb_clk>;
365 clock-names = "timer";
366 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
367 status = "disabled";
368 };
369
370 ao_gpio0: gpio@fffff41000 {
371 compatible = "snps,dw-apb-gpio";
372 reg = <0xff 0xfff41000 0x0 0x1000>;
373 #address-cells = <1>;
374 #size-cells = <0>;
375
376 porte: gpio-controller@0 {
377 compatible = "snps,dw-apb-gpio-port";
378 gpio-controller;
379 #gpio-cells = <2>;
380 ngpios = <32>;
381 reg = <0>;
382 interrupt-controller;
383 #interrupt-cells = <2>;
384 interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
385 };
386 };
387
388 ao_gpio1: gpio@fffff52000 {
389 compatible = "snps,dw-apb-gpio";
390 reg = <0xff 0xfff52000 0x0 0x1000>;
391 #address-cells = <1>;
392 #size-cells = <0>;
393
394 portf: gpio-controller@0 {
395 compatible = "snps,dw-apb-gpio-port";
396 gpio-controller;
397 #gpio-cells = <2>;
398 ngpios = <32>;
399 reg = <0>;
400 interrupt-controller;
401 #interrupt-cells = <2>;
402 interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
403 };
404 };
405 };
406};