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git01.mediatek.com / filogic / uboot / a1b1fd1730d3208da2e7bf5485e47296d8f311b3 / . / arch / mips / mach-octeon / include / mach / cvmx-gmxx-defs.h
blob: 8231fef220e74605307e8d9f9bb1c7d4fdc8c4d5 [file] [log] [blame]
Aaron Williams3b392a92020-12-11 17:05:33 +0100[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2020 Marvell International Ltd.
4 *
5 * Configuration and status register (CSR) type definitions for
6 * Octeon gmxx.
7 */
8
9#ifndef __CVMX_GMXX_DEFS_H__
10#define __CVMX_GMXX_DEFS_H__
11
12static inline u64 CVMX_GMXX_BAD_REG(unsigned long offset)
13{
14 switch (cvmx_get_octeon_family()) {
15 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
16 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
17 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
18 return 0x0001180008000518ull + (offset) * 0x8000000ull;
19 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
20 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
21 return 0x0001180008000518ull + (offset) * 0x8000000ull;
22 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
23 return 0x0001180008000518ull + (offset) * 0x1000000ull;
24 }
25 return 0x0001180008000518ull + (offset) * 0x8000000ull;
26}
27
28static inline u64 CVMX_GMXX_BIST(unsigned long offset)
29{
30 switch (cvmx_get_octeon_family()) {
31 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
32 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
33 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
34 return 0x0001180008000400ull + (offset) * 0x8000000ull;
35 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
36 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
37 return 0x0001180008000400ull + (offset) * 0x8000000ull;
38 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
39 return 0x0001180008000400ull + (offset) * 0x1000000ull;
40 }
41 return 0x0001180008000400ull + (offset) * 0x8000000ull;
42}
43
44#define CVMX_GMXX_BPID_MAPX(offset, block_id) \
45 (0x0001180008000680ull + (((offset) & 15) + ((block_id) & 7) * 0x200000ull) * 8)
46#define CVMX_GMXX_BPID_MSK(offset) (0x0001180008000700ull + ((offset) & 7) * 0x1000000ull)
47static inline u64 CVMX_GMXX_CLK_EN(unsigned long offset)
48{
49 switch (cvmx_get_octeon_family()) {
50 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
51 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
52 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
53 return 0x00011800080007F0ull + (offset) * 0x8000000ull;
54 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
55 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
56 return 0x00011800080007F0ull + (offset) * 0x8000000ull;
57 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
58 return 0x00011800080007F0ull + (offset) * 0x1000000ull;
59 }
60 return 0x00011800080007F0ull + (offset) * 0x8000000ull;
61}
62
63#define CVMX_GMXX_EBP_DIS(offset) (0x0001180008000608ull + ((offset) & 7) * 0x1000000ull)
64#define CVMX_GMXX_EBP_MSK(offset) (0x0001180008000600ull + ((offset) & 7) * 0x1000000ull)
65static inline u64 CVMX_GMXX_HG2_CONTROL(unsigned long offset)
66{
67 switch (cvmx_get_octeon_family()) {
68 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
69 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
70 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
71 return 0x0001180008000550ull + (offset) * 0x8000000ull;
72 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
73 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
74 return 0x0001180008000550ull + (offset) * 0x8000000ull;
75 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
76 return 0x0001180008000550ull + (offset) * 0x1000000ull;
77 }
78 return 0x0001180008000550ull + (offset) * 0x8000000ull;
79}
80
81static inline u64 CVMX_GMXX_INF_MODE(unsigned long offset)
82{
83 switch (cvmx_get_octeon_family()) {
84 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
85 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
86 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
87 return 0x00011800080007F8ull + (offset) * 0x8000000ull;
88 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
89 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
90 return 0x00011800080007F8ull + (offset) * 0x8000000ull;
91 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
92 return 0x00011800080007F8ull + (offset) * 0x1000000ull;
93 }
94 return 0x00011800080007F8ull + (offset) * 0x8000000ull;
95}
96
97static inline u64 CVMX_GMXX_NXA_ADR(unsigned long offset)
98{
99 switch (cvmx_get_octeon_family()) {
100 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
101 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
102 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
103 return 0x0001180008000510ull + (offset) * 0x8000000ull;
104 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
105 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
106 return 0x0001180008000510ull + (offset) * 0x8000000ull;
107 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
108 return 0x0001180008000510ull + (offset) * 0x1000000ull;
109 }
110 return 0x0001180008000510ull + (offset) * 0x8000000ull;
111}
112
113#define CVMX_GMXX_PIPE_STATUS(offset) (0x0001180008000760ull + ((offset) & 7) * 0x1000000ull)
114static inline u64 CVMX_GMXX_PRTX_CBFC_CTL(unsigned long __attribute__((unused)) offset,
115 unsigned long block_id)
116{
117 switch (cvmx_get_octeon_family()) {
118 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
119 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
120 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
121 return 0x0001180008000580ull + (block_id) * 0x8000000ull;
122 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
123 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
124 return 0x0001180008000580ull + (block_id) * 0x8000000ull;
125 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
126 return 0x0001180008000580ull + (block_id) * 0x1000000ull;
127 }
128 return 0x0001180008000580ull + (block_id) * 0x8000000ull;
129}
130
131static inline u64 CVMX_GMXX_PRTX_CFG(unsigned long offset, unsigned long block_id)
132{
133 switch (cvmx_get_octeon_family()) {
134 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
135 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
136 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
137 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
138 return 0x0001180008000010ull + ((offset) + (block_id) * 0x10000ull) * 2048;
139 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
140 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
141 return 0x0001180008000010ull + ((offset) + (block_id) * 0x2000ull) * 2048;
142 }
143 return 0x0001180008000010ull + ((offset) + (block_id) * 0x10000ull) * 2048;
144}
145
146#define CVMX_GMXX_QSGMII_CTL(offset) (0x0001180008000760ull + ((offset) & 1) * 0x8000000ull)
147static inline u64 CVMX_GMXX_RXAUI_CTL(unsigned long offset)
148{
149 switch (cvmx_get_octeon_family()) {
150 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
151 return 0x0001180008000740ull + (offset) * 0x8000000ull;
152 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
153 return 0x0001180008000740ull + (offset) * 0x1000000ull;
154 }
155 return 0x0001180008000740ull + (offset) * 0x8000000ull;
156}
157
158static inline u64 CVMX_GMXX_RXX_ADR_CAM0(unsigned long offset, unsigned long block_id)
159{
160 switch (cvmx_get_octeon_family()) {
161 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
162 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
163 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
164 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
165 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
166 return 0x0001180008000180ull + ((offset) + (block_id) * 0x10000ull) * 2048;
167 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
168 return 0x0001180008000180ull + ((offset) + (block_id) * 0x2000ull) * 2048;
169 }
170 return 0x0001180008000180ull + ((offset) + (block_id) * 0x10000ull) * 2048;
171}
172
173static inline u64 CVMX_GMXX_RXX_ADR_CAM1(unsigned long offset, unsigned long block_id)
174{
175 switch (cvmx_get_octeon_family()) {
176 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
177 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
178 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
179 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
180 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
181 return 0x0001180008000188ull + ((offset) + (block_id) * 0x10000ull) * 2048;
182 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
183 return 0x0001180008000188ull + ((offset) + (block_id) * 0x2000ull) * 2048;
184 }
185 return 0x0001180008000188ull + ((offset) + (block_id) * 0x10000ull) * 2048;
186}
187
188static inline u64 CVMX_GMXX_RXX_ADR_CAM2(unsigned long offset, unsigned long block_id)
189{
190 switch (cvmx_get_octeon_family()) {
191 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
192 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
193 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
194 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
195 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
196 return 0x0001180008000190ull + ((offset) + (block_id) * 0x10000ull) * 2048;
197 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
198 return 0x0001180008000190ull + ((offset) + (block_id) * 0x2000ull) * 2048;
199 }
200 return 0x0001180008000190ull + ((offset) + (block_id) * 0x10000ull) * 2048;
201}
202
203static inline u64 CVMX_GMXX_RXX_ADR_CAM3(unsigned long offset, unsigned long block_id)
204{
205 switch (cvmx_get_octeon_family()) {
206 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
207 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
208 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
209 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
210 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
211 return 0x0001180008000198ull + ((offset) + (block_id) * 0x10000ull) * 2048;
212 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
213 return 0x0001180008000198ull + ((offset) + (block_id) * 0x2000ull) * 2048;
214 }
215 return 0x0001180008000198ull + ((offset) + (block_id) * 0x10000ull) * 2048;
216}
217
218static inline u64 CVMX_GMXX_RXX_ADR_CAM4(unsigned long offset, unsigned long block_id)
219{
220 switch (cvmx_get_octeon_family()) {
221 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
222 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
223 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
224 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
225 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
226 return 0x00011800080001A0ull + ((offset) + (block_id) * 0x10000ull) * 2048;
227 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
228 return 0x00011800080001A0ull + ((offset) + (block_id) * 0x2000ull) * 2048;
229 }
230 return 0x00011800080001A0ull + ((offset) + (block_id) * 0x10000ull) * 2048;
231}
232
233static inline u64 CVMX_GMXX_RXX_ADR_CAM5(unsigned long offset, unsigned long block_id)
234{
235 switch (cvmx_get_octeon_family()) {
236 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
237 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
238 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
239 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
240 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
241 return 0x00011800080001A8ull + ((offset) + (block_id) * 0x10000ull) * 2048;
242 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
243 return 0x00011800080001A8ull + ((offset) + (block_id) * 0x2000ull) * 2048;
244 }
245 return 0x00011800080001A8ull + ((offset) + (block_id) * 0x10000ull) * 2048;
246}
247
248static inline u64 CVMX_GMXX_RXX_ADR_CAM_ALL_EN(unsigned long offset, unsigned long block_id)
249{
250 switch (cvmx_get_octeon_family()) {
251 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
252 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
253 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
254 return 0x0001180008000110ull + ((offset) + (block_id) * 0x10000ull) * 2048;
255 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
256 return 0x0001180008000110ull + ((offset) + (block_id) * 0x10000ull) * 2048;
257 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
258 return 0x0001180008000110ull + ((offset) + (block_id) * 0x2000ull) * 2048;
259 }
260 return 0x0001180008000110ull + ((offset) + (block_id) * 0x10000ull) * 2048;
261}
262
263static inline u64 CVMX_GMXX_RXX_ADR_CAM_EN(unsigned long offset, unsigned long block_id)
264{
265 switch (cvmx_get_octeon_family()) {
266 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
267 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
268 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
269 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
270 return 0x0001180008000108ull + ((offset) + (block_id) * 0x10000ull) * 2048;
271 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
272 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
273 return 0x0001180008000108ull + ((offset) + (block_id) * 0x2000ull) * 2048;
274 }
275 return 0x0001180008000108ull + ((offset) + (block_id) * 0x10000ull) * 2048;
276}
277
278static inline u64 CVMX_GMXX_RXX_ADR_CTL(unsigned long offset, unsigned long block_id)
279{
280 switch (cvmx_get_octeon_family()) {
281 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
282 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
283 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
284 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
285 return 0x0001180008000100ull + ((offset) + (block_id) * 0x10000ull) * 2048;
286 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
287 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
288 return 0x0001180008000100ull + ((offset) + (block_id) * 0x2000ull) * 2048;
289 }
290 return 0x0001180008000100ull + ((offset) + (block_id) * 0x10000ull) * 2048;
291}
292
293static inline u64 CVMX_GMXX_RXX_DECISION(unsigned long offset, unsigned long block_id)
294{
295 switch (cvmx_get_octeon_family()) {
296 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
297 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
298 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
299 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
300 return 0x0001180008000040ull + ((offset) + (block_id) * 0x10000ull) * 2048;
301 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
302 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
303 return 0x0001180008000040ull + ((offset) + (block_id) * 0x2000ull) * 2048;
304 }
305 return 0x0001180008000040ull + ((offset) + (block_id) * 0x10000ull) * 2048;
306}
307
308static inline u64 CVMX_GMXX_RXX_FRM_CHK(unsigned long offset, unsigned long block_id)
309{
310 switch (cvmx_get_octeon_family()) {
311 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
312 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
313 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
314 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
315 return 0x0001180008000020ull + ((offset) + (block_id) * 0x10000ull) * 2048;
316 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
317 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
318 return 0x0001180008000020ull + ((offset) + (block_id) * 0x2000ull) * 2048;
319 }
320 return 0x0001180008000020ull + ((offset) + (block_id) * 0x10000ull) * 2048;
321}
322
323static inline u64 CVMX_GMXX_RXX_FRM_CTL(unsigned long offset, unsigned long block_id)
324{
325 switch (cvmx_get_octeon_family()) {
326 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
327 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
328 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
329 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
330 return 0x0001180008000018ull + ((offset) + (block_id) * 0x10000ull) * 2048;
331 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
332 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
333 return 0x0001180008000018ull + ((offset) + (block_id) * 0x2000ull) * 2048;
334 }
335 return 0x0001180008000018ull + ((offset) + (block_id) * 0x10000ull) * 2048;
336}
337
338#define CVMX_GMXX_RXX_FRM_MAX(offset, block_id) \
339 (0x0001180008000030ull + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
340#define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) \
341 (0x0001180008000028ull + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
342static inline u64 CVMX_GMXX_RXX_IFG(unsigned long offset, unsigned long block_id)
343{
344 switch (cvmx_get_octeon_family()) {
345 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
346 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
347 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
348 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
349 return 0x0001180008000058ull + ((offset) + (block_id) * 0x10000ull) * 2048;
350 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
351 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
352 return 0x0001180008000058ull + ((offset) + (block_id) * 0x2000ull) * 2048;
353 }
354 return 0x0001180008000058ull + ((offset) + (block_id) * 0x10000ull) * 2048;
355}
356
357static inline u64 CVMX_GMXX_RXX_INT_EN(unsigned long offset, unsigned long block_id)
358{
359 switch (cvmx_get_octeon_family()) {
360 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
361 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
362 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
363 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
364 return 0x0001180008000008ull + ((offset) + (block_id) * 0x10000ull) * 2048;
365 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
366 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
367 return 0x0001180008000008ull + ((offset) + (block_id) * 0x2000ull) * 2048;
368 }
369 return 0x0001180008000008ull + ((offset) + (block_id) * 0x10000ull) * 2048;
370}
371
372static inline u64 CVMX_GMXX_RXX_INT_REG(unsigned long offset, unsigned long block_id)
373{
374 switch (cvmx_get_octeon_family()) {
375 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
376 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
377 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
378 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
379 return 0x0001180008000000ull + ((offset) + (block_id) * 0x10000ull) * 2048;
380 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
381 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
382 return 0x0001180008000000ull + ((offset) + (block_id) * 0x2000ull) * 2048;
383 }
384 return 0x0001180008000000ull + ((offset) + (block_id) * 0x10000ull) * 2048;
385}
386
387static inline u64 CVMX_GMXX_RXX_JABBER(unsigned long offset, unsigned long block_id)
388{
389 switch (cvmx_get_octeon_family()) {
390 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
391 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
392 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
393 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
394 return 0x0001180008000038ull + ((offset) + (block_id) * 0x10000ull) * 2048;
395 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
396 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
397 return 0x0001180008000038ull + ((offset) + (block_id) * 0x2000ull) * 2048;
398 }
399 return 0x0001180008000038ull + ((offset) + (block_id) * 0x10000ull) * 2048;
400}
401
402static inline u64 CVMX_GMXX_RXX_PAUSE_DROP_TIME(unsigned long offset, unsigned long block_id)
403{
404 switch (cvmx_get_octeon_family()) {
405 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
406 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
407 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
408 return 0x0001180008000068ull + ((offset) + (block_id) * 0x10000ull) * 2048;
409 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
410 return 0x0001180008000068ull + ((offset) + (block_id) * 0x10000ull) * 2048;
411 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
412 return 0x0001180008000068ull + ((offset) + (block_id) * 0x10000ull) * 2048;
413 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
414 return 0x0001180008000068ull + ((offset) + (block_id) * 0x2000ull) * 2048;
415 }
416 return 0x0001180008000068ull + ((offset) + (block_id) * 0x10000ull) * 2048;
417}
418
419#define CVMX_GMXX_RXX_RX_INBND(offset, block_id) \
420 (0x0001180008000060ull + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
421static inline u64 CVMX_GMXX_RXX_STATS_CTL(unsigned long offset, unsigned long block_id)
422{
423 switch (cvmx_get_octeon_family()) {
424 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
425 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
426 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
427 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
428 return 0x0001180008000050ull + ((offset) + (block_id) * 0x10000ull) * 2048;
429 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
430 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
431 return 0x0001180008000050ull + ((offset) + (block_id) * 0x2000ull) * 2048;
432 }
433 return 0x0001180008000050ull + ((offset) + (block_id) * 0x10000ull) * 2048;
434}
435
436static inline u64 CVMX_GMXX_RXX_STATS_OCTS(unsigned long offset, unsigned long block_id)
437{
438 switch (cvmx_get_octeon_family()) {
439 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
440 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
441 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
442 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
443 return 0x0001180008000088ull + ((offset) + (block_id) * 0x10000ull) * 2048;
444 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
445 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
446 return 0x0001180008000088ull + ((offset) + (block_id) * 0x2000ull) * 2048;
447 }
448 return 0x0001180008000088ull + ((offset) + (block_id) * 0x10000ull) * 2048;
449}
450
451static inline u64 CVMX_GMXX_RXX_STATS_OCTS_CTL(unsigned long offset, unsigned long block_id)
452{
453 switch (cvmx_get_octeon_family()) {
454 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
455 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
456 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
457 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
458 return 0x0001180008000098ull + ((offset) + (block_id) * 0x10000ull) * 2048;
459 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
460 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
461 return 0x0001180008000098ull + ((offset) + (block_id) * 0x2000ull) * 2048;
462 }
463 return 0x0001180008000098ull + ((offset) + (block_id) * 0x10000ull) * 2048;
464}
465
466static inline u64 CVMX_GMXX_RXX_STATS_OCTS_DMAC(unsigned long offset, unsigned long block_id)
467{
468 switch (cvmx_get_octeon_family()) {
469 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
470 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
471 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
472 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
473 return 0x00011800080000A8ull + ((offset) + (block_id) * 0x10000ull) * 2048;
474 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
475 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
476 return 0x00011800080000A8ull + ((offset) + (block_id) * 0x2000ull) * 2048;
477 }
478 return 0x00011800080000A8ull + ((offset) + (block_id) * 0x10000ull) * 2048;
479}
480
481static inline u64 CVMX_GMXX_RXX_STATS_OCTS_DRP(unsigned long offset, unsigned long block_id)
482{
483 switch (cvmx_get_octeon_family()) {
484 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
485 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
486 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
487 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
488 return 0x00011800080000B8ull + ((offset) + (block_id) * 0x10000ull) * 2048;
489 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
490 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
491 return 0x00011800080000B8ull + ((offset) + (block_id) * 0x2000ull) * 2048;
492 }
493 return 0x00011800080000B8ull + ((offset) + (block_id) * 0x10000ull) * 2048;
494}
495
496static inline u64 CVMX_GMXX_RXX_STATS_PKTS(unsigned long offset, unsigned long block_id)
497{
498 switch (cvmx_get_octeon_family()) {
499 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
500 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
501 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
502 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
503 return 0x0001180008000080ull + ((offset) + (block_id) * 0x10000ull) * 2048;
504 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
505 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
506 return 0x0001180008000080ull + ((offset) + (block_id) * 0x2000ull) * 2048;
507 }
508 return 0x0001180008000080ull + ((offset) + (block_id) * 0x10000ull) * 2048;
509}
510
511static inline u64 CVMX_GMXX_RXX_STATS_PKTS_BAD(unsigned long offset, unsigned long block_id)
512{
513 switch (cvmx_get_octeon_family()) {
514 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
515 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
516 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
517 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
518 return 0x00011800080000C0ull + ((offset) + (block_id) * 0x10000ull) * 2048;
519 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
520 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
521 return 0x00011800080000C0ull + ((offset) + (block_id) * 0x2000ull) * 2048;
522 }
523 return 0x00011800080000C0ull + ((offset) + (block_id) * 0x10000ull) * 2048;
524}
525
526static inline u64 CVMX_GMXX_RXX_STATS_PKTS_CTL(unsigned long offset, unsigned long block_id)
527{
528 switch (cvmx_get_octeon_family()) {
529 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
530 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
531 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
532 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
533 return 0x0001180008000090ull + ((offset) + (block_id) * 0x10000ull) * 2048;
534 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
535 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
536 return 0x0001180008000090ull + ((offset) + (block_id) * 0x2000ull) * 2048;
537 }
538 return 0x0001180008000090ull + ((offset) + (block_id) * 0x10000ull) * 2048;
539}
540
541static inline u64 CVMX_GMXX_RXX_STATS_PKTS_DMAC(unsigned long offset, unsigned long block_id)
542{
543 switch (cvmx_get_octeon_family()) {
544 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
545 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
546 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
547 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
548 return 0x00011800080000A0ull + ((offset) + (block_id) * 0x10000ull) * 2048;
549 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
550 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
551 return 0x00011800080000A0ull + ((offset) + (block_id) * 0x2000ull) * 2048;
552 }
553 return 0x00011800080000A0ull + ((offset) + (block_id) * 0x10000ull) * 2048;
554}
555
556static inline u64 CVMX_GMXX_RXX_STATS_PKTS_DRP(unsigned long offset, unsigned long block_id)
557{
558 switch (cvmx_get_octeon_family()) {
559 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
560 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
561 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
562 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
563 return 0x00011800080000B0ull + ((offset) + (block_id) * 0x10000ull) * 2048;
564 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
565 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
566 return 0x00011800080000B0ull + ((offset) + (block_id) * 0x2000ull) * 2048;
567 }
568 return 0x00011800080000B0ull + ((offset) + (block_id) * 0x10000ull) * 2048;
569}
570
571static inline u64 CVMX_GMXX_RXX_UDD_SKP(unsigned long offset, unsigned long block_id)
572{
573 switch (cvmx_get_octeon_family()) {
574 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
575 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
576 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
577 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
578 return 0x0001180008000048ull + ((offset) + (block_id) * 0x10000ull) * 2048;
579 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
580 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
581 return 0x0001180008000048ull + ((offset) + (block_id) * 0x2000ull) * 2048;
582 }
583 return 0x0001180008000048ull + ((offset) + (block_id) * 0x10000ull) * 2048;
584}
585
586static inline u64 CVMX_GMXX_RX_BP_DROPX(unsigned long offset, unsigned long block_id)
587{
588 switch (cvmx_get_octeon_family()) {
589 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
590 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
591 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
592 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
593 return 0x0001180008000420ull + ((offset) + (block_id) * 0x1000000ull) * 8;
594 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
595 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
596 return 0x0001180008000420ull + ((offset) + (block_id) * 0x200000ull) * 8;
597 }
598 return 0x0001180008000420ull + ((offset) + (block_id) * 0x1000000ull) * 8;
599}
600
601static inline u64 CVMX_GMXX_RX_BP_OFFX(unsigned long offset, unsigned long block_id)
602{
603 switch (cvmx_get_octeon_family()) {
604 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
605 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
606 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
607 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
608 return 0x0001180008000460ull + ((offset) + (block_id) * 0x1000000ull) * 8;
609 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
610 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
611 return 0x0001180008000460ull + ((offset) + (block_id) * 0x200000ull) * 8;
612 }
613 return 0x0001180008000460ull + ((offset) + (block_id) * 0x1000000ull) * 8;
614}
615
616static inline u64 CVMX_GMXX_RX_BP_ONX(unsigned long offset, unsigned long block_id)
617{
618 switch (cvmx_get_octeon_family()) {
619 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
620 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
621 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
622 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
623 return 0x0001180008000440ull + ((offset) + (block_id) * 0x1000000ull) * 8;
624 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
625 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
626 return 0x0001180008000440ull + ((offset) + (block_id) * 0x200000ull) * 8;
627 }
628 return 0x0001180008000440ull + ((offset) + (block_id) * 0x1000000ull) * 8;
629}
630
631static inline u64 CVMX_GMXX_RX_HG2_STATUS(unsigned long offset)
632{
633 switch (cvmx_get_octeon_family()) {
634 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
635 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
636 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
637 return 0x0001180008000548ull + (offset) * 0x8000000ull;
638 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
639 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
640 return 0x0001180008000548ull + (offset) * 0x8000000ull;
641 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
642 return 0x0001180008000548ull + (offset) * 0x1000000ull;
643 }
644 return 0x0001180008000548ull + (offset) * 0x8000000ull;
645}
646
647#define CVMX_GMXX_RX_PASS_EN(offset) (0x00011800080005F8ull + ((offset) & 1) * 0x8000000ull)
648#define CVMX_GMXX_RX_PASS_MAPX(offset, block_id) \
649 (0x0001180008000600ull + (((offset) & 15) + ((block_id) & 1) * 0x1000000ull) * 8)
650static inline u64 CVMX_GMXX_RX_PRTS(unsigned long offset)
651{
652 switch (cvmx_get_octeon_family()) {
653 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
654 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
655 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
656 return 0x0001180008000410ull + (offset) * 0x8000000ull;
657 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
658 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
659 return 0x0001180008000410ull + (offset) * 0x8000000ull;
660 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
661 return 0x0001180008000410ull + (offset) * 0x1000000ull;
662 }
663 return 0x0001180008000410ull + (offset) * 0x8000000ull;
664}
665
666static inline u64 CVMX_GMXX_RX_PRT_INFO(unsigned long offset)
667{
668 switch (cvmx_get_octeon_family()) {
669 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
670 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
671 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
672 return 0x00011800080004E8ull + (offset) * 0x8000000ull;
673 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
674 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
675 return 0x00011800080004E8ull + (offset) * 0x8000000ull;
676 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
677 return 0x00011800080004E8ull + (offset) * 0x1000000ull;
678 }
679 return 0x00011800080004E8ull + (offset) * 0x8000000ull;
680}
681
682#define CVMX_GMXX_RX_TX_STATUS(offset) (0x00011800080007E8ull)
683static inline u64 CVMX_GMXX_RX_XAUI_BAD_COL(unsigned long offset)
684{
685 switch (cvmx_get_octeon_family()) {
686 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
687 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
688 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
689 return 0x0001180008000538ull + (offset) * 0x8000000ull;
690 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
691 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
692 return 0x0001180008000538ull + (offset) * 0x8000000ull;
693 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
694 return 0x0001180008000538ull + (offset) * 0x1000000ull;
695 }
696 return 0x0001180008000538ull + (offset) * 0x8000000ull;
697}
698
699static inline u64 CVMX_GMXX_RX_XAUI_CTL(unsigned long offset)
700{
701 switch (cvmx_get_octeon_family()) {
702 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
703 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
704 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
705 return 0x0001180008000530ull + (offset) * 0x8000000ull;
706 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
707 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
708 return 0x0001180008000530ull + (offset) * 0x8000000ull;
709 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
710 return 0x0001180008000530ull + (offset) * 0x1000000ull;
711 }
712 return 0x0001180008000530ull + (offset) * 0x8000000ull;
713}
714
715static inline u64 CVMX_GMXX_SMACX(unsigned long offset, unsigned long block_id)
716{
717 switch (cvmx_get_octeon_family()) {
718 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
719 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
720 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
721 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
722 return 0x0001180008000230ull + ((offset) + (block_id) * 0x10000ull) * 2048;
723 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
724 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
725 return 0x0001180008000230ull + ((offset) + (block_id) * 0x2000ull) * 2048;
726 }
727 return 0x0001180008000230ull + ((offset) + (block_id) * 0x10000ull) * 2048;
728}
729
730static inline u64 CVMX_GMXX_SOFT_BIST(unsigned long offset)
731{
732 switch (cvmx_get_octeon_family()) {
733 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
734 return 0x00011800080007E8ull + (offset) * 0x8000000ull;
735 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
736 return 0x00011800080007E8ull + (offset) * 0x8000000ull;
737 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
738 return 0x00011800080007E8ull + (offset) * 0x1000000ull;
739 }
740 return 0x00011800080007E8ull + (offset) * 0x1000000ull;
741}
742
743static inline u64 CVMX_GMXX_STAT_BP(unsigned long offset)
744{
745 switch (cvmx_get_octeon_family()) {
746 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
747 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
748 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
749 return 0x0001180008000520ull + (offset) * 0x8000000ull;
750 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
751 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
752 return 0x0001180008000520ull + (offset) * 0x8000000ull;
753 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
754 return 0x0001180008000520ull + (offset) * 0x1000000ull;
755 }
756 return 0x0001180008000520ull + (offset) * 0x8000000ull;
757}
758
759static inline u64 CVMX_GMXX_TB_REG(unsigned long offset)
760{
761 switch (cvmx_get_octeon_family()) {
762 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
763 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
764 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
765 return 0x00011800080007E0ull + (offset) * 0x8000000ull;
766 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
767 return 0x00011800080007E0ull + (offset) * 0x8000000ull;
768 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
769 return 0x00011800080007E0ull + (offset) * 0x1000000ull;
770 }
771 return 0x00011800080007E0ull + (offset) * 0x8000000ull;
772}
773
774static inline u64 CVMX_GMXX_TXX_APPEND(unsigned long offset, unsigned long block_id)
775{
776 switch (cvmx_get_octeon_family()) {
777 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
778 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
779 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
780 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
781 return 0x0001180008000218ull + ((offset) + (block_id) * 0x10000ull) * 2048;
782 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
783 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
784 return 0x0001180008000218ull + ((offset) + (block_id) * 0x2000ull) * 2048;
785 }
786 return 0x0001180008000218ull + ((offset) + (block_id) * 0x10000ull) * 2048;
787}
788
789#define CVMX_GMXX_TXX_BCK_CRDT(offset, block_id) \
790 (0x0001180008000388ull + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
791static inline u64 CVMX_GMXX_TXX_BURST(unsigned long offset, unsigned long block_id)
792{
793 switch (cvmx_get_octeon_family()) {
794 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
795 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
796 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
797 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
798 return 0x0001180008000228ull + ((offset) + (block_id) * 0x10000ull) * 2048;
799 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
800 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
801 return 0x0001180008000228ull + ((offset) + (block_id) * 0x2000ull) * 2048;
802 }
803 return 0x0001180008000228ull + ((offset) + (block_id) * 0x10000ull) * 2048;
804}
805
806static inline u64 CVMX_GMXX_TXX_CBFC_XOFF(unsigned long __attribute__((unused)) offset,
807 unsigned long block_id)
808{
809 switch (cvmx_get_octeon_family()) {
810 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
811 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
812 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
813 return 0x00011800080005A0ull + (block_id) * 0x8000000ull;
814 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
815 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
816 return 0x00011800080005A0ull + (block_id) * 0x8000000ull;
817 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
818 return 0x00011800080005A0ull + (block_id) * 0x1000000ull;
819 }
820 return 0x00011800080005A0ull + (block_id) * 0x8000000ull;
821}
822
823static inline u64 CVMX_GMXX_TXX_CBFC_XON(unsigned long __attribute__((unused)) offset,
824 unsigned long block_id)
825{
826 switch (cvmx_get_octeon_family()) {
827 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
828 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
829 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
830 return 0x00011800080005C0ull + (block_id) * 0x8000000ull;
831 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
832 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
833 return 0x00011800080005C0ull + (block_id) * 0x8000000ull;
834 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
835 return 0x00011800080005C0ull + (block_id) * 0x1000000ull;
836 }
837 return 0x00011800080005C0ull + (block_id) * 0x8000000ull;
838}
839
840#define CVMX_GMXX_TXX_CLK(offset, block_id) \
841 (0x0001180008000208ull + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
842static inline u64 CVMX_GMXX_TXX_CTL(unsigned long offset, unsigned long block_id)
843{
844 switch (cvmx_get_octeon_family()) {
845 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
846 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
847 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
848 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
849 return 0x0001180008000270ull + ((offset) + (block_id) * 0x10000ull) * 2048;
850 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
851 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
852 return 0x0001180008000270ull + ((offset) + (block_id) * 0x2000ull) * 2048;
853 }
854 return 0x0001180008000270ull + ((offset) + (block_id) * 0x10000ull) * 2048;
855}
856
857#define CVMX_GMXX_TXX_JAM_MODE(offset, block_id) \
858 (0x0001180008000380ull + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
859static inline u64 CVMX_GMXX_TXX_MIN_PKT(unsigned long offset, unsigned long block_id)
860{
861 switch (cvmx_get_octeon_family()) {
862 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
863 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
864 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
865 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
866 return 0x0001180008000240ull + ((offset) + (block_id) * 0x10000ull) * 2048;
867 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
868 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
869 return 0x0001180008000240ull + ((offset) + (block_id) * 0x2000ull) * 2048;
870 }
871 return 0x0001180008000240ull + ((offset) + (block_id) * 0x10000ull) * 2048;
872}
873
874static inline u64 CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset, unsigned long block_id)
875{
876 switch (cvmx_get_octeon_family()) {
877 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
878 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
879 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
880 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
881 return 0x0001180008000248ull + ((offset) + (block_id) * 0x10000ull) * 2048;
882 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
883 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
884 return 0x0001180008000248ull + ((offset) + (block_id) * 0x2000ull) * 2048;
885 }
886 return 0x0001180008000248ull + ((offset) + (block_id) * 0x10000ull) * 2048;
887}
888
889static inline u64 CVMX_GMXX_TXX_PAUSE_PKT_TIME(unsigned long offset, unsigned long block_id)
890{
891 switch (cvmx_get_octeon_family()) {
892 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
893 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
894 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
895 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
896 return 0x0001180008000238ull + ((offset) + (block_id) * 0x10000ull) * 2048;
897 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
898 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
899 return 0x0001180008000238ull + ((offset) + (block_id) * 0x2000ull) * 2048;
900 }
901 return 0x0001180008000238ull + ((offset) + (block_id) * 0x10000ull) * 2048;
902}
903
904static inline u64 CVMX_GMXX_TXX_PAUSE_TOGO(unsigned long offset, unsigned long block_id)
905{
906 switch (cvmx_get_octeon_family()) {
907 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
908 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
909 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
910 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
911 return 0x0001180008000258ull + ((offset) + (block_id) * 0x10000ull) * 2048;
912 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
913 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
914 return 0x0001180008000258ull + ((offset) + (block_id) * 0x2000ull) * 2048;
915 }
916 return 0x0001180008000258ull + ((offset) + (block_id) * 0x10000ull) * 2048;
917}
918
919static inline u64 CVMX_GMXX_TXX_PAUSE_ZERO(unsigned long offset, unsigned long block_id)
920{
921 switch (cvmx_get_octeon_family()) {
922 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
923 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
924 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
925 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
926 return 0x0001180008000260ull + ((offset) + (block_id) * 0x10000ull) * 2048;
927 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
928 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
929 return 0x0001180008000260ull + ((offset) + (block_id) * 0x2000ull) * 2048;
930 }
931 return 0x0001180008000260ull + ((offset) + (block_id) * 0x10000ull) * 2048;
932}
933
934#define CVMX_GMXX_TXX_PIPE(offset, block_id) \
935 (0x0001180008000310ull + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048)
936static inline u64 CVMX_GMXX_TXX_SGMII_CTL(unsigned long offset, unsigned long block_id)
937{
938 switch (cvmx_get_octeon_family()) {
939 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
940 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
941 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
942 return 0x0001180008000300ull + ((offset) + (block_id) * 0x10000ull) * 2048;
943 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
944 return 0x0001180008000300ull + ((offset) + (block_id) * 0x10000ull) * 2048;
945 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
946 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
947 return 0x0001180008000300ull + ((offset) + (block_id) * 0x2000ull) * 2048;
948 }
949 return 0x0001180008000300ull + ((offset) + (block_id) * 0x10000ull) * 2048;
950}
951
952static inline u64 CVMX_GMXX_TXX_SLOT(unsigned long offset, unsigned long block_id)
953{
954 switch (cvmx_get_octeon_family()) {
955 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
956 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
957 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
958 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
959 return 0x0001180008000220ull + ((offset) + (block_id) * 0x10000ull) * 2048;
960 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
961 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
962 return 0x0001180008000220ull + ((offset) + (block_id) * 0x2000ull) * 2048;
963 }
964 return 0x0001180008000220ull + ((offset) + (block_id) * 0x10000ull) * 2048;
965}
966
967static inline u64 CVMX_GMXX_TXX_SOFT_PAUSE(unsigned long offset, unsigned long block_id)
968{
969 switch (cvmx_get_octeon_family()) {
970 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
971 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
972 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
973 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
974 return 0x0001180008000250ull + ((offset) + (block_id) * 0x10000ull) * 2048;
975 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
976 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
977 return 0x0001180008000250ull + ((offset) + (block_id) * 0x2000ull) * 2048;
978 }
979 return 0x0001180008000250ull + ((offset) + (block_id) * 0x10000ull) * 2048;
980}
981
982static inline u64 CVMX_GMXX_TXX_STAT0(unsigned long offset, unsigned long block_id)
983{
984 switch (cvmx_get_octeon_family()) {
985 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
986 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
987 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
988 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
989 return 0x0001180008000280ull + ((offset) + (block_id) * 0x10000ull) * 2048;
990 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
991 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
992 return 0x0001180008000280ull + ((offset) + (block_id) * 0x2000ull) * 2048;
993 }
994 return 0x0001180008000280ull + ((offset) + (block_id) * 0x10000ull) * 2048;
995}
996
997static inline u64 CVMX_GMXX_TXX_STAT1(unsigned long offset, unsigned long block_id)
998{
999 switch (cvmx_get_octeon_family()) {
1000 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1001 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1002 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1003 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1004 return 0x0001180008000288ull + ((offset) + (block_id) * 0x10000ull) * 2048;
1005 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1006 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1007 return 0x0001180008000288ull + ((offset) + (block_id) * 0x2000ull) * 2048;
1008 }
1009 return 0x0001180008000288ull + ((offset) + (block_id) * 0x10000ull) * 2048;
1010}
1011
1012static inline u64 CVMX_GMXX_TXX_STAT2(unsigned long offset, unsigned long block_id)
1013{
1014 switch (cvmx_get_octeon_family()) {
1015 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1016 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1017 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1018 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1019 return 0x0001180008000290ull + ((offset) + (block_id) * 0x10000ull) * 2048;
1020 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1021 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1022 return 0x0001180008000290ull + ((offset) + (block_id) * 0x2000ull) * 2048;
1023 }
1024 return 0x0001180008000290ull + ((offset) + (block_id) * 0x10000ull) * 2048;
1025}
1026
1027static inline u64 CVMX_GMXX_TXX_STAT3(unsigned long offset, unsigned long block_id)
1028{
1029 switch (cvmx_get_octeon_family()) {
1030 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1031 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1032 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1033 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1034 return 0x0001180008000298ull + ((offset) + (block_id) * 0x10000ull) * 2048;
1035 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1036 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1037 return 0x0001180008000298ull + ((offset) + (block_id) * 0x2000ull) * 2048;
1038 }
1039 return 0x0001180008000298ull + ((offset) + (block_id) * 0x10000ull) * 2048;
1040}
1041
1042static inline u64 CVMX_GMXX_TXX_STAT4(unsigned long offset, unsigned long block_id)
1043{
1044 switch (cvmx_get_octeon_family()) {
1045 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1046 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1047 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1048 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1049 return 0x00011800080002A0ull + ((offset) + (block_id) * 0x10000ull) * 2048;
1050 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1051 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1052 return 0x00011800080002A0ull + ((offset) + (block_id) * 0x2000ull) * 2048;
1053 }
1054 return 0x00011800080002A0ull + ((offset) + (block_id) * 0x10000ull) * 2048;
1055}
1056
1057static inline u64 CVMX_GMXX_TXX_STAT5(unsigned long offset, unsigned long block_id)
1058{
1059 switch (cvmx_get_octeon_family()) {
1060 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1061 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1062 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1063 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1064 return 0x00011800080002A8ull + ((offset) + (block_id) * 0x10000ull) * 2048;
1065 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1066 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1067 return 0x00011800080002A8ull + ((offset) + (block_id) * 0x2000ull) * 2048;
1068 }
1069 return 0x00011800080002A8ull + ((offset) + (block_id) * 0x10000ull) * 2048;
1070}
1071
1072static inline u64 CVMX_GMXX_TXX_STAT6(unsigned long offset, unsigned long block_id)
1073{
1074 switch (cvmx_get_octeon_family()) {
1075 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1076 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1077 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1078 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1079 return 0x00011800080002B0ull + ((offset) + (block_id) * 0x10000ull) * 2048;
1080 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1081 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1082 return 0x00011800080002B0ull + ((offset) + (block_id) * 0x2000ull) * 2048;
1083 }
1084 return 0x00011800080002B0ull + ((offset) + (block_id) * 0x10000ull) * 2048;
1085}
1086
1087static inline u64 CVMX_GMXX_TXX_STAT7(unsigned long offset, unsigned long block_id)
1088{
1089 switch (cvmx_get_octeon_family()) {
1090 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1091 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1092 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1093 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1094 return 0x00011800080002B8ull + ((offset) + (block_id) * 0x10000ull) * 2048;
1095 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1096 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1097 return 0x00011800080002B8ull + ((offset) + (block_id) * 0x2000ull) * 2048;
1098 }
1099 return 0x00011800080002B8ull + ((offset) + (block_id) * 0x10000ull) * 2048;
1100}
1101
1102static inline u64 CVMX_GMXX_TXX_STAT8(unsigned long offset, unsigned long block_id)
1103{
1104 switch (cvmx_get_octeon_family()) {
1105 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1106 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1107 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1108 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1109 return 0x00011800080002C0ull + ((offset) + (block_id) * 0x10000ull) * 2048;
1110 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1111 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1112 return 0x00011800080002C0ull + ((offset) + (block_id) * 0x2000ull) * 2048;
1113 }
1114 return 0x00011800080002C0ull + ((offset) + (block_id) * 0x10000ull) * 2048;
1115}
1116
1117static inline u64 CVMX_GMXX_TXX_STAT9(unsigned long offset, unsigned long block_id)
1118{
1119 switch (cvmx_get_octeon_family()) {
1120 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1121 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1122 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1123 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1124 return 0x00011800080002C8ull + ((offset) + (block_id) * 0x10000ull) * 2048;
1125 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1126 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1127 return 0x00011800080002C8ull + ((offset) + (block_id) * 0x2000ull) * 2048;
1128 }
1129 return 0x00011800080002C8ull + ((offset) + (block_id) * 0x10000ull) * 2048;
1130}
1131
1132static inline u64 CVMX_GMXX_TXX_STATS_CTL(unsigned long offset, unsigned long block_id)
1133{
1134 switch (cvmx_get_octeon_family()) {
1135 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1136 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1137 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1138 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1139 return 0x0001180008000268ull + ((offset) + (block_id) * 0x10000ull) * 2048;
1140 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1141 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1142 return 0x0001180008000268ull + ((offset) + (block_id) * 0x2000ull) * 2048;
1143 }
1144 return 0x0001180008000268ull + ((offset) + (block_id) * 0x10000ull) * 2048;
1145}
1146
1147static inline u64 CVMX_GMXX_TXX_THRESH(unsigned long offset, unsigned long block_id)
1148{
1149 switch (cvmx_get_octeon_family()) {
1150 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1151 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1152 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1153 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1154 return 0x0001180008000210ull + ((offset) + (block_id) * 0x10000ull) * 2048;
1155 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1156 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1157 return 0x0001180008000210ull + ((offset) + (block_id) * 0x2000ull) * 2048;
1158 }
1159 return 0x0001180008000210ull + ((offset) + (block_id) * 0x10000ull) * 2048;
1160}
1161
1162static inline u64 CVMX_GMXX_TX_BP(unsigned long offset)
1163{
1164 switch (cvmx_get_octeon_family()) {
1165 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1166 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1167 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1168 return 0x00011800080004D0ull + (offset) * 0x8000000ull;
1169 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1170 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1171 return 0x00011800080004D0ull + (offset) * 0x8000000ull;
1172 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1173 return 0x00011800080004D0ull + (offset) * 0x1000000ull;
1174 }
1175 return 0x00011800080004D0ull + (offset) * 0x8000000ull;
1176}
1177
1178#define CVMX_GMXX_TX_CLK_MSKX(offset, block_id) \
1179 (0x0001180008000780ull + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)
1180static inline u64 CVMX_GMXX_TX_COL_ATTEMPT(unsigned long offset)
1181{
1182 switch (cvmx_get_octeon_family()) {
1183 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1184 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1185 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1186 return 0x0001180008000498ull + (offset) * 0x8000000ull;
1187 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1188 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1189 return 0x0001180008000498ull + (offset) * 0x8000000ull;
1190 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1191 return 0x0001180008000498ull + (offset) * 0x1000000ull;
1192 }
1193 return 0x0001180008000498ull + (offset) * 0x8000000ull;
1194}
1195
1196static inline u64 CVMX_GMXX_TX_CORRUPT(unsigned long offset)
1197{
1198 switch (cvmx_get_octeon_family()) {
1199 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1200 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1201 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1202 return 0x00011800080004D8ull + (offset) * 0x8000000ull;
1203 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1204 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1205 return 0x00011800080004D8ull + (offset) * 0x8000000ull;
1206 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1207 return 0x00011800080004D8ull + (offset) * 0x1000000ull;
1208 }
1209 return 0x00011800080004D8ull + (offset) * 0x8000000ull;
1210}
1211
1212static inline u64 CVMX_GMXX_TX_HG2_REG1(unsigned long offset)
1213{
1214 switch (cvmx_get_octeon_family()) {
1215 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1216 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1217 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1218 return 0x0001180008000558ull + (offset) * 0x8000000ull;
1219 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1220 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1221 return 0x0001180008000558ull + (offset) * 0x8000000ull;
1222 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1223 return 0x0001180008000558ull + (offset) * 0x1000000ull;
1224 }
1225 return 0x0001180008000558ull + (offset) * 0x8000000ull;
1226}
1227
1228static inline u64 CVMX_GMXX_TX_HG2_REG2(unsigned long offset)
1229{
1230 switch (cvmx_get_octeon_family()) {
1231 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1232 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1233 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1234 return 0x0001180008000560ull + (offset) * 0x8000000ull;
1235 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1236 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1237 return 0x0001180008000560ull + (offset) * 0x8000000ull;
1238 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1239 return 0x0001180008000560ull + (offset) * 0x1000000ull;
1240 }
1241 return 0x0001180008000560ull + (offset) * 0x8000000ull;
1242}
1243
1244static inline u64 CVMX_GMXX_TX_IFG(unsigned long offset)
1245{
1246 switch (cvmx_get_octeon_family()) {
1247 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1248 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1249 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1250 return 0x0001180008000488ull + (offset) * 0x8000000ull;
1251 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1252 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1253 return 0x0001180008000488ull + (offset) * 0x8000000ull;
1254 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1255 return 0x0001180008000488ull + (offset) * 0x1000000ull;
1256 }
1257 return 0x0001180008000488ull + (offset) * 0x8000000ull;
1258}
1259
1260static inline u64 CVMX_GMXX_TX_INT_EN(unsigned long offset)
1261{
1262 switch (cvmx_get_octeon_family()) {
1263 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1264 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1265 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1266 return 0x0001180008000508ull + (offset) * 0x8000000ull;
1267 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1268 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1269 return 0x0001180008000508ull + (offset) * 0x8000000ull;
1270 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1271 return 0x0001180008000508ull + (offset) * 0x1000000ull;
1272 }
1273 return 0x0001180008000508ull + (offset) * 0x8000000ull;
1274}
1275
1276static inline u64 CVMX_GMXX_TX_INT_REG(unsigned long offset)
1277{
1278 switch (cvmx_get_octeon_family()) {
1279 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1280 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1281 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1282 return 0x0001180008000500ull + (offset) * 0x8000000ull;
1283 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1284 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1285 return 0x0001180008000500ull + (offset) * 0x8000000ull;
1286 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1287 return 0x0001180008000500ull + (offset) * 0x1000000ull;
1288 }
1289 return 0x0001180008000500ull + (offset) * 0x8000000ull;
1290}
1291
1292static inline u64 CVMX_GMXX_TX_JAM(unsigned long offset)
1293{
1294 switch (cvmx_get_octeon_family()) {
1295 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1296 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1297 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1298 return 0x0001180008000490ull + (offset) * 0x8000000ull;
1299 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1300 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1301 return 0x0001180008000490ull + (offset) * 0x8000000ull;
1302 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1303 return 0x0001180008000490ull + (offset) * 0x1000000ull;
1304 }
1305 return 0x0001180008000490ull + (offset) * 0x8000000ull;
1306}
1307
1308static inline u64 CVMX_GMXX_TX_LFSR(unsigned long offset)
1309{
1310 switch (cvmx_get_octeon_family()) {
1311 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1312 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1313 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1314 return 0x00011800080004F8ull + (offset) * 0x8000000ull;
1315 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1316 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1317 return 0x00011800080004F8ull + (offset) * 0x8000000ull;
1318 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1319 return 0x00011800080004F8ull + (offset) * 0x1000000ull;
1320 }
1321 return 0x00011800080004F8ull + (offset) * 0x8000000ull;
1322}
1323
1324static inline u64 CVMX_GMXX_TX_OVR_BP(unsigned long offset)
1325{
1326 switch (cvmx_get_octeon_family()) {
1327 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1328 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1329 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1330 return 0x00011800080004C8ull + (offset) * 0x8000000ull;
1331 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1332 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1333 return 0x00011800080004C8ull + (offset) * 0x8000000ull;
1334 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1335 return 0x00011800080004C8ull + (offset) * 0x1000000ull;
1336 }
1337 return 0x00011800080004C8ull + (offset) * 0x8000000ull;
1338}
1339
1340static inline u64 CVMX_GMXX_TX_PAUSE_PKT_DMAC(unsigned long offset)
1341{
1342 switch (cvmx_get_octeon_family()) {
1343 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1344 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1345 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1346 return 0x00011800080004A0ull + (offset) * 0x8000000ull;
1347 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1348 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1349 return 0x00011800080004A0ull + (offset) * 0x8000000ull;
1350 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1351 return 0x00011800080004A0ull + (offset) * 0x1000000ull;
1352 }
1353 return 0x00011800080004A0ull + (offset) * 0x8000000ull;
1354}
1355
1356static inline u64 CVMX_GMXX_TX_PAUSE_PKT_TYPE(unsigned long offset)
1357{
1358 switch (cvmx_get_octeon_family()) {
1359 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1360 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1361 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1362 return 0x00011800080004A8ull + (offset) * 0x8000000ull;
1363 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1364 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1365 return 0x00011800080004A8ull + (offset) * 0x8000000ull;
1366 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1367 return 0x00011800080004A8ull + (offset) * 0x1000000ull;
1368 }
1369 return 0x00011800080004A8ull + (offset) * 0x8000000ull;
1370}
1371
1372static inline u64 CVMX_GMXX_TX_PRTS(unsigned long offset)
1373{
1374 switch (cvmx_get_octeon_family()) {
1375 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1376 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1377 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1378 return 0x0001180008000480ull + (offset) * 0x8000000ull;
1379 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1380 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1381 return 0x0001180008000480ull + (offset) * 0x8000000ull;
1382 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1383 return 0x0001180008000480ull + (offset) * 0x1000000ull;
1384 }
1385 return 0x0001180008000480ull + (offset) * 0x8000000ull;
1386}
1387
1388#define CVMX_GMXX_TX_SPI_CTL(offset) (0x00011800080004C0ull + ((offset) & 1) * 0x8000000ull)
1389#define CVMX_GMXX_TX_SPI_DRAIN(offset) (0x00011800080004E0ull + ((offset) & 1) * 0x8000000ull)
1390#define CVMX_GMXX_TX_SPI_MAX(offset) (0x00011800080004B0ull + ((offset) & 1) * 0x8000000ull)
1391#define CVMX_GMXX_TX_SPI_ROUNDX(offset, block_id) \
1392 (0x0001180008000680ull + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)
1393#define CVMX_GMXX_TX_SPI_THRESH(offset) (0x00011800080004B8ull + ((offset) & 1) * 0x8000000ull)
1394static inline u64 CVMX_GMXX_TX_XAUI_CTL(unsigned long offset)
1395{
1396 switch (cvmx_get_octeon_family()) {
1397 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1398 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1399 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1400 return 0x0001180008000528ull + (offset) * 0x8000000ull;
1401 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1402 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1403 return 0x0001180008000528ull + (offset) * 0x8000000ull;
1404 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1405 return 0x0001180008000528ull + (offset) * 0x1000000ull;
1406 }
1407 return 0x0001180008000528ull + (offset) * 0x8000000ull;
1408}
1409
1410#define CVMX_GMXX_WOL_CTL(offset) (0x0001180008000780ull + ((offset) & 1) * 0x8000000ull)
1411static inline u64 CVMX_GMXX_XAUI_EXT_LOOPBACK(unsigned long offset)
1412{
1413 switch (cvmx_get_octeon_family()) {
1414 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
1415 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
1416 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
1417 return 0x0001180008000540ull + (offset) * 0x8000000ull;
1418 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
1419 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
1420 return 0x0001180008000540ull + (offset) * 0x8000000ull;
1421 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
1422 return 0x0001180008000540ull + (offset) * 0x1000000ull;
1423 }
1424 return 0x0001180008000540ull + (offset) * 0x8000000ull;
1425}
1426
1427/**
1428 * cvmx_gmx#_bad_reg
1429 *
1430 * GMX_BAD_REG = A collection of things that have gone very, very wrong
1431 *
1432 *
1433 * Notes:
1434 * In XAUI mode, only the lsb (corresponding to port0) of INB_NXA, LOSTSTAT, OUT_OVR, are used.
1435 *
1436 */
1437union cvmx_gmxx_bad_reg {
1438 u64 u64;
1439 struct cvmx_gmxx_bad_reg_s {
1440 u64 reserved_31_63 : 33;
1441 u64 inb_nxa : 4;
1442 u64 statovr : 1;
1443 u64 loststat : 4;
1444 u64 reserved_18_21 : 4;
1445 u64 out_ovr : 16;
1446 u64 ncb_ovr : 1;
1447 u64 out_col : 1;
1448 } s;
1449 struct cvmx_gmxx_bad_reg_cn30xx {
1450 u64 reserved_31_63 : 33;
1451 u64 inb_nxa : 4;
1452 u64 statovr : 1;
1453 u64 reserved_25_25 : 1;
1454 u64 loststat : 3;
1455 u64 reserved_5_21 : 17;
1456 u64 out_ovr : 3;
1457 u64 reserved_0_1 : 2;
1458 } cn30xx;
1459 struct cvmx_gmxx_bad_reg_cn30xx cn31xx;
1460 struct cvmx_gmxx_bad_reg_s cn38xx;
1461 struct cvmx_gmxx_bad_reg_s cn38xxp2;
1462 struct cvmx_gmxx_bad_reg_cn30xx cn50xx;
1463 struct cvmx_gmxx_bad_reg_cn52xx {
1464 u64 reserved_31_63 : 33;
1465 u64 inb_nxa : 4;
1466 u64 statovr : 1;
1467 u64 loststat : 4;
1468 u64 reserved_6_21 : 16;
1469 u64 out_ovr : 4;
1470 u64 reserved_0_1 : 2;
1471 } cn52xx;
1472 struct cvmx_gmxx_bad_reg_cn52xx cn52xxp1;
1473 struct cvmx_gmxx_bad_reg_cn52xx cn56xx;
1474 struct cvmx_gmxx_bad_reg_cn52xx cn56xxp1;
1475 struct cvmx_gmxx_bad_reg_s cn58xx;
1476 struct cvmx_gmxx_bad_reg_s cn58xxp1;
1477 struct cvmx_gmxx_bad_reg_cn52xx cn61xx;
1478 struct cvmx_gmxx_bad_reg_cn52xx cn63xx;
1479 struct cvmx_gmxx_bad_reg_cn52xx cn63xxp1;
1480 struct cvmx_gmxx_bad_reg_cn52xx cn66xx;
1481 struct cvmx_gmxx_bad_reg_cn52xx cn68xx;
1482 struct cvmx_gmxx_bad_reg_cn52xx cn68xxp1;
1483 struct cvmx_gmxx_bad_reg_cn52xx cn70xx;
1484 struct cvmx_gmxx_bad_reg_cn52xx cn70xxp1;
1485 struct cvmx_gmxx_bad_reg_cn52xx cnf71xx;
1486};
1487
1488typedef union cvmx_gmxx_bad_reg cvmx_gmxx_bad_reg_t;
1489
1490/**
1491 * cvmx_gmx#_bist
1492 *
1493 * GMX_BIST = GMX BIST Results
1494 *
1495 */
1496union cvmx_gmxx_bist {
1497 u64 u64;
1498 struct cvmx_gmxx_bist_s {
1499 u64 reserved_25_63 : 39;
1500 u64 status : 25;
1501 } s;
1502 struct cvmx_gmxx_bist_cn30xx {
1503 u64 reserved_10_63 : 54;
1504 u64 status : 10;
1505 } cn30xx;
1506 struct cvmx_gmxx_bist_cn30xx cn31xx;
1507 struct cvmx_gmxx_bist_cn30xx cn38xx;
1508 struct cvmx_gmxx_bist_cn30xx cn38xxp2;
1509 struct cvmx_gmxx_bist_cn50xx {
1510 u64 reserved_12_63 : 52;
1511 u64 status : 12;
1512 } cn50xx;
1513 struct cvmx_gmxx_bist_cn52xx {
1514 u64 reserved_16_63 : 48;
1515 u64 status : 16;
1516 } cn52xx;
1517 struct cvmx_gmxx_bist_cn52xx cn52xxp1;
1518 struct cvmx_gmxx_bist_cn52xx cn56xx;
1519 struct cvmx_gmxx_bist_cn52xx cn56xxp1;
1520 struct cvmx_gmxx_bist_cn58xx {
1521 u64 reserved_17_63 : 47;
1522 u64 status : 17;
1523 } cn58xx;
1524 struct cvmx_gmxx_bist_cn58xx cn58xxp1;
1525 struct cvmx_gmxx_bist_s cn61xx;
1526 struct cvmx_gmxx_bist_s cn63xx;
1527 struct cvmx_gmxx_bist_s cn63xxp1;
1528 struct cvmx_gmxx_bist_s cn66xx;
1529 struct cvmx_gmxx_bist_s cn68xx;
1530 struct cvmx_gmxx_bist_s cn68xxp1;
1531 struct cvmx_gmxx_bist_s cn70xx;
1532 struct cvmx_gmxx_bist_s cn70xxp1;
1533 struct cvmx_gmxx_bist_s cnf71xx;
1534};
1535
1536typedef union cvmx_gmxx_bist cvmx_gmxx_bist_t;
1537
1538/**
1539 * cvmx_gmx#_bpid_map#
1540 *
1541 * Notes:
1542 * GMX will build BPID_VECTOR<15:0> using the 16 GMX_BPID_MAP entries and the BPID
1543 * state from IPD. In XAUI/RXAUI mode when PFC/CBFC/HiGig2 is used, the
1544 * BPID_VECTOR becomes the logical backpressure. In XAUI/RXAUI mode when
1545 * PFC/CBFC/HiGig2 is not used or when in 4xSGMII mode, the BPID_VECTOR can be used
1546 * with the GMX_BPID_MSK register to determine the physical backpressure.
1547 *
1548 * In XAUI/RXAUI mode, the entire BPID_VECTOR<15:0> is available determining physical
1549 * backpressure for the single XAUI/RXAUI interface.
1550 *
1551 * In SGMII mode, BPID_VECTOR is broken up as follows:
1552 * SGMII interface0 uses BPID_VECTOR<3:0>
1553 * SGMII interface1 uses BPID_VECTOR<7:4>
1554 * SGMII interface2 uses BPID_VECTOR<11:8>
1555 * SGMII interface3 uses BPID_VECTOR<15:12>
1556 *
1557 * In all SGMII configurations, and in some XAUI/RXAUI configurations, the
1558 * interface protocols only support physical backpressure. In these cases, a single
1559 * BPID will commonly drive the physical backpressure for the physical
1560 * interface. We provide example programmings for these simple cases.
1561 *
1562 * In XAUI/RXAUI mode where PFC/CBFC/HiGig2 is not used, an example programming
1563 * would be as follows:
1564 *
1565 * @verbatim
1566 * GMX_BPID_MAP0[VAL] = 1;
1567 * GMX_BPID_MAP0[BPID] = xaui_bpid;
1568 * GMX_BPID_MSK[MSK_OR] = 1;
1569 * GMX_BPID_MSK[MSK_AND] = 0;
1570 * @endverbatim
1571 *
1572 * In SGMII mode, an example programming would be as follows:
1573 *
1574 * @verbatim
1575 * for (i=0; i<4; i++) [
1576 * if (GMX_PRTi_CFG[EN]) [
1577 * GMX_BPID_MAP(i*4)[VAL] = 1;
1578 * GMX_BPID_MAP(i*4)[BPID] = sgmii_bpid(i);
1579 * GMX_BPID_MSK[MSK_OR] = (1 << (i*4)) | GMX_BPID_MSK[MSK_OR];
1580 * ]
1581 * ]
1582 * GMX_BPID_MSK[MSK_AND] = 0;
1583 * @endverbatim
1584 */
1585union cvmx_gmxx_bpid_mapx {
1586 u64 u64;
1587 struct cvmx_gmxx_bpid_mapx_s {
1588 u64 reserved_17_63 : 47;
1589 u64 status : 1;
1590 u64 reserved_9_15 : 7;
1591 u64 val : 1;
1592 u64 reserved_6_7 : 2;
1593 u64 bpid : 6;
1594 } s;
1595 struct cvmx_gmxx_bpid_mapx_s cn68xx;
1596 struct cvmx_gmxx_bpid_mapx_s cn68xxp1;
1597};
1598
1599typedef union cvmx_gmxx_bpid_mapx cvmx_gmxx_bpid_mapx_t;
1600
1601/**
1602 * cvmx_gmx#_bpid_msk
1603 */
1604union cvmx_gmxx_bpid_msk {
1605 u64 u64;
1606 struct cvmx_gmxx_bpid_msk_s {
1607 u64 reserved_48_63 : 16;
1608 u64 msk_or : 16;
1609 u64 reserved_16_31 : 16;
1610 u64 msk_and : 16;
1611 } s;
1612 struct cvmx_gmxx_bpid_msk_s cn68xx;
1613 struct cvmx_gmxx_bpid_msk_s cn68xxp1;
1614};
1615
1616typedef union cvmx_gmxx_bpid_msk cvmx_gmxx_bpid_msk_t;
1617
1618/**
1619 * cvmx_gmx#_clk_en
1620 *
1621 * DON'T PUT IN HRM*
1622 *
1623 */
1624union cvmx_gmxx_clk_en {
1625 u64 u64;
1626 struct cvmx_gmxx_clk_en_s {
1627 u64 reserved_1_63 : 63;
1628 u64 clk_en : 1;
1629 } s;
1630 struct cvmx_gmxx_clk_en_s cn52xx;
1631 struct cvmx_gmxx_clk_en_s cn52xxp1;
1632 struct cvmx_gmxx_clk_en_s cn56xx;
1633 struct cvmx_gmxx_clk_en_s cn56xxp1;
1634 struct cvmx_gmxx_clk_en_s cn61xx;
1635 struct cvmx_gmxx_clk_en_s cn63xx;
1636 struct cvmx_gmxx_clk_en_s cn63xxp1;
1637 struct cvmx_gmxx_clk_en_s cn66xx;
1638 struct cvmx_gmxx_clk_en_s cn68xx;
1639 struct cvmx_gmxx_clk_en_s cn68xxp1;
1640 struct cvmx_gmxx_clk_en_s cn70xx;
1641 struct cvmx_gmxx_clk_en_s cn70xxp1;
1642 struct cvmx_gmxx_clk_en_s cnf71xx;
1643};
1644
1645typedef union cvmx_gmxx_clk_en cvmx_gmxx_clk_en_t;
1646
1647/**
1648 * cvmx_gmx#_ebp_dis
1649 */
1650union cvmx_gmxx_ebp_dis {
1651 u64 u64;
1652 struct cvmx_gmxx_ebp_dis_s {
1653 u64 reserved_16_63 : 48;
1654 u64 dis : 16;
1655 } s;
1656 struct cvmx_gmxx_ebp_dis_s cn68xx;
1657 struct cvmx_gmxx_ebp_dis_s cn68xxp1;
1658};
1659
1660typedef union cvmx_gmxx_ebp_dis cvmx_gmxx_ebp_dis_t;
1661
1662/**
1663 * cvmx_gmx#_ebp_msk
1664 */
1665union cvmx_gmxx_ebp_msk {
1666 u64 u64;
1667 struct cvmx_gmxx_ebp_msk_s {
1668 u64 reserved_16_63 : 48;
1669 u64 msk : 16;
1670 } s;
1671 struct cvmx_gmxx_ebp_msk_s cn68xx;
1672 struct cvmx_gmxx_ebp_msk_s cn68xxp1;
1673};
1674
1675typedef union cvmx_gmxx_ebp_msk cvmx_gmxx_ebp_msk_t;
1676
1677/**
1678 * cvmx_gmx#_hg2_control
1679 *
1680 * Notes:
1681 * The HiGig2 TX and RX enable would normally be both set together for HiGig2 messaging. However
1682 * setting just the TX or RX bit will result in only the HG2 message transmit or the receive
1683 * capability.
1684 * PHYS_EN and LOGL_EN bits when 1, allow link pause or back pressure to PKO as per received
1685 * HiGig2 message. When 0, link pause and back pressure to PKO in response to received messages
1686 * are disabled.
1687 *
1688 * GMX*_TX_XAUI_CTL[HG_EN] must be set to one(to enable HiGig) whenever either HG2TX_EN or HG2RX_EN
1689 * are set.
1690 *
1691 * GMX*_RX0_UDD_SKP[LEN] must be set to 16 (to select HiGig2) whenever either HG2TX_EN or HG2RX_EN
1692 * are set.
1693 *
1694 * GMX*_TX_OVR_BP[EN<0>] must be set to one and GMX*_TX_OVR_BP[BP<0>] must be cleared to zero
1695 * (to forcibly disable HW-automatic 802.3 pause packet generation) with the HiGig2 Protocol when
1696 * GMX*_HG2_CONTROL[HG2TX_EN]=0. (The HiGig2 protocol is indicated by GMX*_TX_XAUI_CTL[HG_EN]=1
1697 * and GMX*_RX0_UDD_SKP[LEN]=16.) The HW can only auto-generate backpressure via HiGig2 messages
1698 * (optionally, when HG2TX_EN=1) with the HiGig2 protocol.
1699 */
1700union cvmx_gmxx_hg2_control {
1701 u64 u64;
1702 struct cvmx_gmxx_hg2_control_s {
1703 u64 reserved_19_63 : 45;
1704 u64 hg2tx_en : 1;
1705 u64 hg2rx_en : 1;
1706 u64 phys_en : 1;
1707 u64 logl_en : 16;
1708 } s;
1709 struct cvmx_gmxx_hg2_control_s cn52xx;
1710 struct cvmx_gmxx_hg2_control_s cn52xxp1;
1711 struct cvmx_gmxx_hg2_control_s cn56xx;
1712 struct cvmx_gmxx_hg2_control_s cn61xx;
1713 struct cvmx_gmxx_hg2_control_s cn63xx;
1714 struct cvmx_gmxx_hg2_control_s cn63xxp1;
1715 struct cvmx_gmxx_hg2_control_s cn66xx;
1716 struct cvmx_gmxx_hg2_control_s cn68xx;
1717 struct cvmx_gmxx_hg2_control_s cn68xxp1;
1718 struct cvmx_gmxx_hg2_control_s cn70xx;
1719 struct cvmx_gmxx_hg2_control_s cn70xxp1;
1720 struct cvmx_gmxx_hg2_control_s cnf71xx;
1721};
1722
1723typedef union cvmx_gmxx_hg2_control cvmx_gmxx_hg2_control_t;
1724
1725/**
1726 * cvmx_gmx#_inf_mode
1727 *
1728 * GMX_INF_MODE = Interface Mode
1729 *
1730 */
1731union cvmx_gmxx_inf_mode {
1732 u64 u64;
1733 struct cvmx_gmxx_inf_mode_s {
1734 u64 reserved_20_63 : 44;
1735 u64 rate : 4;
1736 u64 reserved_12_15 : 4;
1737 u64 speed : 4;
1738 u64 reserved_7_7 : 1;
1739 u64 mode : 3;
1740 u64 reserved_3_3 : 1;
1741 u64 p0mii : 1;
1742 u64 en : 1;
1743 u64 type : 1;
1744 } s;
1745 struct cvmx_gmxx_inf_mode_cn30xx {
1746 u64 reserved_3_63 : 61;
1747 u64 p0mii : 1;
1748 u64 en : 1;
1749 u64 type : 1;
1750 } cn30xx;
1751 struct cvmx_gmxx_inf_mode_cn31xx {
1752 u64 reserved_2_63 : 62;
1753 u64 en : 1;
1754 u64 type : 1;
1755 } cn31xx;
1756 struct cvmx_gmxx_inf_mode_cn31xx cn38xx;
1757 struct cvmx_gmxx_inf_mode_cn31xx cn38xxp2;
1758 struct cvmx_gmxx_inf_mode_cn30xx cn50xx;
1759 struct cvmx_gmxx_inf_mode_cn52xx {
1760 u64 reserved_10_63 : 54;
1761 u64 speed : 2;
1762 u64 reserved_6_7 : 2;
1763 u64 mode : 2;
1764 u64 reserved_2_3 : 2;
1765 u64 en : 1;
1766 u64 type : 1;
1767 } cn52xx;
1768 struct cvmx_gmxx_inf_mode_cn52xx cn52xxp1;
1769 struct cvmx_gmxx_inf_mode_cn52xx cn56xx;
1770 struct cvmx_gmxx_inf_mode_cn52xx cn56xxp1;
1771 struct cvmx_gmxx_inf_mode_cn31xx cn58xx;
1772 struct cvmx_gmxx_inf_mode_cn31xx cn58xxp1;
1773 struct cvmx_gmxx_inf_mode_cn61xx {
1774 u64 reserved_12_63 : 52;
1775 u64 speed : 4;
1776 u64 reserved_5_7 : 3;
1777 u64 mode : 1;
1778 u64 reserved_2_3 : 2;
1779 u64 en : 1;
1780 u64 type : 1;
1781 } cn61xx;
1782 struct cvmx_gmxx_inf_mode_cn61xx cn63xx;
1783 struct cvmx_gmxx_inf_mode_cn61xx cn63xxp1;
1784 struct cvmx_gmxx_inf_mode_cn66xx {
1785 u64 reserved_20_63 : 44;
1786 u64 rate : 4;
1787 u64 reserved_12_15 : 4;
1788 u64 speed : 4;
1789 u64 reserved_5_7 : 3;
1790 u64 mode : 1;
1791 u64 reserved_2_3 : 2;
1792 u64 en : 1;
1793 u64 type : 1;
1794 } cn66xx;
1795 struct cvmx_gmxx_inf_mode_cn68xx {
1796 u64 reserved_12_63 : 52;
1797 u64 speed : 4;
1798 u64 reserved_7_7 : 1;
1799 u64 mode : 3;
1800 u64 reserved_2_3 : 2;
1801 u64 en : 1;
1802 u64 type : 1;
1803 } cn68xx;
1804 struct cvmx_gmxx_inf_mode_cn68xx cn68xxp1;
1805 struct cvmx_gmxx_inf_mode_cn70xx {
1806 u64 reserved_6_63 : 58;
1807 u64 mode : 2;
1808 u64 reserved_2_3 : 2;
1809 u64 en : 1;
1810 u64 reserved_0_0 : 1;
1811 } cn70xx;
1812 struct cvmx_gmxx_inf_mode_cn70xx cn70xxp1;
1813 struct cvmx_gmxx_inf_mode_cn61xx cnf71xx;
1814};
1815
1816typedef union cvmx_gmxx_inf_mode cvmx_gmxx_inf_mode_t;
1817
1818/**
1819 * cvmx_gmx#_nxa_adr
1820 *
1821 * GMX_NXA_ADR = NXA Port Address
1822 *
1823 */
1824union cvmx_gmxx_nxa_adr {
1825 u64 u64;
1826 struct cvmx_gmxx_nxa_adr_s {
1827 u64 reserved_23_63 : 41;
1828 u64 pipe : 7;
1829 u64 reserved_6_15 : 10;
1830 u64 prt : 6;
1831 } s;
1832 struct cvmx_gmxx_nxa_adr_cn30xx {
1833 u64 reserved_6_63 : 58;
1834 u64 prt : 6;
1835 } cn30xx;
1836 struct cvmx_gmxx_nxa_adr_cn30xx cn31xx;
1837 struct cvmx_gmxx_nxa_adr_cn30xx cn38xx;
1838 struct cvmx_gmxx_nxa_adr_cn30xx cn38xxp2;
1839 struct cvmx_gmxx_nxa_adr_cn30xx cn50xx;
1840 struct cvmx_gmxx_nxa_adr_cn30xx cn52xx;
1841 struct cvmx_gmxx_nxa_adr_cn30xx cn52xxp1;
1842 struct cvmx_gmxx_nxa_adr_cn30xx cn56xx;
1843 struct cvmx_gmxx_nxa_adr_cn30xx cn56xxp1;
1844 struct cvmx_gmxx_nxa_adr_cn30xx cn58xx;
1845 struct cvmx_gmxx_nxa_adr_cn30xx cn58xxp1;
1846 struct cvmx_gmxx_nxa_adr_cn30xx cn61xx;
1847 struct cvmx_gmxx_nxa_adr_cn30xx cn63xx;
1848 struct cvmx_gmxx_nxa_adr_cn30xx cn63xxp1;
1849 struct cvmx_gmxx_nxa_adr_cn30xx cn66xx;
1850 struct cvmx_gmxx_nxa_adr_s cn68xx;
1851 struct cvmx_gmxx_nxa_adr_s cn68xxp1;
1852 struct cvmx_gmxx_nxa_adr_cn30xx cn70xx;
1853 struct cvmx_gmxx_nxa_adr_cn30xx cn70xxp1;
1854 struct cvmx_gmxx_nxa_adr_cn30xx cnf71xx;
1855};
1856
1857typedef union cvmx_gmxx_nxa_adr cvmx_gmxx_nxa_adr_t;
1858
1859/**
1860 * cvmx_gmx#_pipe_status
1861 *
1862 * DON'T PUT IN HRM*
1863 *
1864 */
1865union cvmx_gmxx_pipe_status {
1866 u64 u64;
1867 struct cvmx_gmxx_pipe_status_s {
1868 u64 reserved_20_63 : 44;
1869 u64 ovr : 4;
1870 u64 reserved_12_15 : 4;
1871 u64 bp : 4;
1872 u64 reserved_4_7 : 4;
1873 u64 stop : 4;
1874 } s;
1875 struct cvmx_gmxx_pipe_status_s cn68xx;
1876 struct cvmx_gmxx_pipe_status_s cn68xxp1;
1877};
1878
1879typedef union cvmx_gmxx_pipe_status cvmx_gmxx_pipe_status_t;
1880
1881/**
1882 * cvmx_gmx#_prt#_cbfc_ctl
1883 *
1884 * ** HG2 message CSRs end
1885 *
1886 */
1887union cvmx_gmxx_prtx_cbfc_ctl {
1888 u64 u64;
1889 struct cvmx_gmxx_prtx_cbfc_ctl_s {
1890 u64 phys_en : 16;
1891 u64 logl_en : 16;
1892 u64 phys_bp : 16;
1893 u64 reserved_4_15 : 12;
1894 u64 bck_en : 1;
1895 u64 drp_en : 1;
1896 u64 tx_en : 1;
1897 u64 rx_en : 1;
1898 } s;
1899 struct cvmx_gmxx_prtx_cbfc_ctl_s cn52xx;
1900 struct cvmx_gmxx_prtx_cbfc_ctl_s cn56xx;
1901 struct cvmx_gmxx_prtx_cbfc_ctl_s cn61xx;
1902 struct cvmx_gmxx_prtx_cbfc_ctl_s cn63xx;
1903 struct cvmx_gmxx_prtx_cbfc_ctl_s cn63xxp1;
1904 struct cvmx_gmxx_prtx_cbfc_ctl_s cn66xx;
1905 struct cvmx_gmxx_prtx_cbfc_ctl_s cn68xx;
1906 struct cvmx_gmxx_prtx_cbfc_ctl_s cn68xxp1;
1907 struct cvmx_gmxx_prtx_cbfc_ctl_s cn70xx;
1908 struct cvmx_gmxx_prtx_cbfc_ctl_s cn70xxp1;
1909 struct cvmx_gmxx_prtx_cbfc_ctl_s cnf71xx;
1910};
1911
1912typedef union cvmx_gmxx_prtx_cbfc_ctl cvmx_gmxx_prtx_cbfc_ctl_t;
1913
1914/**
1915 * cvmx_gmx#_prt#_cfg
1916 *
1917 * GMX_PRT_CFG = Port description
1918 *
1919 */
1920union cvmx_gmxx_prtx_cfg {
1921 u64 u64;
1922 struct cvmx_gmxx_prtx_cfg_s {
1923 u64 reserved_22_63 : 42;
1924 u64 pknd : 6;
1925 u64 reserved_14_15 : 2;
1926 u64 tx_idle : 1;
1927 u64 rx_idle : 1;
1928 u64 reserved_9_11 : 3;
1929 u64 speed_msb : 1;
1930 u64 reserved_4_7 : 4;
1931 u64 slottime : 1;
1932 u64 duplex : 1;
1933 u64 speed : 1;
1934 u64 en : 1;
1935 } s;
1936 struct cvmx_gmxx_prtx_cfg_cn30xx {
1937 u64 reserved_4_63 : 60;
1938 u64 slottime : 1;
1939 u64 duplex : 1;
1940 u64 speed : 1;
1941 u64 en : 1;
1942 } cn30xx;
1943 struct cvmx_gmxx_prtx_cfg_cn30xx cn31xx;
1944 struct cvmx_gmxx_prtx_cfg_cn30xx cn38xx;
1945 struct cvmx_gmxx_prtx_cfg_cn30xx cn38xxp2;
1946 struct cvmx_gmxx_prtx_cfg_cn30xx cn50xx;
1947 struct cvmx_gmxx_prtx_cfg_cn52xx {
1948 u64 reserved_14_63 : 50;
1949 u64 tx_idle : 1;
1950 u64 rx_idle : 1;
1951 u64 reserved_9_11 : 3;
1952 u64 speed_msb : 1;
1953 u64 reserved_4_7 : 4;
1954 u64 slottime : 1;
1955 u64 duplex : 1;
1956 u64 speed : 1;
1957 u64 en : 1;
1958 } cn52xx;
1959 struct cvmx_gmxx_prtx_cfg_cn52xx cn52xxp1;
1960 struct cvmx_gmxx_prtx_cfg_cn52xx cn56xx;
1961 struct cvmx_gmxx_prtx_cfg_cn52xx cn56xxp1;
1962 struct cvmx_gmxx_prtx_cfg_cn30xx cn58xx;
1963 struct cvmx_gmxx_prtx_cfg_cn30xx cn58xxp1;
1964 struct cvmx_gmxx_prtx_cfg_cn52xx cn61xx;
1965 struct cvmx_gmxx_prtx_cfg_cn52xx cn63xx;
1966 struct cvmx_gmxx_prtx_cfg_cn52xx cn63xxp1;
1967 struct cvmx_gmxx_prtx_cfg_cn52xx cn66xx;
1968 struct cvmx_gmxx_prtx_cfg_s cn68xx;
1969 struct cvmx_gmxx_prtx_cfg_s cn68xxp1;
1970 struct cvmx_gmxx_prtx_cfg_cn52xx cn70xx;
1971 struct cvmx_gmxx_prtx_cfg_cn52xx cn70xxp1;
1972 struct cvmx_gmxx_prtx_cfg_cn52xx cnf71xx;
1973};
1974
1975typedef union cvmx_gmxx_prtx_cfg cvmx_gmxx_prtx_cfg_t;
1976
1977/**
1978 * cvmx_gmx#_qsgmii_ctl
1979 */
1980union cvmx_gmxx_qsgmii_ctl {
1981 u64 u64;
1982 struct cvmx_gmxx_qsgmii_ctl_s {
1983 u64 reserved_1_63 : 63;
1984 u64 disparity : 1;
1985 } s;
1986 struct cvmx_gmxx_qsgmii_ctl_s cn70xx;
1987 struct cvmx_gmxx_qsgmii_ctl_s cn70xxp1;
1988};
1989
1990typedef union cvmx_gmxx_qsgmii_ctl cvmx_gmxx_qsgmii_ctl_t;
1991
1992/**
1993 * cvmx_gmx#_rx#_adr_cam0
1994 *
1995 * GMX_RX_ADR_CAM = Address Filtering Control
1996 *
1997 */
1998union cvmx_gmxx_rxx_adr_cam0 {
1999 u64 u64;
2000 struct cvmx_gmxx_rxx_adr_cam0_s {
2001 u64 adr : 64;
2002 } s;
2003 struct cvmx_gmxx_rxx_adr_cam0_s cn30xx;
2004 struct cvmx_gmxx_rxx_adr_cam0_s cn31xx;
2005 struct cvmx_gmxx_rxx_adr_cam0_s cn38xx;
2006 struct cvmx_gmxx_rxx_adr_cam0_s cn38xxp2;
2007 struct cvmx_gmxx_rxx_adr_cam0_s cn50xx;
2008 struct cvmx_gmxx_rxx_adr_cam0_s cn52xx;
2009 struct cvmx_gmxx_rxx_adr_cam0_s cn52xxp1;
2010 struct cvmx_gmxx_rxx_adr_cam0_s cn56xx;
2011 struct cvmx_gmxx_rxx_adr_cam0_s cn56xxp1;
2012 struct cvmx_gmxx_rxx_adr_cam0_s cn58xx;
2013 struct cvmx_gmxx_rxx_adr_cam0_s cn58xxp1;
2014 struct cvmx_gmxx_rxx_adr_cam0_s cn61xx;
2015 struct cvmx_gmxx_rxx_adr_cam0_s cn63xx;
2016 struct cvmx_gmxx_rxx_adr_cam0_s cn63xxp1;
2017 struct cvmx_gmxx_rxx_adr_cam0_s cn66xx;
2018 struct cvmx_gmxx_rxx_adr_cam0_s cn68xx;
2019 struct cvmx_gmxx_rxx_adr_cam0_s cn68xxp1;
2020 struct cvmx_gmxx_rxx_adr_cam0_s cn70xx;
2021 struct cvmx_gmxx_rxx_adr_cam0_s cn70xxp1;
2022 struct cvmx_gmxx_rxx_adr_cam0_s cnf71xx;
2023};
2024
2025typedef union cvmx_gmxx_rxx_adr_cam0 cvmx_gmxx_rxx_adr_cam0_t;
2026
2027/**
2028 * cvmx_gmx#_rx#_adr_cam1
2029 *
2030 * GMX_RX_ADR_CAM = Address Filtering Control
2031 *
2032 */
2033union cvmx_gmxx_rxx_adr_cam1 {
2034 u64 u64;
2035 struct cvmx_gmxx_rxx_adr_cam1_s {
2036 u64 adr : 64;
2037 } s;
2038 struct cvmx_gmxx_rxx_adr_cam1_s cn30xx;
2039 struct cvmx_gmxx_rxx_adr_cam1_s cn31xx;
2040 struct cvmx_gmxx_rxx_adr_cam1_s cn38xx;
2041 struct cvmx_gmxx_rxx_adr_cam1_s cn38xxp2;
2042 struct cvmx_gmxx_rxx_adr_cam1_s cn50xx;
2043 struct cvmx_gmxx_rxx_adr_cam1_s cn52xx;
2044 struct cvmx_gmxx_rxx_adr_cam1_s cn52xxp1;
2045 struct cvmx_gmxx_rxx_adr_cam1_s cn56xx;
2046 struct cvmx_gmxx_rxx_adr_cam1_s cn56xxp1;
2047 struct cvmx_gmxx_rxx_adr_cam1_s cn58xx;
2048 struct cvmx_gmxx_rxx_adr_cam1_s cn58xxp1;
2049 struct cvmx_gmxx_rxx_adr_cam1_s cn61xx;
2050 struct cvmx_gmxx_rxx_adr_cam1_s cn63xx;
2051 struct cvmx_gmxx_rxx_adr_cam1_s cn63xxp1;
2052 struct cvmx_gmxx_rxx_adr_cam1_s cn66xx;
2053 struct cvmx_gmxx_rxx_adr_cam1_s cn68xx;
2054 struct cvmx_gmxx_rxx_adr_cam1_s cn68xxp1;
2055 struct cvmx_gmxx_rxx_adr_cam1_s cn70xx;
2056 struct cvmx_gmxx_rxx_adr_cam1_s cn70xxp1;
2057 struct cvmx_gmxx_rxx_adr_cam1_s cnf71xx;
2058};
2059
2060typedef union cvmx_gmxx_rxx_adr_cam1 cvmx_gmxx_rxx_adr_cam1_t;
2061
2062/**
2063 * cvmx_gmx#_rx#_adr_cam2
2064 *
2065 * GMX_RX_ADR_CAM = Address Filtering Control
2066 *
2067 */
2068union cvmx_gmxx_rxx_adr_cam2 {
2069 u64 u64;
2070 struct cvmx_gmxx_rxx_adr_cam2_s {
2071 u64 adr : 64;
2072 } s;
2073 struct cvmx_gmxx_rxx_adr_cam2_s cn30xx;
2074 struct cvmx_gmxx_rxx_adr_cam2_s cn31xx;
2075 struct cvmx_gmxx_rxx_adr_cam2_s cn38xx;
2076 struct cvmx_gmxx_rxx_adr_cam2_s cn38xxp2;
2077 struct cvmx_gmxx_rxx_adr_cam2_s cn50xx;
2078 struct cvmx_gmxx_rxx_adr_cam2_s cn52xx;
2079 struct cvmx_gmxx_rxx_adr_cam2_s cn52xxp1;
2080 struct cvmx_gmxx_rxx_adr_cam2_s cn56xx;
2081 struct cvmx_gmxx_rxx_adr_cam2_s cn56xxp1;
2082 struct cvmx_gmxx_rxx_adr_cam2_s cn58xx;
2083 struct cvmx_gmxx_rxx_adr_cam2_s cn58xxp1;
2084 struct cvmx_gmxx_rxx_adr_cam2_s cn61xx;
2085 struct cvmx_gmxx_rxx_adr_cam2_s cn63xx;
2086 struct cvmx_gmxx_rxx_adr_cam2_s cn63xxp1;
2087 struct cvmx_gmxx_rxx_adr_cam2_s cn66xx;
2088 struct cvmx_gmxx_rxx_adr_cam2_s cn68xx;
2089 struct cvmx_gmxx_rxx_adr_cam2_s cn68xxp1;
2090 struct cvmx_gmxx_rxx_adr_cam2_s cn70xx;
2091 struct cvmx_gmxx_rxx_adr_cam2_s cn70xxp1;
2092 struct cvmx_gmxx_rxx_adr_cam2_s cnf71xx;
2093};
2094
2095typedef union cvmx_gmxx_rxx_adr_cam2 cvmx_gmxx_rxx_adr_cam2_t;
2096
2097/**
2098 * cvmx_gmx#_rx#_adr_cam3
2099 *
2100 * GMX_RX_ADR_CAM = Address Filtering Control
2101 *
2102 */
2103union cvmx_gmxx_rxx_adr_cam3 {
2104 u64 u64;
2105 struct cvmx_gmxx_rxx_adr_cam3_s {
2106 u64 adr : 64;
2107 } s;
2108 struct cvmx_gmxx_rxx_adr_cam3_s cn30xx;
2109 struct cvmx_gmxx_rxx_adr_cam3_s cn31xx;
2110 struct cvmx_gmxx_rxx_adr_cam3_s cn38xx;
2111 struct cvmx_gmxx_rxx_adr_cam3_s cn38xxp2;
2112 struct cvmx_gmxx_rxx_adr_cam3_s cn50xx;
2113 struct cvmx_gmxx_rxx_adr_cam3_s cn52xx;
2114 struct cvmx_gmxx_rxx_adr_cam3_s cn52xxp1;
2115 struct cvmx_gmxx_rxx_adr_cam3_s cn56xx;
2116 struct cvmx_gmxx_rxx_adr_cam3_s cn56xxp1;
2117 struct cvmx_gmxx_rxx_adr_cam3_s cn58xx;
2118 struct cvmx_gmxx_rxx_adr_cam3_s cn58xxp1;
2119 struct cvmx_gmxx_rxx_adr_cam3_s cn61xx;
2120 struct cvmx_gmxx_rxx_adr_cam3_s cn63xx;
2121 struct cvmx_gmxx_rxx_adr_cam3_s cn63xxp1;
2122 struct cvmx_gmxx_rxx_adr_cam3_s cn66xx;
2123 struct cvmx_gmxx_rxx_adr_cam3_s cn68xx;
2124 struct cvmx_gmxx_rxx_adr_cam3_s cn68xxp1;
2125 struct cvmx_gmxx_rxx_adr_cam3_s cn70xx;
2126 struct cvmx_gmxx_rxx_adr_cam3_s cn70xxp1;
2127 struct cvmx_gmxx_rxx_adr_cam3_s cnf71xx;
2128};
2129
2130typedef union cvmx_gmxx_rxx_adr_cam3 cvmx_gmxx_rxx_adr_cam3_t;
2131
2132/**
2133 * cvmx_gmx#_rx#_adr_cam4
2134 *
2135 * GMX_RX_ADR_CAM = Address Filtering Control
2136 *
2137 */
2138union cvmx_gmxx_rxx_adr_cam4 {
2139 u64 u64;
2140 struct cvmx_gmxx_rxx_adr_cam4_s {
2141 u64 adr : 64;
2142 } s;
2143 struct cvmx_gmxx_rxx_adr_cam4_s cn30xx;
2144 struct cvmx_gmxx_rxx_adr_cam4_s cn31xx;
2145 struct cvmx_gmxx_rxx_adr_cam4_s cn38xx;
2146 struct cvmx_gmxx_rxx_adr_cam4_s cn38xxp2;
2147 struct cvmx_gmxx_rxx_adr_cam4_s cn50xx;
2148 struct cvmx_gmxx_rxx_adr_cam4_s cn52xx;
2149 struct cvmx_gmxx_rxx_adr_cam4_s cn52xxp1;
2150 struct cvmx_gmxx_rxx_adr_cam4_s cn56xx;
2151 struct cvmx_gmxx_rxx_adr_cam4_s cn56xxp1;
2152 struct cvmx_gmxx_rxx_adr_cam4_s cn58xx;
2153 struct cvmx_gmxx_rxx_adr_cam4_s cn58xxp1;
2154 struct cvmx_gmxx_rxx_adr_cam4_s cn61xx;
2155 struct cvmx_gmxx_rxx_adr_cam4_s cn63xx;
2156 struct cvmx_gmxx_rxx_adr_cam4_s cn63xxp1;
2157 struct cvmx_gmxx_rxx_adr_cam4_s cn66xx;
2158 struct cvmx_gmxx_rxx_adr_cam4_s cn68xx;
2159 struct cvmx_gmxx_rxx_adr_cam4_s cn68xxp1;
2160 struct cvmx_gmxx_rxx_adr_cam4_s cn70xx;
2161 struct cvmx_gmxx_rxx_adr_cam4_s cn70xxp1;
2162 struct cvmx_gmxx_rxx_adr_cam4_s cnf71xx;
2163};
2164
2165typedef union cvmx_gmxx_rxx_adr_cam4 cvmx_gmxx_rxx_adr_cam4_t;
2166
2167/**
2168 * cvmx_gmx#_rx#_adr_cam5
2169 *
2170 * GMX_RX_ADR_CAM = Address Filtering Control
2171 *
2172 */
2173union cvmx_gmxx_rxx_adr_cam5 {
2174 u64 u64;
2175 struct cvmx_gmxx_rxx_adr_cam5_s {
2176 u64 adr : 64;
2177 } s;
2178 struct cvmx_gmxx_rxx_adr_cam5_s cn30xx;
2179 struct cvmx_gmxx_rxx_adr_cam5_s cn31xx;
2180 struct cvmx_gmxx_rxx_adr_cam5_s cn38xx;
2181 struct cvmx_gmxx_rxx_adr_cam5_s cn38xxp2;
2182 struct cvmx_gmxx_rxx_adr_cam5_s cn50xx;
2183 struct cvmx_gmxx_rxx_adr_cam5_s cn52xx;
2184 struct cvmx_gmxx_rxx_adr_cam5_s cn52xxp1;
2185 struct cvmx_gmxx_rxx_adr_cam5_s cn56xx;
2186 struct cvmx_gmxx_rxx_adr_cam5_s cn56xxp1;
2187 struct cvmx_gmxx_rxx_adr_cam5_s cn58xx;
2188 struct cvmx_gmxx_rxx_adr_cam5_s cn58xxp1;
2189 struct cvmx_gmxx_rxx_adr_cam5_s cn61xx;
2190 struct cvmx_gmxx_rxx_adr_cam5_s cn63xx;
2191 struct cvmx_gmxx_rxx_adr_cam5_s cn63xxp1;
2192 struct cvmx_gmxx_rxx_adr_cam5_s cn66xx;
2193 struct cvmx_gmxx_rxx_adr_cam5_s cn68xx;
2194 struct cvmx_gmxx_rxx_adr_cam5_s cn68xxp1;
2195 struct cvmx_gmxx_rxx_adr_cam5_s cn70xx;
2196 struct cvmx_gmxx_rxx_adr_cam5_s cn70xxp1;
2197 struct cvmx_gmxx_rxx_adr_cam5_s cnf71xx;
2198};
2199
2200typedef union cvmx_gmxx_rxx_adr_cam5 cvmx_gmxx_rxx_adr_cam5_t;
2201
2202/**
2203 * cvmx_gmx#_rx#_adr_cam_all_en
2204 *
2205 * GMX_RX_ADR_CAM_ALL_EN = Address Filtering Control Enable
2206 *
2207 */
2208union cvmx_gmxx_rxx_adr_cam_all_en {
2209 u64 u64;
2210 struct cvmx_gmxx_rxx_adr_cam_all_en_s {
2211 u64 reserved_32_63 : 32;
2212 u64 en : 32;
2213 } s;
2214 struct cvmx_gmxx_rxx_adr_cam_all_en_s cn61xx;
2215 struct cvmx_gmxx_rxx_adr_cam_all_en_s cn66xx;
2216 struct cvmx_gmxx_rxx_adr_cam_all_en_s cn68xx;
2217 struct cvmx_gmxx_rxx_adr_cam_all_en_s cn70xx;
2218 struct cvmx_gmxx_rxx_adr_cam_all_en_s cn70xxp1;
2219 struct cvmx_gmxx_rxx_adr_cam_all_en_s cnf71xx;
2220};
2221
2222typedef union cvmx_gmxx_rxx_adr_cam_all_en cvmx_gmxx_rxx_adr_cam_all_en_t;
2223
2224/**
2225 * cvmx_gmx#_rx#_adr_cam_en
2226 *
2227 * GMX_RX_ADR_CAM_EN = Address Filtering Control Enable
2228 *
2229 */
2230union cvmx_gmxx_rxx_adr_cam_en {
2231 u64 u64;
2232 struct cvmx_gmxx_rxx_adr_cam_en_s {
2233 u64 reserved_8_63 : 56;
2234 u64 en : 8;
2235 } s;
2236 struct cvmx_gmxx_rxx_adr_cam_en_s cn30xx;
2237 struct cvmx_gmxx_rxx_adr_cam_en_s cn31xx;
2238 struct cvmx_gmxx_rxx_adr_cam_en_s cn38xx;
2239 struct cvmx_gmxx_rxx_adr_cam_en_s cn38xxp2;
2240 struct cvmx_gmxx_rxx_adr_cam_en_s cn50xx;
2241 struct cvmx_gmxx_rxx_adr_cam_en_s cn52xx;
2242 struct cvmx_gmxx_rxx_adr_cam_en_s cn52xxp1;
2243 struct cvmx_gmxx_rxx_adr_cam_en_s cn56xx;
2244 struct cvmx_gmxx_rxx_adr_cam_en_s cn56xxp1;
2245 struct cvmx_gmxx_rxx_adr_cam_en_s cn58xx;
2246 struct cvmx_gmxx_rxx_adr_cam_en_s cn58xxp1;
2247 struct cvmx_gmxx_rxx_adr_cam_en_s cn61xx;
2248 struct cvmx_gmxx_rxx_adr_cam_en_s cn63xx;
2249 struct cvmx_gmxx_rxx_adr_cam_en_s cn63xxp1;
2250 struct cvmx_gmxx_rxx_adr_cam_en_s cn66xx;
2251 struct cvmx_gmxx_rxx_adr_cam_en_s cn68xx;
2252 struct cvmx_gmxx_rxx_adr_cam_en_s cn68xxp1;
2253 struct cvmx_gmxx_rxx_adr_cam_en_s cn70xx;
2254 struct cvmx_gmxx_rxx_adr_cam_en_s cn70xxp1;
2255 struct cvmx_gmxx_rxx_adr_cam_en_s cnf71xx;
2256};
2257
2258typedef union cvmx_gmxx_rxx_adr_cam_en cvmx_gmxx_rxx_adr_cam_en_t;
2259
2260/**
2261 * cvmx_gmx#_rx#_adr_ctl
2262 *
2263 * GMX_RX_ADR_CTL = Address Filtering Control
2264 *
2265 *
2266 * Notes:
2267 * * ALGORITHM
2268 * Here is some pseudo code that represents the address filter behavior.
2269 *
2270 * @verbatim
2271 * bool dmac_addr_filter(uint8 prt, uint48 dmac) [
2272 * ASSERT(prt >= 0 && prt <= 3);
2273 * if (is_bcst(dmac)) // broadcast accept
2274 * return (GMX_RX[prt]_ADR_CTL[BCST] ? ACCEPT : REJECT);
2275 * if (is_mcst(dmac) & GMX_RX[prt]_ADR_CTL[MCST] == 1) // multicast reject
2276 * return REJECT;
2277 * if (is_mcst(dmac) & GMX_RX[prt]_ADR_CTL[MCST] == 2) // multicast accept
2278 * return ACCEPT;
2279 *
2280 * cam_hit = 0;
2281 *
2282 * for (i=0; i<32; i++) [
2283 * if (GMX_RX[prt]_ADR_CAM_ALL_EN[EN<i>] == 0)
2284 * continue;
2285 * uint48 unswizzled_mac_adr = 0x0;
2286 * for (j=5; j>=0; j--) [
2287 * unswizzled_mac_adr = (unswizzled_mac_adr << 8) | GMX_RX[i>>3]_ADR_CAM[j][ADR<(i&7)*8+7:(i&7)*8>];
2288 * ]
2289 * if (unswizzled_mac_adr == dmac) [
2290 * cam_hit = 1;
2291 * break;
2292 * ]
2293 * ]
2294 *
2295 * if (cam_hit)
2296 * return (GMX_RX[prt]_ADR_CTL[CAM_MODE] ? ACCEPT : REJECT);
2297 * else
2298 * return (GMX_RX[prt]_ADR_CTL[CAM_MODE] ? REJECT : ACCEPT);
2299 * ]
2300 * @endverbatim
2301 *
2302 * * XAUI Mode
2303 *
2304 * In XAUI mode, only GMX_RX0_ADR_CTL is used. GMX_RX[1,2,3]_ADR_CTL should not be used.
2305 */
2306union cvmx_gmxx_rxx_adr_ctl {
2307 u64 u64;
2308 struct cvmx_gmxx_rxx_adr_ctl_s {
2309 u64 reserved_4_63 : 60;
2310 u64 cam_mode : 1;
2311 u64 mcst : 2;
2312 u64 bcst : 1;
2313 } s;
2314 struct cvmx_gmxx_rxx_adr_ctl_s cn30xx;
2315 struct cvmx_gmxx_rxx_adr_ctl_s cn31xx;
2316 struct cvmx_gmxx_rxx_adr_ctl_s cn38xx;
2317 struct cvmx_gmxx_rxx_adr_ctl_s cn38xxp2;
2318 struct cvmx_gmxx_rxx_adr_ctl_s cn50xx;
2319 struct cvmx_gmxx_rxx_adr_ctl_s cn52xx;
2320 struct cvmx_gmxx_rxx_adr_ctl_s cn52xxp1;
2321 struct cvmx_gmxx_rxx_adr_ctl_s cn56xx;
2322 struct cvmx_gmxx_rxx_adr_ctl_s cn56xxp1;
2323 struct cvmx_gmxx_rxx_adr_ctl_s cn58xx;
2324 struct cvmx_gmxx_rxx_adr_ctl_s cn58xxp1;
2325 struct cvmx_gmxx_rxx_adr_ctl_s cn61xx;
2326 struct cvmx_gmxx_rxx_adr_ctl_s cn63xx;
2327 struct cvmx_gmxx_rxx_adr_ctl_s cn63xxp1;
2328 struct cvmx_gmxx_rxx_adr_ctl_s cn66xx;
2329 struct cvmx_gmxx_rxx_adr_ctl_s cn68xx;
2330 struct cvmx_gmxx_rxx_adr_ctl_s cn68xxp1;
2331 struct cvmx_gmxx_rxx_adr_ctl_s cn70xx;
2332 struct cvmx_gmxx_rxx_adr_ctl_s cn70xxp1;
2333 struct cvmx_gmxx_rxx_adr_ctl_s cnf71xx;
2334};
2335
2336typedef union cvmx_gmxx_rxx_adr_ctl cvmx_gmxx_rxx_adr_ctl_t;
2337
2338/**
2339 * cvmx_gmx#_rx#_decision
2340 *
2341 * GMX_RX_DECISION = The byte count to decide when to accept or filter a packet
2342 *
2343 *
2344 * Notes:
2345 * As each byte in a packet is received by GMX, the L2 byte count is compared
2346 * against the GMX_RX_DECISION[CNT]. The L2 byte count is the number of bytes
2347 * from the beginning of the L2 header (DMAC). In normal operation, the L2
2348 * header begins after the PREAMBLE+SFD (GMX_RX_FRM_CTL[PRE_CHK]=1) and any
2349 * optional UDD skip data (GMX_RX_UDD_SKP[LEN]).
2350 *
2351 * When GMX_RX_FRM_CTL[PRE_CHK] is clear, PREAMBLE+SFD are prepended to the
2352 * packet and would require UDD skip length to account for them.
2353 *
2354 * L2 Size
2355 * Port Mode <GMX_RX_DECISION bytes (default=24) >=GMX_RX_DECISION bytes (default=24)
2356 *
2357 * Full Duplex accept packet apply filters
2358 * no filtering is applied accept packet based on DMAC and PAUSE packet filters
2359 *
2360 * Half Duplex drop packet apply filters
2361 * packet is unconditionally dropped accept packet based on DMAC
2362 *
2363 * where l2_size = MAX(0, total_packet_size - GMX_RX_UDD_SKP[LEN] - ((GMX_RX_FRM_CTL[PRE_CHK]==1)*8)
2364 */
2365union cvmx_gmxx_rxx_decision {
2366 u64 u64;
2367 struct cvmx_gmxx_rxx_decision_s {
2368 u64 reserved_5_63 : 59;
2369 u64 cnt : 5;
2370 } s;
2371 struct cvmx_gmxx_rxx_decision_s cn30xx;
2372 struct cvmx_gmxx_rxx_decision_s cn31xx;
2373 struct cvmx_gmxx_rxx_decision_s cn38xx;
2374 struct cvmx_gmxx_rxx_decision_s cn38xxp2;
2375 struct cvmx_gmxx_rxx_decision_s cn50xx;
2376 struct cvmx_gmxx_rxx_decision_s cn52xx;
2377 struct cvmx_gmxx_rxx_decision_s cn52xxp1;
2378 struct cvmx_gmxx_rxx_decision_s cn56xx;
2379 struct cvmx_gmxx_rxx_decision_s cn56xxp1;
2380 struct cvmx_gmxx_rxx_decision_s cn58xx;
2381 struct cvmx_gmxx_rxx_decision_s cn58xxp1;
2382 struct cvmx_gmxx_rxx_decision_s cn61xx;
2383 struct cvmx_gmxx_rxx_decision_s cn63xx;
2384 struct cvmx_gmxx_rxx_decision_s cn63xxp1;
2385 struct cvmx_gmxx_rxx_decision_s cn66xx;
2386 struct cvmx_gmxx_rxx_decision_s cn68xx;
2387 struct cvmx_gmxx_rxx_decision_s cn68xxp1;
2388 struct cvmx_gmxx_rxx_decision_s cn70xx;
2389 struct cvmx_gmxx_rxx_decision_s cn70xxp1;
2390 struct cvmx_gmxx_rxx_decision_s cnf71xx;
2391};
2392
2393typedef union cvmx_gmxx_rxx_decision cvmx_gmxx_rxx_decision_t;
2394
2395/**
2396 * cvmx_gmx#_rx#_frm_chk
2397 *
2398 * GMX_RX_FRM_CHK = Which frame errors will set the ERR bit of the frame
2399 *
2400 *
2401 * Notes:
2402 * If GMX_RX_UDD_SKP[LEN] != 0, then LENERR will be forced to zero in HW.
2403 *
2404 * In XAUI mode prt0 is used for checking.
2405 */
2406union cvmx_gmxx_rxx_frm_chk {
2407 u64 u64;
2408 struct cvmx_gmxx_rxx_frm_chk_s {
2409 u64 reserved_10_63 : 54;
2410 u64 niberr : 1;
2411 u64 skperr : 1;
2412 u64 rcverr : 1;
2413 u64 lenerr : 1;
2414 u64 alnerr : 1;
2415 u64 fcserr : 1;
2416 u64 jabber : 1;
2417 u64 maxerr : 1;
2418 u64 carext : 1;
2419 u64 minerr : 1;
2420 } s;
2421 struct cvmx_gmxx_rxx_frm_chk_s cn30xx;
2422 struct cvmx_gmxx_rxx_frm_chk_s cn31xx;
2423 struct cvmx_gmxx_rxx_frm_chk_s cn38xx;
2424 struct cvmx_gmxx_rxx_frm_chk_s cn38xxp2;
2425 struct cvmx_gmxx_rxx_frm_chk_cn50xx {
2426 u64 reserved_10_63 : 54;
2427 u64 niberr : 1;
2428 u64 skperr : 1;
2429 u64 rcverr : 1;
2430 u64 reserved_6_6 : 1;
2431 u64 alnerr : 1;
2432 u64 fcserr : 1;
2433 u64 jabber : 1;
2434 u64 reserved_2_2 : 1;
2435 u64 carext : 1;
2436 u64 reserved_0_0 : 1;
2437 } cn50xx;
2438 struct cvmx_gmxx_rxx_frm_chk_cn52xx {
2439 u64 reserved_9_63 : 55;
2440 u64 skperr : 1;
2441 u64 rcverr : 1;
2442 u64 reserved_5_6 : 2;
2443 u64 fcserr : 1;
2444 u64 jabber : 1;
2445 u64 reserved_2_2 : 1;
2446 u64 carext : 1;
2447 u64 reserved_0_0 : 1;
2448 } cn52xx;
2449 struct cvmx_gmxx_rxx_frm_chk_cn52xx cn52xxp1;
2450 struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xx;
2451 struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xxp1;
2452 struct cvmx_gmxx_rxx_frm_chk_s cn58xx;
2453 struct cvmx_gmxx_rxx_frm_chk_s cn58xxp1;
2454 struct cvmx_gmxx_rxx_frm_chk_cn61xx {
2455 u64 reserved_9_63 : 55;
2456 u64 skperr : 1;
2457 u64 rcverr : 1;
2458 u64 reserved_5_6 : 2;
2459 u64 fcserr : 1;
2460 u64 jabber : 1;
2461 u64 reserved_2_2 : 1;
2462 u64 carext : 1;
2463 u64 minerr : 1;
2464 } cn61xx;
2465 struct cvmx_gmxx_rxx_frm_chk_cn61xx cn63xx;
2466 struct cvmx_gmxx_rxx_frm_chk_cn61xx cn63xxp1;
2467 struct cvmx_gmxx_rxx_frm_chk_cn61xx cn66xx;
2468 struct cvmx_gmxx_rxx_frm_chk_cn61xx cn68xx;
2469 struct cvmx_gmxx_rxx_frm_chk_cn61xx cn68xxp1;
2470 struct cvmx_gmxx_rxx_frm_chk_cn61xx cn70xx;
2471 struct cvmx_gmxx_rxx_frm_chk_cn61xx cn70xxp1;
2472 struct cvmx_gmxx_rxx_frm_chk_cn61xx cnf71xx;
2473};
2474
2475typedef union cvmx_gmxx_rxx_frm_chk cvmx_gmxx_rxx_frm_chk_t;
2476
2477/**
2478 * cvmx_gmx#_rx#_frm_ctl
2479 *
2480 * GMX_RX_FRM_CTL = Frame Control
2481 *
2482 *
2483 * Notes:
2484 * * PRE_STRP
2485 * When PRE_CHK is set (indicating that the PREAMBLE will be sent), PRE_STRP
2486 * determines if the PREAMBLE+SFD bytes are thrown away or sent to the Octane
2487 * core as part of the packet.
2488 *
2489 * In either mode, the PREAMBLE+SFD bytes are not counted toward the packet
2490 * size when checking against the MIN and MAX bounds. Furthermore, the bytes
2491 * are skipped when locating the start of the L2 header for DMAC and Control
2492 * frame recognition.
2493 *
2494 * * CTL_BCK/CTL_DRP
2495 * These bits control how the HW handles incoming PAUSE packets. Here are
2496 * the most common modes of operation:
2497 * CTL_BCK=1,CTL_DRP=1 - HW does it all
2498 * CTL_BCK=0,CTL_DRP=0 - SW sees all pause frames
2499 * CTL_BCK=0,CTL_DRP=1 - all pause frames are completely ignored
2500 *
2501 * These control bits should be set to CTL_BCK=0,CTL_DRP=0 in halfdup mode.
2502 * Since PAUSE packets only apply to fulldup operation, any PAUSE packet
2503 * would constitute an exception which should be handled by the processing
2504 * cores. PAUSE packets should not be forwarded.
2505 */
2506union cvmx_gmxx_rxx_frm_ctl {
2507 u64 u64;
2508 struct cvmx_gmxx_rxx_frm_ctl_s {
2509 u64 reserved_13_63 : 51;
2510 u64 ptp_mode : 1;
2511 u64 reserved_11_11 : 1;
2512 u64 null_dis : 1;
2513 u64 pre_align : 1;
2514 u64 pad_len : 1;
2515 u64 vlan_len : 1;
2516 u64 pre_free : 1;
2517 u64 ctl_smac : 1;
2518 u64 ctl_mcst : 1;
2519 u64 ctl_bck : 1;
2520 u64 ctl_drp : 1;
2521 u64 pre_strp : 1;
2522 u64 pre_chk : 1;
2523 } s;
2524 struct cvmx_gmxx_rxx_frm_ctl_cn30xx {
2525 u64 reserved_9_63 : 55;
2526 u64 pad_len : 1;
2527 u64 vlan_len : 1;
2528 u64 pre_free : 1;
2529 u64 ctl_smac : 1;
2530 u64 ctl_mcst : 1;
2531 u64 ctl_bck : 1;
2532 u64 ctl_drp : 1;
2533 u64 pre_strp : 1;
2534 u64 pre_chk : 1;
2535 } cn30xx;
2536 struct cvmx_gmxx_rxx_frm_ctl_cn31xx {
2537 u64 reserved_8_63 : 56;
2538 u64 vlan_len : 1;
2539 u64 pre_free : 1;
2540 u64 ctl_smac : 1;
2541 u64 ctl_mcst : 1;
2542 u64 ctl_bck : 1;
2543 u64 ctl_drp : 1;
2544 u64 pre_strp : 1;
2545 u64 pre_chk : 1;
2546 } cn31xx;
2547 struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn38xx;
2548 struct cvmx_gmxx_rxx_frm_ctl_cn31xx cn38xxp2;
2549 struct cvmx_gmxx_rxx_frm_ctl_cn50xx {
2550 u64 reserved_11_63 : 53;
2551 u64 null_dis : 1;
2552 u64 pre_align : 1;
2553 u64 reserved_7_8 : 2;
2554 u64 pre_free : 1;
2555 u64 ctl_smac : 1;
2556 u64 ctl_mcst : 1;
2557 u64 ctl_bck : 1;
2558 u64 ctl_drp : 1;
2559 u64 pre_strp : 1;
2560 u64 pre_chk : 1;
2561 } cn50xx;
2562 struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xx;
2563 struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xxp1;
2564 struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn56xx;
2565 struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 {
2566 u64 reserved_10_63 : 54;
2567 u64 pre_align : 1;
2568 u64 reserved_7_8 : 2;
2569 u64 pre_free : 1;
2570 u64 ctl_smac : 1;
2571 u64 ctl_mcst : 1;
2572 u64 ctl_bck : 1;
2573 u64 ctl_drp : 1;
2574 u64 pre_strp : 1;
2575 u64 pre_chk : 1;
2576 } cn56xxp1;
2577 struct cvmx_gmxx_rxx_frm_ctl_cn58xx {
2578 u64 reserved_11_63 : 53;
2579 u64 null_dis : 1;
2580 u64 pre_align : 1;
2581 u64 pad_len : 1;
2582 u64 vlan_len : 1;
2583 u64 pre_free : 1;
2584 u64 ctl_smac : 1;
2585 u64 ctl_mcst : 1;
2586 u64 ctl_bck : 1;
2587 u64 ctl_drp : 1;
2588 u64 pre_strp : 1;
2589 u64 pre_chk : 1;
2590 } cn58xx;
2591 struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn58xxp1;
2592 struct cvmx_gmxx_rxx_frm_ctl_cn61xx {
2593 u64 reserved_13_63 : 51;
2594 u64 ptp_mode : 1;
2595 u64 reserved_11_11 : 1;
2596 u64 null_dis : 1;
2597 u64 pre_align : 1;
2598 u64 reserved_7_8 : 2;
2599 u64 pre_free : 1;
2600 u64 ctl_smac : 1;
2601 u64 ctl_mcst : 1;
2602 u64 ctl_bck : 1;
2603 u64 ctl_drp : 1;
2604 u64 pre_strp : 1;
2605 u64 pre_chk : 1;
2606 } cn61xx;
2607 struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn63xx;
2608 struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn63xxp1;
2609 struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn66xx;
2610 struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn68xx;
2611 struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn68xxp1;
2612 struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn70xx;
2613 struct cvmx_gmxx_rxx_frm_ctl_cn61xx cn70xxp1;
2614 struct cvmx_gmxx_rxx_frm_ctl_cn61xx cnf71xx;
2615};
2616
2617typedef union cvmx_gmxx_rxx_frm_ctl cvmx_gmxx_rxx_frm_ctl_t;
2618
2619/**
2620 * cvmx_gmx#_rx#_frm_max
2621 *
2622 * GMX_RX_FRM_MAX = Frame Max length
2623 *
2624 *
2625 * Notes:
2626 * In spi4 mode, all spi4 ports use prt0 for checking.
2627 *
2628 * When changing the LEN field, be sure that LEN does not exceed
2629 * GMX_RX_JABBER[CNT]. Failure to meet this constraint will cause packets that
2630 * are within the maximum length parameter to be rejected because they exceed
2631 * the GMX_RX_JABBER[CNT] limit.
2632 */
2633union cvmx_gmxx_rxx_frm_max {
2634 u64 u64;
2635 struct cvmx_gmxx_rxx_frm_max_s {
2636 u64 reserved_16_63 : 48;
2637 u64 len : 16;
2638 } s;
2639 struct cvmx_gmxx_rxx_frm_max_s cn30xx;
2640 struct cvmx_gmxx_rxx_frm_max_s cn31xx;
2641 struct cvmx_gmxx_rxx_frm_max_s cn38xx;
2642 struct cvmx_gmxx_rxx_frm_max_s cn38xxp2;
2643 struct cvmx_gmxx_rxx_frm_max_s cn58xx;
2644 struct cvmx_gmxx_rxx_frm_max_s cn58xxp1;
2645};
2646
2647typedef union cvmx_gmxx_rxx_frm_max cvmx_gmxx_rxx_frm_max_t;
2648
2649/**
2650 * cvmx_gmx#_rx#_frm_min
2651 *
2652 * GMX_RX_FRM_MIN = Frame Min length
2653 *
2654 *
2655 * Notes:
2656 * In spi4 mode, all spi4 ports use prt0 for checking.
2657 *
2658 */
2659union cvmx_gmxx_rxx_frm_min {
2660 u64 u64;
2661 struct cvmx_gmxx_rxx_frm_min_s {
2662 u64 reserved_16_63 : 48;
2663 u64 len : 16;
2664 } s;
2665 struct cvmx_gmxx_rxx_frm_min_s cn30xx;
2666 struct cvmx_gmxx_rxx_frm_min_s cn31xx;
2667 struct cvmx_gmxx_rxx_frm_min_s cn38xx;
2668 struct cvmx_gmxx_rxx_frm_min_s cn38xxp2;
2669 struct cvmx_gmxx_rxx_frm_min_s cn58xx;
2670 struct cvmx_gmxx_rxx_frm_min_s cn58xxp1;
2671};
2672
2673typedef union cvmx_gmxx_rxx_frm_min cvmx_gmxx_rxx_frm_min_t;
2674
2675/**
2676 * cvmx_gmx#_rx#_ifg
2677 *
2678 * GMX_RX_IFG = RX Min IFG
2679 *
2680 */
2681union cvmx_gmxx_rxx_ifg {
2682 u64 u64;
2683 struct cvmx_gmxx_rxx_ifg_s {
2684 u64 reserved_4_63 : 60;
2685 u64 ifg : 4;
2686 } s;
2687 struct cvmx_gmxx_rxx_ifg_s cn30xx;
2688 struct cvmx_gmxx_rxx_ifg_s cn31xx;
2689 struct cvmx_gmxx_rxx_ifg_s cn38xx;
2690 struct cvmx_gmxx_rxx_ifg_s cn38xxp2;
2691 struct cvmx_gmxx_rxx_ifg_s cn50xx;
2692 struct cvmx_gmxx_rxx_ifg_s cn52xx;
2693 struct cvmx_gmxx_rxx_ifg_s cn52xxp1;
2694 struct cvmx_gmxx_rxx_ifg_s cn56xx;
2695 struct cvmx_gmxx_rxx_ifg_s cn56xxp1;
2696 struct cvmx_gmxx_rxx_ifg_s cn58xx;
2697 struct cvmx_gmxx_rxx_ifg_s cn58xxp1;
2698 struct cvmx_gmxx_rxx_ifg_s cn61xx;
2699 struct cvmx_gmxx_rxx_ifg_s cn63xx;
2700 struct cvmx_gmxx_rxx_ifg_s cn63xxp1;
2701 struct cvmx_gmxx_rxx_ifg_s cn66xx;
2702 struct cvmx_gmxx_rxx_ifg_s cn68xx;
2703 struct cvmx_gmxx_rxx_ifg_s cn68xxp1;
2704 struct cvmx_gmxx_rxx_ifg_s cn70xx;
2705 struct cvmx_gmxx_rxx_ifg_s cn70xxp1;
2706 struct cvmx_gmxx_rxx_ifg_s cnf71xx;
2707};
2708
2709typedef union cvmx_gmxx_rxx_ifg cvmx_gmxx_rxx_ifg_t;
2710
2711/**
2712 * cvmx_gmx#_rx#_int_en
2713 *
2714 * GMX_RX_INT_EN = Interrupt Enable
2715 *
2716 *
2717 * Notes:
2718 * In XAUI mode prt0 is used for checking.
2719 *
2720 */
2721union cvmx_gmxx_rxx_int_en {
2722 u64 u64;
2723 struct cvmx_gmxx_rxx_int_en_s {
2724 u64 reserved_30_63 : 34;
2725 u64 wol : 1;
2726 u64 hg2cc : 1;
2727 u64 hg2fld : 1;
2728 u64 undat : 1;
2729 u64 uneop : 1;
2730 u64 unsop : 1;
2731 u64 bad_term : 1;
2732 u64 bad_seq : 1;
2733 u64 rem_fault : 1;
2734 u64 loc_fault : 1;
2735 u64 pause_drp : 1;
2736 u64 phy_dupx : 1;
2737 u64 phy_spd : 1;
2738 u64 phy_link : 1;
2739 u64 ifgerr : 1;
2740 u64 coldet : 1;
2741 u64 falerr : 1;
2742 u64 rsverr : 1;
2743 u64 pcterr : 1;
2744 u64 ovrerr : 1;
2745 u64 niberr : 1;
2746 u64 skperr : 1;
2747 u64 rcverr : 1;
2748 u64 lenerr : 1;
2749 u64 alnerr : 1;
2750 u64 fcserr : 1;
2751 u64 jabber : 1;
2752 u64 maxerr : 1;
2753 u64 carext : 1;
2754 u64 minerr : 1;
2755 } s;
2756 struct cvmx_gmxx_rxx_int_en_cn30xx {
2757 u64 reserved_19_63 : 45;
2758 u64 phy_dupx : 1;
2759 u64 phy_spd : 1;
2760 u64 phy_link : 1;
2761 u64 ifgerr : 1;
2762 u64 coldet : 1;
2763 u64 falerr : 1;
2764 u64 rsverr : 1;
2765 u64 pcterr : 1;
2766 u64 ovrerr : 1;
2767 u64 niberr : 1;
2768 u64 skperr : 1;
2769 u64 rcverr : 1;
2770 u64 lenerr : 1;
2771 u64 alnerr : 1;
2772 u64 fcserr : 1;
2773 u64 jabber : 1;
2774 u64 maxerr : 1;
2775 u64 carext : 1;
2776 u64 minerr : 1;
2777 } cn30xx;
2778 struct cvmx_gmxx_rxx_int_en_cn30xx cn31xx;
2779 struct cvmx_gmxx_rxx_int_en_cn30xx cn38xx;
2780 struct cvmx_gmxx_rxx_int_en_cn30xx cn38xxp2;
2781 struct cvmx_gmxx_rxx_int_en_cn50xx {
2782 u64 reserved_20_63 : 44;
2783 u64 pause_drp : 1;
2784 u64 phy_dupx : 1;
2785 u64 phy_spd : 1;
2786 u64 phy_link : 1;
2787 u64 ifgerr : 1;
2788 u64 coldet : 1;
2789 u64 falerr : 1;
2790 u64 rsverr : 1;
2791 u64 pcterr : 1;
2792 u64 ovrerr : 1;
2793 u64 niberr : 1;
2794 u64 skperr : 1;
2795 u64 rcverr : 1;
2796 u64 reserved_6_6 : 1;
2797 u64 alnerr : 1;
2798 u64 fcserr : 1;
2799 u64 jabber : 1;
2800 u64 reserved_2_2 : 1;
2801 u64 carext : 1;
2802 u64 reserved_0_0 : 1;
2803 } cn50xx;
2804 struct cvmx_gmxx_rxx_int_en_cn52xx {
2805 u64 reserved_29_63 : 35;
2806 u64 hg2cc : 1;
2807 u64 hg2fld : 1;
2808 u64 undat : 1;
2809 u64 uneop : 1;
2810 u64 unsop : 1;
2811 u64 bad_term : 1;
2812 u64 bad_seq : 1;
2813 u64 rem_fault : 1;
2814 u64 loc_fault : 1;
2815 u64 pause_drp : 1;
2816 u64 reserved_16_18 : 3;
2817 u64 ifgerr : 1;
2818 u64 coldet : 1;
2819 u64 falerr : 1;
2820 u64 rsverr : 1;
2821 u64 pcterr : 1;
2822 u64 ovrerr : 1;
2823 u64 reserved_9_9 : 1;
2824 u64 skperr : 1;
2825 u64 rcverr : 1;
2826 u64 reserved_5_6 : 2;
2827 u64 fcserr : 1;
2828 u64 jabber : 1;
2829 u64 reserved_2_2 : 1;
2830 u64 carext : 1;
2831 u64 reserved_0_0 : 1;
2832 } cn52xx;
2833 struct cvmx_gmxx_rxx_int_en_cn52xx cn52xxp1;
2834 struct cvmx_gmxx_rxx_int_en_cn52xx cn56xx;
2835 struct cvmx_gmxx_rxx_int_en_cn56xxp1 {
2836 u64 reserved_27_63 : 37;
2837 u64 undat : 1;
2838 u64 uneop : 1;
2839 u64 unsop : 1;
2840 u64 bad_term : 1;
2841 u64 bad_seq : 1;
2842 u64 rem_fault : 1;
2843 u64 loc_fault : 1;
2844 u64 pause_drp : 1;
2845 u64 reserved_16_18 : 3;
2846 u64 ifgerr : 1;
2847 u64 coldet : 1;
2848 u64 falerr : 1;
2849 u64 rsverr : 1;
2850 u64 pcterr : 1;
2851 u64 ovrerr : 1;
2852 u64 reserved_9_9 : 1;
2853 u64 skperr : 1;
2854 u64 rcverr : 1;
2855 u64 reserved_5_6 : 2;
2856 u64 fcserr : 1;
2857 u64 jabber : 1;
2858 u64 reserved_2_2 : 1;
2859 u64 carext : 1;
2860 u64 reserved_0_0 : 1;
2861 } cn56xxp1;
2862 struct cvmx_gmxx_rxx_int_en_cn58xx {
2863 u64 reserved_20_63 : 44;
2864 u64 pause_drp : 1;
2865 u64 phy_dupx : 1;
2866 u64 phy_spd : 1;
2867 u64 phy_link : 1;
2868 u64 ifgerr : 1;
2869 u64 coldet : 1;
2870 u64 falerr : 1;
2871 u64 rsverr : 1;
2872 u64 pcterr : 1;
2873 u64 ovrerr : 1;
2874 u64 niberr : 1;
2875 u64 skperr : 1;
2876 u64 rcverr : 1;
2877 u64 lenerr : 1;
2878 u64 alnerr : 1;
2879 u64 fcserr : 1;
2880 u64 jabber : 1;
2881 u64 maxerr : 1;
2882 u64 carext : 1;
2883 u64 minerr : 1;
2884 } cn58xx;
2885 struct cvmx_gmxx_rxx_int_en_cn58xx cn58xxp1;
2886 struct cvmx_gmxx_rxx_int_en_cn61xx {
2887 u64 reserved_29_63 : 35;
2888 u64 hg2cc : 1;
2889 u64 hg2fld : 1;
2890 u64 undat : 1;
2891 u64 uneop : 1;
2892 u64 unsop : 1;
2893 u64 bad_term : 1;
2894 u64 bad_seq : 1;
2895 u64 rem_fault : 1;
2896 u64 loc_fault : 1;
2897 u64 pause_drp : 1;
2898 u64 reserved_16_18 : 3;
2899 u64 ifgerr : 1;
2900 u64 coldet : 1;
2901 u64 falerr : 1;
2902 u64 rsverr : 1;
2903 u64 pcterr : 1;
2904 u64 ovrerr : 1;
2905 u64 reserved_9_9 : 1;
2906 u64 skperr : 1;
2907 u64 rcverr : 1;
2908 u64 reserved_5_6 : 2;
2909 u64 fcserr : 1;
2910 u64 jabber : 1;
2911 u64 reserved_2_2 : 1;
2912 u64 carext : 1;
2913 u64 minerr : 1;
2914 } cn61xx;
2915 struct cvmx_gmxx_rxx_int_en_cn61xx cn63xx;
2916 struct cvmx_gmxx_rxx_int_en_cn61xx cn63xxp1;
2917 struct cvmx_gmxx_rxx_int_en_cn61xx cn66xx;
2918 struct cvmx_gmxx_rxx_int_en_cn61xx cn68xx;
2919 struct cvmx_gmxx_rxx_int_en_cn61xx cn68xxp1;
2920 struct cvmx_gmxx_rxx_int_en_cn70xx {
2921 u64 reserved_30_63 : 34;
2922 u64 wol : 1;
2923 u64 hg2cc : 1;
2924 u64 hg2fld : 1;
2925 u64 undat : 1;
2926 u64 uneop : 1;
2927 u64 unsop : 1;
2928 u64 bad_term : 1;
2929 u64 bad_seq : 1;
2930 u64 rem_fault : 1;
2931 u64 loc_fault : 1;
2932 u64 pause_drp : 1;
2933 u64 reserved_16_18 : 3;
2934 u64 ifgerr : 1;
2935 u64 coldet : 1;
2936 u64 falerr : 1;
2937 u64 rsverr : 1;
2938 u64 pcterr : 1;
2939 u64 ovrerr : 1;
2940 u64 reserved_9_9 : 1;
2941 u64 skperr : 1;
2942 u64 rcverr : 1;
2943 u64 reserved_5_6 : 2;
2944 u64 fcserr : 1;
2945 u64 jabber : 1;
2946 u64 reserved_2_2 : 1;
2947 u64 carext : 1;
2948 u64 minerr : 1;
2949 } cn70xx;
2950 struct cvmx_gmxx_rxx_int_en_cn70xx cn70xxp1;
2951 struct cvmx_gmxx_rxx_int_en_cn61xx cnf71xx;
2952};
2953
2954typedef union cvmx_gmxx_rxx_int_en cvmx_gmxx_rxx_int_en_t;
2955
2956/**
2957 * cvmx_gmx#_rx#_int_reg
2958 *
2959 * GMX_RX_INT_REG = Interrupt Register
2960 *
2961 *
2962 * Notes:
2963 * (1) exceptions will only be raised to the control processor if the
2964 * corresponding bit in the GMX_RX_INT_EN register is set.
2965 *
2966 * (2) exception conditions 10:0 can also set the rcv/opcode in the received
2967 * packet's workQ entry. The GMX_RX_FRM_CHK register provides a bit mask
2968 * for configuring which conditions set the error.
2969 *
2970 * (3) in half duplex operation, the expectation is that collisions will appear
2971 * as either MINERR o r CAREXT errors.
2972 *
2973 * (4) JABBER - An RX Jabber error indicates that a packet was received which
2974 * is longer than the maximum allowed packet as defined by the
2975 * system. GMX will truncate the packet at the JABBER count.
2976 * Failure to do so could lead to system instabilty.
2977 *
2978 * (5) NIBERR - This error is illegal at 1000Mbs speeds
2979 * (GMX_RX_PRT_CFG[SPEED]==0) and will never assert.
2980 *
2981 * (6) MAXERR - for untagged frames, the total frame DA+SA+TL+DATA+PAD+FCS >
2982 * GMX_RX_FRM_MAX. For tagged frames, DA+SA+VLAN+TL+DATA+PAD+FCS
2983 * > GMX_RX_FRM_MAX + 4*VLAN_VAL + 4*VLAN_STACKED.
2984 *
2985 * (7) MINERR - total frame DA+SA+TL+DATA+PAD+FCS < 64
2986 *
2987 * (8) ALNERR - Indicates that the packet received was not an integer number of
2988 * bytes. If FCS checking is enabled, ALNERR will only assert if
2989 * the FCS is bad. If FCS checking is disabled, ALNERR will
2990 * assert in all non-integer frame cases.
2991 *
2992 * (9) Collisions - Collisions can only occur in half-duplex mode. A collision
2993 * is assumed by the receiver when the slottime
2994 * (GMX_PRT_CFG[SLOTTIME]) is not satisfied. In 10/100 mode,
2995 * this will result in a frame < SLOTTIME. In 1000 mode, it
2996 * could result either in frame < SLOTTIME or a carrier extend
2997 * error with the SLOTTIME. These conditions are visible by...
2998 *
2999 * . transfer ended before slottime - COLDET
3000 * . carrier extend error - CAREXT
3001 *
3002 * (A) LENERR - Length errors occur when the received packet does not match the
3003 * length field. LENERR is only checked for packets between 64
3004 * and 1500 bytes. For untagged frames, the length must exact
3005 * match. For tagged frames the length or length+4 must match.
3006 *
3007 * (B) PCTERR - checks that the frame begins with a valid PREAMBLE sequence.
3008 * Does not check the number of PREAMBLE cycles.
3009 *
3010 * (C) OVRERR -
3011 *
3012 * OVRERR is an architectural assertion check internal to GMX to
3013 * make sure no assumption was violated. In a correctly operating
3014 * system, this interrupt can never fire.
3015 *
3016 * GMX has an internal arbiter which selects which of 4 ports to
3017 * buffer in the main RX FIFO. If we normally buffer 8 bytes,
3018 * then each port will typically push a tick every 8 cycles - if
3019 * the packet interface is going as fast as possible. If there
3020 * are four ports, they push every two cycles. So that's the
3021 * assumption. That the inbound module will always be able to
3022 * consume the tick before another is produced. If that doesn't
3023 * happen - that's when OVRERR will assert.
3024 *
3025 * (D) In XAUI mode prt0 is used for interrupt logging.
3026 */
3027union cvmx_gmxx_rxx_int_reg {
3028 u64 u64;
3029 struct cvmx_gmxx_rxx_int_reg_s {
3030 u64 reserved_30_63 : 34;
3031 u64 wol : 1;
3032 u64 hg2cc : 1;
3033 u64 hg2fld : 1;
3034 u64 undat : 1;
3035 u64 uneop : 1;
3036 u64 unsop : 1;
3037 u64 bad_term : 1;
3038 u64 bad_seq : 1;
3039 u64 rem_fault : 1;
3040 u64 loc_fault : 1;
3041 u64 pause_drp : 1;
3042 u64 phy_dupx : 1;
3043 u64 phy_spd : 1;
3044 u64 phy_link : 1;
3045 u64 ifgerr : 1;
3046 u64 coldet : 1;
3047 u64 falerr : 1;
3048 u64 rsverr : 1;
3049 u64 pcterr : 1;
3050 u64 ovrerr : 1;
3051 u64 niberr : 1;
3052 u64 skperr : 1;
3053 u64 rcverr : 1;
3054 u64 lenerr : 1;
3055 u64 alnerr : 1;
3056 u64 fcserr : 1;
3057 u64 jabber : 1;
3058 u64 maxerr : 1;
3059 u64 carext : 1;
3060 u64 minerr : 1;
3061 } s;
3062 struct cvmx_gmxx_rxx_int_reg_cn30xx {
3063 u64 reserved_19_63 : 45;
3064 u64 phy_dupx : 1;
3065 u64 phy_spd : 1;
3066 u64 phy_link : 1;
3067 u64 ifgerr : 1;
3068 u64 coldet : 1;
3069 u64 falerr : 1;
3070 u64 rsverr : 1;
3071 u64 pcterr : 1;
3072 u64 ovrerr : 1;
3073 u64 niberr : 1;
3074 u64 skperr : 1;
3075 u64 rcverr : 1;
3076 u64 lenerr : 1;
3077 u64 alnerr : 1;
3078 u64 fcserr : 1;
3079 u64 jabber : 1;
3080 u64 maxerr : 1;
3081 u64 carext : 1;
3082 u64 minerr : 1;
3083 } cn30xx;
3084 struct cvmx_gmxx_rxx_int_reg_cn30xx cn31xx;
3085 struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xx;
3086 struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xxp2;
3087 struct cvmx_gmxx_rxx_int_reg_cn50xx {
3088 u64 reserved_20_63 : 44;
3089 u64 pause_drp : 1;
3090 u64 phy_dupx : 1;
3091 u64 phy_spd : 1;
3092 u64 phy_link : 1;
3093 u64 ifgerr : 1;
3094 u64 coldet : 1;
3095 u64 falerr : 1;
3096 u64 rsverr : 1;
3097 u64 pcterr : 1;
3098 u64 ovrerr : 1;
3099 u64 niberr : 1;
3100 u64 skperr : 1;
3101 u64 rcverr : 1;
3102 u64 reserved_6_6 : 1;
3103 u64 alnerr : 1;
3104 u64 fcserr : 1;
3105 u64 jabber : 1;
3106 u64 reserved_2_2 : 1;
3107 u64 carext : 1;
3108 u64 reserved_0_0 : 1;
3109 } cn50xx;
3110 struct cvmx_gmxx_rxx_int_reg_cn52xx {
3111 u64 reserved_29_63 : 35;
3112 u64 hg2cc : 1;
3113 u64 hg2fld : 1;
3114 u64 undat : 1;
3115 u64 uneop : 1;
3116 u64 unsop : 1;
3117 u64 bad_term : 1;
3118 u64 bad_seq : 1;
3119 u64 rem_fault : 1;
3120 u64 loc_fault : 1;
3121 u64 pause_drp : 1;
3122 u64 reserved_16_18 : 3;
3123 u64 ifgerr : 1;
3124 u64 coldet : 1;
3125 u64 falerr : 1;
3126 u64 rsverr : 1;
3127 u64 pcterr : 1;
3128 u64 ovrerr : 1;
3129 u64 reserved_9_9 : 1;
3130 u64 skperr : 1;
3131 u64 rcverr : 1;
3132 u64 reserved_5_6 : 2;
3133 u64 fcserr : 1;
3134 u64 jabber : 1;
3135 u64 reserved_2_2 : 1;
3136 u64 carext : 1;
3137 u64 reserved_0_0 : 1;
3138 } cn52xx;
3139 struct cvmx_gmxx_rxx_int_reg_cn52xx cn52xxp1;
3140 struct cvmx_gmxx_rxx_int_reg_cn52xx cn56xx;
3141 struct cvmx_gmxx_rxx_int_reg_cn56xxp1 {
3142 u64 reserved_27_63 : 37;
3143 u64 undat : 1;
3144 u64 uneop : 1;
3145 u64 unsop : 1;
3146 u64 bad_term : 1;
3147 u64 bad_seq : 1;
3148 u64 rem_fault : 1;
3149 u64 loc_fault : 1;
3150 u64 pause_drp : 1;
3151 u64 reserved_16_18 : 3;
3152 u64 ifgerr : 1;
3153 u64 coldet : 1;
3154 u64 falerr : 1;
3155 u64 rsverr : 1;
3156 u64 pcterr : 1;
3157 u64 ovrerr : 1;
3158 u64 reserved_9_9 : 1;
3159 u64 skperr : 1;
3160 u64 rcverr : 1;
3161 u64 reserved_5_6 : 2;
3162 u64 fcserr : 1;
3163 u64 jabber : 1;
3164 u64 reserved_2_2 : 1;
3165 u64 carext : 1;
3166 u64 reserved_0_0 : 1;
3167 } cn56xxp1;
3168 struct cvmx_gmxx_rxx_int_reg_cn58xx {
3169 u64 reserved_20_63 : 44;
3170 u64 pause_drp : 1;
3171 u64 phy_dupx : 1;
3172 u64 phy_spd : 1;
3173 u64 phy_link : 1;
3174 u64 ifgerr : 1;
3175 u64 coldet : 1;
3176 u64 falerr : 1;
3177 u64 rsverr : 1;
3178 u64 pcterr : 1;
3179 u64 ovrerr : 1;
3180 u64 niberr : 1;
3181 u64 skperr : 1;
3182 u64 rcverr : 1;
3183 u64 lenerr : 1;
3184 u64 alnerr : 1;
3185 u64 fcserr : 1;
3186 u64 jabber : 1;
3187 u64 maxerr : 1;
3188 u64 carext : 1;
3189 u64 minerr : 1;
3190 } cn58xx;
3191 struct cvmx_gmxx_rxx_int_reg_cn58xx cn58xxp1;
3192 struct cvmx_gmxx_rxx_int_reg_cn61xx {
3193 u64 reserved_29_63 : 35;
3194 u64 hg2cc : 1;
3195 u64 hg2fld : 1;
3196 u64 undat : 1;
3197 u64 uneop : 1;
3198 u64 unsop : 1;
3199 u64 bad_term : 1;
3200 u64 bad_seq : 1;
3201 u64 rem_fault : 1;
3202 u64 loc_fault : 1;
3203 u64 pause_drp : 1;
3204 u64 reserved_16_18 : 3;
3205 u64 ifgerr : 1;
3206 u64 coldet : 1;
3207 u64 falerr : 1;
3208 u64 rsverr : 1;
3209 u64 pcterr : 1;
3210 u64 ovrerr : 1;
3211 u64 reserved_9_9 : 1;
3212 u64 skperr : 1;
3213 u64 rcverr : 1;
3214 u64 reserved_5_6 : 2;
3215 u64 fcserr : 1;
3216 u64 jabber : 1;
3217 u64 reserved_2_2 : 1;
3218 u64 carext : 1;
3219 u64 minerr : 1;
3220 } cn61xx;
3221 struct cvmx_gmxx_rxx_int_reg_cn61xx cn63xx;
3222 struct cvmx_gmxx_rxx_int_reg_cn61xx cn63xxp1;
3223 struct cvmx_gmxx_rxx_int_reg_cn61xx cn66xx;
3224 struct cvmx_gmxx_rxx_int_reg_cn61xx cn68xx;
3225 struct cvmx_gmxx_rxx_int_reg_cn61xx cn68xxp1;
3226 struct cvmx_gmxx_rxx_int_reg_cn70xx {
3227 u64 reserved_30_63 : 34;
3228 u64 wol : 1;
3229 u64 hg2cc : 1;
3230 u64 hg2fld : 1;
3231 u64 undat : 1;
3232 u64 uneop : 1;
3233 u64 unsop : 1;
3234 u64 bad_term : 1;
3235 u64 bad_seq : 1;
3236 u64 rem_fault : 1;
3237 u64 loc_fault : 1;
3238 u64 pause_drp : 1;
3239 u64 reserved_16_18 : 3;
3240 u64 ifgerr : 1;
3241 u64 coldet : 1;
3242 u64 falerr : 1;
3243 u64 rsverr : 1;
3244 u64 pcterr : 1;
3245 u64 ovrerr : 1;
3246 u64 reserved_9_9 : 1;
3247 u64 skperr : 1;
3248 u64 rcverr : 1;
3249 u64 reserved_5_6 : 2;
3250 u64 fcserr : 1;
3251 u64 jabber : 1;
3252 u64 reserved_2_2 : 1;
3253 u64 carext : 1;
3254 u64 minerr : 1;
3255 } cn70xx;
3256 struct cvmx_gmxx_rxx_int_reg_cn70xx cn70xxp1;
3257 struct cvmx_gmxx_rxx_int_reg_cn61xx cnf71xx;
3258};
3259
3260typedef union cvmx_gmxx_rxx_int_reg cvmx_gmxx_rxx_int_reg_t;
3261
3262/**
3263 * cvmx_gmx#_rx#_jabber
3264 *
3265 * GMX_RX_JABBER = The max size packet after which GMX will truncate
3266 *
3267 *
3268 * Notes:
3269 * CNT must be 8-byte aligned such that CNT[2:0] == 0
3270 *
3271 * The packet that will be sent to the packet input logic will have an
3272 * additionl 8 bytes if GMX_RX_FRM_CTL[PRE_CHK] is set and
3273 * GMX_RX_FRM_CTL[PRE_STRP] is clear. The max packet that will be sent is
3274 * defined as...
3275 *
3276 * max_sized_packet = GMX_RX_JABBER[CNT]+((GMX_RX_FRM_CTL[PRE_CHK] & !GMX_RX_FRM_CTL[PRE_STRP])*8)
3277 *
3278 * In XAUI mode prt0 is used for checking.
3279 */
3280union cvmx_gmxx_rxx_jabber {
3281 u64 u64;
3282 struct cvmx_gmxx_rxx_jabber_s {
3283 u64 reserved_16_63 : 48;
3284 u64 cnt : 16;
3285 } s;
3286 struct cvmx_gmxx_rxx_jabber_s cn30xx;
3287 struct cvmx_gmxx_rxx_jabber_s cn31xx;
3288 struct cvmx_gmxx_rxx_jabber_s cn38xx;
3289 struct cvmx_gmxx_rxx_jabber_s cn38xxp2;
3290 struct cvmx_gmxx_rxx_jabber_s cn50xx;
3291 struct cvmx_gmxx_rxx_jabber_s cn52xx;
3292 struct cvmx_gmxx_rxx_jabber_s cn52xxp1;
3293 struct cvmx_gmxx_rxx_jabber_s cn56xx;
3294 struct cvmx_gmxx_rxx_jabber_s cn56xxp1;
3295 struct cvmx_gmxx_rxx_jabber_s cn58xx;
3296 struct cvmx_gmxx_rxx_jabber_s cn58xxp1;
3297 struct cvmx_gmxx_rxx_jabber_s cn61xx;
3298 struct cvmx_gmxx_rxx_jabber_s cn63xx;
3299 struct cvmx_gmxx_rxx_jabber_s cn63xxp1;
3300 struct cvmx_gmxx_rxx_jabber_s cn66xx;
3301 struct cvmx_gmxx_rxx_jabber_s cn68xx;
3302 struct cvmx_gmxx_rxx_jabber_s cn68xxp1;
3303 struct cvmx_gmxx_rxx_jabber_s cn70xx;
3304 struct cvmx_gmxx_rxx_jabber_s cn70xxp1;
3305 struct cvmx_gmxx_rxx_jabber_s cnf71xx;
3306};
3307
3308typedef union cvmx_gmxx_rxx_jabber cvmx_gmxx_rxx_jabber_t;
3309
3310/**
3311 * cvmx_gmx#_rx#_pause_drop_time
3312 *
3313 * GMX_RX_PAUSE_DROP_TIME = The TIME field in a PAUSE Packet which was dropped due to GMX RX FIFO full condition
3314 *
3315 */
3316union cvmx_gmxx_rxx_pause_drop_time {
3317 u64 u64;
3318 struct cvmx_gmxx_rxx_pause_drop_time_s {
3319 u64 reserved_16_63 : 48;
3320 u64 status : 16;
3321 } s;
3322 struct cvmx_gmxx_rxx_pause_drop_time_s cn50xx;
3323 struct cvmx_gmxx_rxx_pause_drop_time_s cn52xx;
3324 struct cvmx_gmxx_rxx_pause_drop_time_s cn52xxp1;
3325 struct cvmx_gmxx_rxx_pause_drop_time_s cn56xx;
3326 struct cvmx_gmxx_rxx_pause_drop_time_s cn56xxp1;
3327 struct cvmx_gmxx_rxx_pause_drop_time_s cn58xx;
3328 struct cvmx_gmxx_rxx_pause_drop_time_s cn58xxp1;
3329 struct cvmx_gmxx_rxx_pause_drop_time_s cn61xx;
3330 struct cvmx_gmxx_rxx_pause_drop_time_s cn63xx;
3331 struct cvmx_gmxx_rxx_pause_drop_time_s cn63xxp1;
3332 struct cvmx_gmxx_rxx_pause_drop_time_s cn66xx;
3333 struct cvmx_gmxx_rxx_pause_drop_time_s cn68xx;
3334 struct cvmx_gmxx_rxx_pause_drop_time_s cn68xxp1;
3335 struct cvmx_gmxx_rxx_pause_drop_time_s cn70xx;
3336 struct cvmx_gmxx_rxx_pause_drop_time_s cn70xxp1;
3337 struct cvmx_gmxx_rxx_pause_drop_time_s cnf71xx;
3338};
3339
3340typedef union cvmx_gmxx_rxx_pause_drop_time cvmx_gmxx_rxx_pause_drop_time_t;
3341
3342/**
3343 * cvmx_gmx#_rx#_rx_inbnd
3344 *
3345 * GMX_RX_INBND = RGMII InBand Link Status
3346 *
3347 *
3348 * Notes:
3349 * These fields are only valid if the attached PHY is operating in RGMII mode
3350 * and supports the optional in-band status (see section 3.4.1 of the RGMII
3351 * specification, version 1.3 for more information).
3352 */
3353union cvmx_gmxx_rxx_rx_inbnd {
3354 u64 u64;
3355 struct cvmx_gmxx_rxx_rx_inbnd_s {
3356 u64 reserved_4_63 : 60;
3357 u64 duplex : 1;
3358 u64 speed : 2;
3359 u64 status : 1;
3360 } s;
3361 struct cvmx_gmxx_rxx_rx_inbnd_s cn30xx;
3362 struct cvmx_gmxx_rxx_rx_inbnd_s cn31xx;
3363 struct cvmx_gmxx_rxx_rx_inbnd_s cn38xx;
3364 struct cvmx_gmxx_rxx_rx_inbnd_s cn38xxp2;
3365 struct cvmx_gmxx_rxx_rx_inbnd_s cn50xx;
3366 struct cvmx_gmxx_rxx_rx_inbnd_s cn58xx;
3367 struct cvmx_gmxx_rxx_rx_inbnd_s cn58xxp1;
3368};
3369
3370typedef union cvmx_gmxx_rxx_rx_inbnd cvmx_gmxx_rxx_rx_inbnd_t;
3371
3372/**
3373 * cvmx_gmx#_rx#_stats_ctl
3374 *
3375 * GMX_RX_STATS_CTL = RX Stats Control register
3376 *
3377 */
3378union cvmx_gmxx_rxx_stats_ctl {
3379 u64 u64;
3380 struct cvmx_gmxx_rxx_stats_ctl_s {
3381 u64 reserved_1_63 : 63;
3382 u64 rd_clr : 1;
3383 } s;
3384 struct cvmx_gmxx_rxx_stats_ctl_s cn30xx;
3385 struct cvmx_gmxx_rxx_stats_ctl_s cn31xx;
3386 struct cvmx_gmxx_rxx_stats_ctl_s cn38xx;
3387 struct cvmx_gmxx_rxx_stats_ctl_s cn38xxp2;
3388 struct cvmx_gmxx_rxx_stats_ctl_s cn50xx;
3389 struct cvmx_gmxx_rxx_stats_ctl_s cn52xx;
3390 struct cvmx_gmxx_rxx_stats_ctl_s cn52xxp1;
3391 struct cvmx_gmxx_rxx_stats_ctl_s cn56xx;
3392 struct cvmx_gmxx_rxx_stats_ctl_s cn56xxp1;
3393 struct cvmx_gmxx_rxx_stats_ctl_s cn58xx;
3394 struct cvmx_gmxx_rxx_stats_ctl_s cn58xxp1;
3395 struct cvmx_gmxx_rxx_stats_ctl_s cn61xx;
3396 struct cvmx_gmxx_rxx_stats_ctl_s cn63xx;
3397 struct cvmx_gmxx_rxx_stats_ctl_s cn63xxp1;
3398 struct cvmx_gmxx_rxx_stats_ctl_s cn66xx;
3399 struct cvmx_gmxx_rxx_stats_ctl_s cn68xx;
3400 struct cvmx_gmxx_rxx_stats_ctl_s cn68xxp1;
3401 struct cvmx_gmxx_rxx_stats_ctl_s cn70xx;
3402 struct cvmx_gmxx_rxx_stats_ctl_s cn70xxp1;
3403 struct cvmx_gmxx_rxx_stats_ctl_s cnf71xx;
3404};
3405
3406typedef union cvmx_gmxx_rxx_stats_ctl cvmx_gmxx_rxx_stats_ctl_t;
3407
3408/**
3409 * cvmx_gmx#_rx#_stats_octs
3410 *
3411 * Notes:
3412 * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
3413 * - Counters will wrap
3414 */
3415union cvmx_gmxx_rxx_stats_octs {
3416 u64 u64;
3417 struct cvmx_gmxx_rxx_stats_octs_s {
3418 u64 reserved_48_63 : 16;
3419 u64 cnt : 48;
3420 } s;
3421 struct cvmx_gmxx_rxx_stats_octs_s cn30xx;
3422 struct cvmx_gmxx_rxx_stats_octs_s cn31xx;
3423 struct cvmx_gmxx_rxx_stats_octs_s cn38xx;
3424 struct cvmx_gmxx_rxx_stats_octs_s cn38xxp2;
3425 struct cvmx_gmxx_rxx_stats_octs_s cn50xx;
3426 struct cvmx_gmxx_rxx_stats_octs_s cn52xx;
3427 struct cvmx_gmxx_rxx_stats_octs_s cn52xxp1;
3428 struct cvmx_gmxx_rxx_stats_octs_s cn56xx;
3429 struct cvmx_gmxx_rxx_stats_octs_s cn56xxp1;
3430 struct cvmx_gmxx_rxx_stats_octs_s cn58xx;
3431 struct cvmx_gmxx_rxx_stats_octs_s cn58xxp1;
3432 struct cvmx_gmxx_rxx_stats_octs_s cn61xx;
3433 struct cvmx_gmxx_rxx_stats_octs_s cn63xx;
3434 struct cvmx_gmxx_rxx_stats_octs_s cn63xxp1;
3435 struct cvmx_gmxx_rxx_stats_octs_s cn66xx;
3436 struct cvmx_gmxx_rxx_stats_octs_s cn68xx;
3437 struct cvmx_gmxx_rxx_stats_octs_s cn68xxp1;
3438 struct cvmx_gmxx_rxx_stats_octs_s cn70xx;
3439 struct cvmx_gmxx_rxx_stats_octs_s cn70xxp1;
3440 struct cvmx_gmxx_rxx_stats_octs_s cnf71xx;
3441};
3442
3443typedef union cvmx_gmxx_rxx_stats_octs cvmx_gmxx_rxx_stats_octs_t;
3444
3445/**
3446 * cvmx_gmx#_rx#_stats_octs_ctl
3447 *
3448 * Notes:
3449 * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
3450 * - Counters will wrap
3451 */
3452union cvmx_gmxx_rxx_stats_octs_ctl {
3453 u64 u64;
3454 struct cvmx_gmxx_rxx_stats_octs_ctl_s {
3455 u64 reserved_48_63 : 16;
3456 u64 cnt : 48;
3457 } s;
3458 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn30xx;
3459 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn31xx;
3460 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xx;
3461 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xxp2;
3462 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn50xx;
3463 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xx;
3464 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xxp1;
3465 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xx;
3466 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xxp1;
3467 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xx;
3468 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xxp1;
3469 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn61xx;
3470 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn63xx;
3471 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn63xxp1;
3472 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn66xx;
3473 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn68xx;
3474 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn68xxp1;
3475 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn70xx;
3476 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn70xxp1;
3477 struct cvmx_gmxx_rxx_stats_octs_ctl_s cnf71xx;
3478};
3479
3480typedef union cvmx_gmxx_rxx_stats_octs_ctl cvmx_gmxx_rxx_stats_octs_ctl_t;
3481
3482/**
3483 * cvmx_gmx#_rx#_stats_octs_dmac
3484 *
3485 * Notes:
3486 * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
3487 * - Counters will wrap
3488 */
3489union cvmx_gmxx_rxx_stats_octs_dmac {
3490 u64 u64;
3491 struct cvmx_gmxx_rxx_stats_octs_dmac_s {
3492 u64 reserved_48_63 : 16;
3493 u64 cnt : 48;
3494 } s;
3495 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn30xx;
3496 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn31xx;
3497 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xx;
3498 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xxp2;
3499 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn50xx;
3500 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xx;
3501 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xxp1;
3502 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xx;
3503 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xxp1;
3504 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xx;
3505 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xxp1;
3506 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn61xx;
3507 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn63xx;
3508 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn63xxp1;
3509 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn66xx;
3510 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn68xx;
3511 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn68xxp1;
3512 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn70xx;
3513 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn70xxp1;
3514 struct cvmx_gmxx_rxx_stats_octs_dmac_s cnf71xx;
3515};
3516
3517typedef union cvmx_gmxx_rxx_stats_octs_dmac cvmx_gmxx_rxx_stats_octs_dmac_t;
3518
3519/**
3520 * cvmx_gmx#_rx#_stats_octs_drp
3521 *
3522 * Notes:
3523 * - Cleared either by a write (of any value) or a read when GMX_RX_STATS_CTL[RD_CLR] is set
3524 * - Counters will wrap
3525 */
3526union cvmx_gmxx_rxx_stats_octs_drp {
3527 u64 u64;
3528 struct cvmx_gmxx_rxx_stats_octs_drp_s {
3529 u64 reserved_48_63 : 16;
3530 u64 cnt : 48;
3531 } s;
3532 struct cvmx_gmxx_rxx_stats_octs_drp_s cn30xx;
3533 struct cvmx_gmxx_rxx_stats_octs_drp_s cn31xx;
3534 struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xx;
3535 struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xxp2;
3536 struct cvmx_gmxx_rxx_stats_octs_drp_s cn50xx;
3537 struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xx;
3538 struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xxp1;
3539 struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xx;
3540 struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xxp1;
3541 struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xx;
3542 struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xxp1;
3543 struct cvmx_gmxx_rxx_stats_octs_drp_s cn61xx;
3544 struct cvmx_gmxx_rxx_stats_octs_drp_s cn63xx;
3545 struct cvmx_gmxx_rxx_stats_octs_drp_s cn63xxp1;
3546 struct cvmx_gmxx_rxx_stats_octs_drp_s cn66xx;
3547 struct cvmx_gmxx_rxx_stats_octs_drp_s cn68xx;
3548 struct cvmx_gmxx_rxx_stats_octs_drp_s cn68xxp1;
3549 struct cvmx_gmxx_rxx_stats_octs_drp_s cn70xx;
3550 struct cvmx_gmxx_rxx_stats_octs_drp_s cn70xxp1;
3551 struct cvmx_gmxx_rxx_stats_octs_drp_s cnf71xx;
3552};
3553
3554typedef union cvmx_gmxx_rxx_stats_octs_drp cvmx_gmxx_rxx_stats_octs_drp_t;
3555
3556/**
3557 * cvmx_gmx#_rx#_stats_pkts
3558 *
3559 * Count of good received packets - packets that are not recognized as PAUSE
3560 * packets, dropped due the DMAC filter, dropped due FIFO full status, or
3561 * have any other OPCODE (FCS, Length, etc).
3562 */
3563union cvmx_gmxx_rxx_stats_pkts {
3564 u64 u64;
3565 struct cvmx_gmxx_rxx_stats_pkts_s {
3566 u64 reserved_32_63 : 32;
3567 u64 cnt : 32;
3568 } s;
3569 struct cvmx_gmxx_rxx_stats_pkts_s cn30xx;
3570 struct cvmx_gmxx_rxx_stats_pkts_s cn31xx;
3571 struct cvmx_gmxx_rxx_stats_pkts_s cn38xx;
3572 struct cvmx_gmxx_rxx_stats_pkts_s cn38xxp2;
3573 struct cvmx_gmxx_rxx_stats_pkts_s cn50xx;
3574 struct cvmx_gmxx_rxx_stats_pkts_s cn52xx;
3575 struct cvmx_gmxx_rxx_stats_pkts_s cn52xxp1;
3576 struct cvmx_gmxx_rxx_stats_pkts_s cn56xx;
3577 struct cvmx_gmxx_rxx_stats_pkts_s cn56xxp1;
3578 struct cvmx_gmxx_rxx_stats_pkts_s cn58xx;
3579 struct cvmx_gmxx_rxx_stats_pkts_s cn58xxp1;
3580 struct cvmx_gmxx_rxx_stats_pkts_s cn61xx;
3581 struct cvmx_gmxx_rxx_stats_pkts_s cn63xx;
3582 struct cvmx_gmxx_rxx_stats_pkts_s cn63xxp1;
3583 struct cvmx_gmxx_rxx_stats_pkts_s cn66xx;
3584 struct cvmx_gmxx_rxx_stats_pkts_s cn68xx;
3585 struct cvmx_gmxx_rxx_stats_pkts_s cn68xxp1;
3586 struct cvmx_gmxx_rxx_stats_pkts_s cn70xx;
3587 struct cvmx_gmxx_rxx_stats_pkts_s cn70xxp1;
3588 struct cvmx_gmxx_rxx_stats_pkts_s cnf71xx;
3589};
3590
3591typedef union cvmx_gmxx_rxx_stats_pkts cvmx_gmxx_rxx_stats_pkts_t;
3592
3593/**
3594 * cvmx_gmx#_rx#_stats_pkts_bad
3595 *
3596 * Count of all packets received with some error that were not dropped
3597 * either due to the dmac filter or lack of room in the receive FIFO.
3598 */
3599union cvmx_gmxx_rxx_stats_pkts_bad {
3600 u64 u64;
3601 struct cvmx_gmxx_rxx_stats_pkts_bad_s {
3602 u64 reserved_32_63 : 32;
3603 u64 cnt : 32;
3604 } s;
3605 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn30xx;
3606 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn31xx;
3607 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xx;
3608 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xxp2;
3609 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn50xx;
3610 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xx;
3611 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xxp1;
3612 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xx;
3613 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xxp1;
3614 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xx;
3615 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xxp1;
3616 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn61xx;
3617 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn63xx;
3618 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn63xxp1;
3619 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn66xx;
3620 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn68xx;
3621 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn68xxp1;
3622 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn70xx;
3623 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn70xxp1;
3624 struct cvmx_gmxx_rxx_stats_pkts_bad_s cnf71xx;
3625};
3626
3627typedef union cvmx_gmxx_rxx_stats_pkts_bad cvmx_gmxx_rxx_stats_pkts_bad_t;
3628
3629/**
3630 * cvmx_gmx#_rx#_stats_pkts_ctl
3631 *
3632 * Count of all packets received that were recognized as Flow Control or
3633 * PAUSE packets. PAUSE packets with any kind of error are counted in
3634 * GMX_RX_STATS_PKTS_BAD. Pause packets can be optionally dropped or
3635 * forwarded based on the GMX_RX_FRM_CTL[CTL_DRP] bit. This count
3636 * increments regardless of whether the packet is dropped. Pause packets
3637 * will never be counted in GMX_RX_STATS_PKTS. Packets dropped due the dmac
3638 * filter will be counted in GMX_RX_STATS_PKTS_DMAC and not here.
3639 */
3640union cvmx_gmxx_rxx_stats_pkts_ctl {
3641 u64 u64;
3642 struct cvmx_gmxx_rxx_stats_pkts_ctl_s {
3643 u64 reserved_32_63 : 32;
3644 u64 cnt : 32;
3645 } s;
3646 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn30xx;
3647 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn31xx;
3648 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xx;
3649 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xxp2;
3650 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn50xx;
3651 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xx;
3652 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xxp1;
3653 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xx;
3654 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xxp1;
3655 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xx;
3656 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xxp1;
3657 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn61xx;
3658 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn63xx;
3659 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn63xxp1;
3660 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn66xx;
3661 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn68xx;
3662 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn68xxp1;
3663 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn70xx;
3664 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn70xxp1;
3665 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cnf71xx;
3666};
3667
3668typedef union cvmx_gmxx_rxx_stats_pkts_ctl cvmx_gmxx_rxx_stats_pkts_ctl_t;
3669
3670/**
3671 * cvmx_gmx#_rx#_stats_pkts_dmac
3672 *
3673 * Count of all packets received that were dropped by the dmac filter.
3674 * Packets that match the DMAC will be dropped and counted here regardless
3675 * of if they were bad packets. These packets will never be counted in
3676 * GMX_RX_STATS_PKTS.
3677 * Some packets that were not able to satisify the DECISION_CNT may not
3678 * actually be dropped by Octeon, but they will be counted here as if they
3679 * were dropped.
3680 */
3681union cvmx_gmxx_rxx_stats_pkts_dmac {
3682 u64 u64;
3683 struct cvmx_gmxx_rxx_stats_pkts_dmac_s {
3684 u64 reserved_32_63 : 32;
3685 u64 cnt : 32;
3686 } s;
3687 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn30xx;
3688 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn31xx;
3689 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xx;
3690 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xxp2;
3691 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn50xx;
3692 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xx;
3693 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xxp1;
3694 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xx;
3695 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xxp1;
3696 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xx;
3697 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xxp1;
3698 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn61xx;
3699 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn63xx;
3700 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn63xxp1;
3701 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn66xx;
3702 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn68xx;
3703 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn68xxp1;
3704 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn70xx;
3705 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn70xxp1;
3706 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cnf71xx;
3707};
3708
3709typedef union cvmx_gmxx_rxx_stats_pkts_dmac cvmx_gmxx_rxx_stats_pkts_dmac_t;
3710
3711/**
3712 * cvmx_gmx#_rx#_stats_pkts_drp
3713 *
3714 * Count of all packets received that were dropped due to a full receive FIFO.
3715 * This counts both partial packets in which there was enough space in the RX
3716 * FIFO to begin to buffer and the packet and total drops in which no packet was
3717 * sent to PKI. This counts good and bad packets received - all packets dropped
3718 * by the FIFO. It does not count packets dropped by the dmac or pause packet
3719 * filters.
3720 */
3721union cvmx_gmxx_rxx_stats_pkts_drp {
3722 u64 u64;
3723 struct cvmx_gmxx_rxx_stats_pkts_drp_s {
3724 u64 reserved_32_63 : 32;
3725 u64 cnt : 32;
3726 } s;
3727 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn30xx;
3728 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn31xx;
3729 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xx;
3730 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xxp2;
3731 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn50xx;
3732 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xx;
3733 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xxp1;
3734 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xx;
3735 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xxp1;
3736 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xx;
3737 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xxp1;
3738 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn61xx;
3739 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn63xx;
3740 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn63xxp1;
3741 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn66xx;
3742 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn68xx;
3743 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn68xxp1;
3744 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn70xx;
3745 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn70xxp1;
3746 struct cvmx_gmxx_rxx_stats_pkts_drp_s cnf71xx;
3747};
3748
3749typedef union cvmx_gmxx_rxx_stats_pkts_drp cvmx_gmxx_rxx_stats_pkts_drp_t;
3750
3751/**
3752 * cvmx_gmx#_rx#_udd_skp
3753 *
3754 * GMX_RX_UDD_SKP = Amount of User-defined data before the start of the L2 data
3755 *
3756 *
3757 * Notes:
3758 * (1) The skip bytes are part of the packet and will be sent down the NCB
3759 * packet interface and will be handled by PKI.
3760 *
3761 * (2) The system can determine if the UDD bytes are included in the FCS check
3762 * by using the FCSSEL field - if the FCS check is enabled.
3763 *
3764 * (3) Assume that the preamble/sfd is always at the start of the frame - even
3765 * before UDD bytes. In most cases, there will be no preamble in these
3766 * cases since it will be packet interface in direct communication to
3767 * another packet interface (MAC to MAC) without a PHY involved.
3768 *
3769 * (4) We can still do address filtering and control packet filtering is the
3770 * user desires.
3771 *
3772 * (5) UDD_SKP must be 0 in half-duplex operation unless
3773 * GMX_RX_FRM_CTL[PRE_CHK] is clear. If GMX_RX_FRM_CTL[PRE_CHK] is clear,
3774 * then UDD_SKP will normally be 8.
3775 *
3776 * (6) In all cases, the UDD bytes will be sent down the packet interface as
3777 * part of the packet. The UDD bytes are never stripped from the actual
3778 * packet.
3779 *
3780 * (7) If LEN != 0, then GMX_RX_FRM_CHK[LENERR] will be disabled and GMX_RX_INT_REG[LENERR] will be zero
3781 */
3782union cvmx_gmxx_rxx_udd_skp {
3783 u64 u64;
3784 struct cvmx_gmxx_rxx_udd_skp_s {
3785 u64 reserved_9_63 : 55;
3786 u64 fcssel : 1;
3787 u64 reserved_7_7 : 1;
3788 u64 len : 7;
3789 } s;
3790 struct cvmx_gmxx_rxx_udd_skp_s cn30xx;
3791 struct cvmx_gmxx_rxx_udd_skp_s cn31xx;
3792 struct cvmx_gmxx_rxx_udd_skp_s cn38xx;
3793 struct cvmx_gmxx_rxx_udd_skp_s cn38xxp2;
3794 struct cvmx_gmxx_rxx_udd_skp_s cn50xx;
3795 struct cvmx_gmxx_rxx_udd_skp_s cn52xx;
3796 struct cvmx_gmxx_rxx_udd_skp_s cn52xxp1;
3797 struct cvmx_gmxx_rxx_udd_skp_s cn56xx;
3798 struct cvmx_gmxx_rxx_udd_skp_s cn56xxp1;
3799 struct cvmx_gmxx_rxx_udd_skp_s cn58xx;
3800 struct cvmx_gmxx_rxx_udd_skp_s cn58xxp1;
3801 struct cvmx_gmxx_rxx_udd_skp_s cn61xx;
3802 struct cvmx_gmxx_rxx_udd_skp_s cn63xx;
3803 struct cvmx_gmxx_rxx_udd_skp_s cn63xxp1;
3804 struct cvmx_gmxx_rxx_udd_skp_s cn66xx;
3805 struct cvmx_gmxx_rxx_udd_skp_s cn68xx;
3806 struct cvmx_gmxx_rxx_udd_skp_s cn68xxp1;
3807 struct cvmx_gmxx_rxx_udd_skp_s cn70xx;
3808 struct cvmx_gmxx_rxx_udd_skp_s cn70xxp1;
3809 struct cvmx_gmxx_rxx_udd_skp_s cnf71xx;
3810};
3811
3812typedef union cvmx_gmxx_rxx_udd_skp cvmx_gmxx_rxx_udd_skp_t;
3813
3814/**
3815 * cvmx_gmx#_rx_bp_drop#
3816 *
3817 * GMX_RX_BP_DROP = FIFO mark for packet drop
3818 *
3819 *
3820 * Notes:
3821 * The actual watermark is dynamic with respect to the GMX_RX_PRTS
3822 * register. The GMX_RX_PRTS controls the depth of the port's
3823 * FIFO so as ports are added or removed, the drop point may change.
3824 *
3825 * In XAUI mode prt0 is used for checking.
3826 */
3827union cvmx_gmxx_rx_bp_dropx {
3828 u64 u64;
3829 struct cvmx_gmxx_rx_bp_dropx_s {
3830 u64 reserved_6_63 : 58;
3831 u64 mark : 6;
3832 } s;
3833 struct cvmx_gmxx_rx_bp_dropx_s cn30xx;
3834 struct cvmx_gmxx_rx_bp_dropx_s cn31xx;
3835 struct cvmx_gmxx_rx_bp_dropx_s cn38xx;
3836 struct cvmx_gmxx_rx_bp_dropx_s cn38xxp2;
3837 struct cvmx_gmxx_rx_bp_dropx_s cn50xx;
3838 struct cvmx_gmxx_rx_bp_dropx_s cn52xx;
3839 struct cvmx_gmxx_rx_bp_dropx_s cn52xxp1;
3840 struct cvmx_gmxx_rx_bp_dropx_s cn56xx;
3841 struct cvmx_gmxx_rx_bp_dropx_s cn56xxp1;
3842 struct cvmx_gmxx_rx_bp_dropx_s cn58xx;
3843 struct cvmx_gmxx_rx_bp_dropx_s cn58xxp1;
3844 struct cvmx_gmxx_rx_bp_dropx_s cn61xx;
3845 struct cvmx_gmxx_rx_bp_dropx_s cn63xx;
3846 struct cvmx_gmxx_rx_bp_dropx_s cn63xxp1;
3847 struct cvmx_gmxx_rx_bp_dropx_s cn66xx;
3848 struct cvmx_gmxx_rx_bp_dropx_s cn68xx;
3849 struct cvmx_gmxx_rx_bp_dropx_s cn68xxp1;
3850 struct cvmx_gmxx_rx_bp_dropx_s cn70xx;
3851 struct cvmx_gmxx_rx_bp_dropx_s cn70xxp1;
3852 struct cvmx_gmxx_rx_bp_dropx_s cnf71xx;
3853};
3854
3855typedef union cvmx_gmxx_rx_bp_dropx cvmx_gmxx_rx_bp_dropx_t;
3856
3857/**
3858 * cvmx_gmx#_rx_bp_off#
3859 *
3860 * GMX_RX_BP_OFF = Lowater mark for packet drop
3861 *
3862 *
3863 * Notes:
3864 * In XAUI mode, prt0 is used for checking.
3865 *
3866 */
3867union cvmx_gmxx_rx_bp_offx {
3868 u64 u64;
3869 struct cvmx_gmxx_rx_bp_offx_s {
3870 u64 reserved_6_63 : 58;
3871 u64 mark : 6;
3872 } s;
3873 struct cvmx_gmxx_rx_bp_offx_s cn30xx;
3874 struct cvmx_gmxx_rx_bp_offx_s cn31xx;
3875 struct cvmx_gmxx_rx_bp_offx_s cn38xx;
3876 struct cvmx_gmxx_rx_bp_offx_s cn38xxp2;
3877 struct cvmx_gmxx_rx_bp_offx_s cn50xx;
3878 struct cvmx_gmxx_rx_bp_offx_s cn52xx;
3879 struct cvmx_gmxx_rx_bp_offx_s cn52xxp1;
3880 struct cvmx_gmxx_rx_bp_offx_s cn56xx;
3881 struct cvmx_gmxx_rx_bp_offx_s cn56xxp1;
3882 struct cvmx_gmxx_rx_bp_offx_s cn58xx;
3883 struct cvmx_gmxx_rx_bp_offx_s cn58xxp1;
3884 struct cvmx_gmxx_rx_bp_offx_s cn61xx;
3885 struct cvmx_gmxx_rx_bp_offx_s cn63xx;
3886 struct cvmx_gmxx_rx_bp_offx_s cn63xxp1;
3887 struct cvmx_gmxx_rx_bp_offx_s cn66xx;
3888 struct cvmx_gmxx_rx_bp_offx_s cn68xx;
3889 struct cvmx_gmxx_rx_bp_offx_s cn68xxp1;
3890 struct cvmx_gmxx_rx_bp_offx_s cn70xx;
3891 struct cvmx_gmxx_rx_bp_offx_s cn70xxp1;
3892 struct cvmx_gmxx_rx_bp_offx_s cnf71xx;
3893};
3894
3895typedef union cvmx_gmxx_rx_bp_offx cvmx_gmxx_rx_bp_offx_t;
3896
3897/**
3898 * cvmx_gmx#_rx_bp_on#
3899 *
3900 * GMX_RX_BP_ON = Hiwater mark for port/interface backpressure
3901 *
3902 *
3903 * Notes:
3904 * In XAUI mode, prt0 is used for checking.
3905 *
3906 */
3907union cvmx_gmxx_rx_bp_onx {
3908 u64 u64;
3909 struct cvmx_gmxx_rx_bp_onx_s {
3910 u64 reserved_11_63 : 53;
3911 u64 mark : 11;
3912 } s;
3913 struct cvmx_gmxx_rx_bp_onx_cn30xx {
3914 u64 reserved_9_63 : 55;
3915 u64 mark : 9;
3916 } cn30xx;
3917 struct cvmx_gmxx_rx_bp_onx_cn30xx cn31xx;
3918 struct cvmx_gmxx_rx_bp_onx_cn30xx cn38xx;
3919 struct cvmx_gmxx_rx_bp_onx_cn30xx cn38xxp2;
3920 struct cvmx_gmxx_rx_bp_onx_cn30xx cn50xx;
3921 struct cvmx_gmxx_rx_bp_onx_cn30xx cn52xx;
3922 struct cvmx_gmxx_rx_bp_onx_cn30xx cn52xxp1;
3923 struct cvmx_gmxx_rx_bp_onx_cn30xx cn56xx;
3924 struct cvmx_gmxx_rx_bp_onx_cn30xx cn56xxp1;
3925 struct cvmx_gmxx_rx_bp_onx_cn30xx cn58xx;
3926 struct cvmx_gmxx_rx_bp_onx_cn30xx cn58xxp1;
3927 struct cvmx_gmxx_rx_bp_onx_cn30xx cn61xx;
3928 struct cvmx_gmxx_rx_bp_onx_cn30xx cn63xx;
3929 struct cvmx_gmxx_rx_bp_onx_cn30xx cn63xxp1;
3930 struct cvmx_gmxx_rx_bp_onx_cn30xx cn66xx;
3931 struct cvmx_gmxx_rx_bp_onx_s cn68xx;
3932 struct cvmx_gmxx_rx_bp_onx_s cn68xxp1;
3933 struct cvmx_gmxx_rx_bp_onx_cn30xx cn70xx;
3934 struct cvmx_gmxx_rx_bp_onx_cn30xx cn70xxp1;
3935 struct cvmx_gmxx_rx_bp_onx_cn30xx cnf71xx;
3936};
3937
3938typedef union cvmx_gmxx_rx_bp_onx cvmx_gmxx_rx_bp_onx_t;
3939
3940/**
3941 * cvmx_gmx#_rx_hg2_status
3942 *
3943 * ** HG2 message CSRs
3944 *
3945 */
3946union cvmx_gmxx_rx_hg2_status {
3947 u64 u64;
3948 struct cvmx_gmxx_rx_hg2_status_s {
3949 u64 reserved_48_63 : 16;
3950 u64 phtim2go : 16;
3951 u64 xof : 16;
3952 u64 lgtim2go : 16;
3953 } s;
3954 struct cvmx_gmxx_rx_hg2_status_s cn52xx;
3955 struct cvmx_gmxx_rx_hg2_status_s cn52xxp1;
3956 struct cvmx_gmxx_rx_hg2_status_s cn56xx;
3957 struct cvmx_gmxx_rx_hg2_status_s cn61xx;
3958 struct cvmx_gmxx_rx_hg2_status_s cn63xx;
3959 struct cvmx_gmxx_rx_hg2_status_s cn63xxp1;
3960 struct cvmx_gmxx_rx_hg2_status_s cn66xx;
3961 struct cvmx_gmxx_rx_hg2_status_s cn68xx;
3962 struct cvmx_gmxx_rx_hg2_status_s cn68xxp1;
3963 struct cvmx_gmxx_rx_hg2_status_s cn70xx;
3964 struct cvmx_gmxx_rx_hg2_status_s cn70xxp1;
3965 struct cvmx_gmxx_rx_hg2_status_s cnf71xx;
3966};
3967
3968typedef union cvmx_gmxx_rx_hg2_status cvmx_gmxx_rx_hg2_status_t;
3969
3970/**
3971 * cvmx_gmx#_rx_pass_en
3972 *
3973 * GMX_RX_PASS_EN = Packet pass through mode enable
3974 *
3975 * When both Octane ports are running in Spi4 mode, packets can be directly
3976 * passed from one SPX interface to the other without being processed by the
3977 * core or PP's. The register has one bit for each port to enable the pass
3978 * through feature.
3979 *
3980 * Notes:
3981 * (1) Can only be used in dual Spi4 configs
3982 *
3983 * (2) The mapped pass through output port cannot be the destination port for
3984 * any Octane core traffic.
3985 */
3986union cvmx_gmxx_rx_pass_en {
3987 u64 u64;
3988 struct cvmx_gmxx_rx_pass_en_s {
3989 u64 reserved_16_63 : 48;
3990 u64 en : 16;
3991 } s;
3992 struct cvmx_gmxx_rx_pass_en_s cn38xx;
3993 struct cvmx_gmxx_rx_pass_en_s cn38xxp2;
3994 struct cvmx_gmxx_rx_pass_en_s cn58xx;
3995 struct cvmx_gmxx_rx_pass_en_s cn58xxp1;
3996};
3997
3998typedef union cvmx_gmxx_rx_pass_en cvmx_gmxx_rx_pass_en_t;
3999
4000/**
4001 * cvmx_gmx#_rx_pass_map#
4002 *
4003 * GMX_RX_PASS_MAP = Packet pass through port map
4004 *
4005 */
4006union cvmx_gmxx_rx_pass_mapx {
4007 u64 u64;
4008 struct cvmx_gmxx_rx_pass_mapx_s {
4009 u64 reserved_4_63 : 60;
4010 u64 dprt : 4;
4011 } s;
4012 struct cvmx_gmxx_rx_pass_mapx_s cn38xx;
4013 struct cvmx_gmxx_rx_pass_mapx_s cn38xxp2;
4014 struct cvmx_gmxx_rx_pass_mapx_s cn58xx;
4015 struct cvmx_gmxx_rx_pass_mapx_s cn58xxp1;
4016};
4017
4018typedef union cvmx_gmxx_rx_pass_mapx cvmx_gmxx_rx_pass_mapx_t;
4019
4020/**
4021 * cvmx_gmx#_rx_prt_info
4022 *
4023 * GMX_RX_PRT_INFO = Report the RX status for port
4024 *
4025 *
4026 * Notes:
4027 * In XAUI mode, only the lsb (corresponding to port0) of DROP and COMMIT are used.
4028 *
4029 */
4030union cvmx_gmxx_rx_prt_info {
4031 u64 u64;
4032 struct cvmx_gmxx_rx_prt_info_s {
4033 u64 reserved_32_63 : 32;
4034 u64 drop : 16;
4035 u64 commit : 16;
4036 } s;
4037 struct cvmx_gmxx_rx_prt_info_cn30xx {
4038 u64 reserved_19_63 : 45;
4039 u64 drop : 3;
4040 u64 reserved_3_15 : 13;
4041 u64 commit : 3;
4042 } cn30xx;
4043 struct cvmx_gmxx_rx_prt_info_cn30xx cn31xx;
4044 struct cvmx_gmxx_rx_prt_info_s cn38xx;
4045 struct cvmx_gmxx_rx_prt_info_cn30xx cn50xx;
4046 struct cvmx_gmxx_rx_prt_info_cn52xx {
4047 u64 reserved_20_63 : 44;
4048 u64 drop : 4;
4049 u64 reserved_4_15 : 12;
4050 u64 commit : 4;
4051 } cn52xx;
4052 struct cvmx_gmxx_rx_prt_info_cn52xx cn52xxp1;
4053 struct cvmx_gmxx_rx_prt_info_cn52xx cn56xx;
4054 struct cvmx_gmxx_rx_prt_info_cn52xx cn56xxp1;
4055 struct cvmx_gmxx_rx_prt_info_s cn58xx;
4056 struct cvmx_gmxx_rx_prt_info_s cn58xxp1;
4057 struct cvmx_gmxx_rx_prt_info_cn52xx cn61xx;
4058 struct cvmx_gmxx_rx_prt_info_cn52xx cn63xx;
4059 struct cvmx_gmxx_rx_prt_info_cn52xx cn63xxp1;
4060 struct cvmx_gmxx_rx_prt_info_cn52xx cn66xx;
4061 struct cvmx_gmxx_rx_prt_info_cn52xx cn68xx;
4062 struct cvmx_gmxx_rx_prt_info_cn52xx cn68xxp1;
4063 struct cvmx_gmxx_rx_prt_info_cn52xx cn70xx;
4064 struct cvmx_gmxx_rx_prt_info_cn52xx cn70xxp1;
4065 struct cvmx_gmxx_rx_prt_info_cnf71xx {
4066 u64 reserved_18_63 : 46;
4067 u64 drop : 2;
4068 u64 reserved_2_15 : 14;
4069 u64 commit : 2;
4070 } cnf71xx;
4071};
4072
4073typedef union cvmx_gmxx_rx_prt_info cvmx_gmxx_rx_prt_info_t;
4074
4075/**
4076 * cvmx_gmx#_rx_prts
4077 *
4078 * GMX_RX_PRTS = Number of FIFOs to carve the RX buffer into
4079 *
4080 *
4081 * Notes:
4082 * GMX_RX_PRTS[PRTS] must be set to '1' in XAUI mode.
4083 *
4084 */
4085union cvmx_gmxx_rx_prts {
4086 u64 u64;
4087 struct cvmx_gmxx_rx_prts_s {
4088 u64 reserved_3_63 : 61;
4089 u64 prts : 3;
4090 } s;
4091 struct cvmx_gmxx_rx_prts_s cn30xx;
4092 struct cvmx_gmxx_rx_prts_s cn31xx;
4093 struct cvmx_gmxx_rx_prts_s cn38xx;
4094 struct cvmx_gmxx_rx_prts_s cn38xxp2;
4095 struct cvmx_gmxx_rx_prts_s cn50xx;
4096 struct cvmx_gmxx_rx_prts_s cn52xx;
4097 struct cvmx_gmxx_rx_prts_s cn52xxp1;
4098 struct cvmx_gmxx_rx_prts_s cn56xx;
4099 struct cvmx_gmxx_rx_prts_s cn56xxp1;
4100 struct cvmx_gmxx_rx_prts_s cn58xx;
4101 struct cvmx_gmxx_rx_prts_s cn58xxp1;
4102 struct cvmx_gmxx_rx_prts_s cn61xx;
4103 struct cvmx_gmxx_rx_prts_s cn63xx;
4104 struct cvmx_gmxx_rx_prts_s cn63xxp1;
4105 struct cvmx_gmxx_rx_prts_s cn66xx;
4106 struct cvmx_gmxx_rx_prts_s cn68xx;
4107 struct cvmx_gmxx_rx_prts_s cn68xxp1;
4108 struct cvmx_gmxx_rx_prts_s cn70xx;
4109 struct cvmx_gmxx_rx_prts_s cn70xxp1;
4110 struct cvmx_gmxx_rx_prts_s cnf71xx;
4111};
4112
4113typedef union cvmx_gmxx_rx_prts cvmx_gmxx_rx_prts_t;
4114
4115/**
4116 * cvmx_gmx#_rx_tx_status
4117 *
4118 * GMX_RX_TX_STATUS = GMX RX/TX Status
4119 *
4120 */
4121union cvmx_gmxx_rx_tx_status {
4122 u64 u64;
4123 struct cvmx_gmxx_rx_tx_status_s {
4124 u64 reserved_7_63 : 57;
4125 u64 tx : 3;
4126 u64 reserved_3_3 : 1;
4127 u64 rx : 3;
4128 } s;
4129 struct cvmx_gmxx_rx_tx_status_s cn30xx;
4130 struct cvmx_gmxx_rx_tx_status_s cn31xx;
4131 struct cvmx_gmxx_rx_tx_status_s cn50xx;
4132};
4133
4134typedef union cvmx_gmxx_rx_tx_status cvmx_gmxx_rx_tx_status_t;
4135
4136/**
4137 * cvmx_gmx#_rx_xaui_bad_col
4138 */
4139union cvmx_gmxx_rx_xaui_bad_col {
4140 u64 u64;
4141 struct cvmx_gmxx_rx_xaui_bad_col_s {
4142 u64 reserved_40_63 : 24;
4143 u64 val : 1;
4144 u64 state : 3;
4145 u64 lane_rxc : 4;
4146 u64 lane_rxd : 32;
4147 } s;
4148 struct cvmx_gmxx_rx_xaui_bad_col_s cn52xx;
4149 struct cvmx_gmxx_rx_xaui_bad_col_s cn52xxp1;
4150 struct cvmx_gmxx_rx_xaui_bad_col_s cn56xx;
4151 struct cvmx_gmxx_rx_xaui_bad_col_s cn56xxp1;
4152 struct cvmx_gmxx_rx_xaui_bad_col_s cn61xx;
4153 struct cvmx_gmxx_rx_xaui_bad_col_s cn63xx;
4154 struct cvmx_gmxx_rx_xaui_bad_col_s cn63xxp1;
4155 struct cvmx_gmxx_rx_xaui_bad_col_s cn66xx;
4156 struct cvmx_gmxx_rx_xaui_bad_col_s cn68xx;
4157 struct cvmx_gmxx_rx_xaui_bad_col_s cn68xxp1;
4158 struct cvmx_gmxx_rx_xaui_bad_col_s cn70xx;
4159 struct cvmx_gmxx_rx_xaui_bad_col_s cn70xxp1;
4160 struct cvmx_gmxx_rx_xaui_bad_col_s cnf71xx;
4161};
4162
4163typedef union cvmx_gmxx_rx_xaui_bad_col cvmx_gmxx_rx_xaui_bad_col_t;
4164
4165/**
4166 * cvmx_gmx#_rx_xaui_ctl
4167 */
4168union cvmx_gmxx_rx_xaui_ctl {
4169 u64 u64;
4170 struct cvmx_gmxx_rx_xaui_ctl_s {
4171 u64 reserved_2_63 : 62;
4172 u64 status : 2;
4173 } s;
4174 struct cvmx_gmxx_rx_xaui_ctl_s cn52xx;
4175 struct cvmx_gmxx_rx_xaui_ctl_s cn52xxp1;
4176 struct cvmx_gmxx_rx_xaui_ctl_s cn56xx;
4177 struct cvmx_gmxx_rx_xaui_ctl_s cn56xxp1;
4178 struct cvmx_gmxx_rx_xaui_ctl_s cn61xx;
4179 struct cvmx_gmxx_rx_xaui_ctl_s cn63xx;
4180 struct cvmx_gmxx_rx_xaui_ctl_s cn63xxp1;
4181 struct cvmx_gmxx_rx_xaui_ctl_s cn66xx;
4182 struct cvmx_gmxx_rx_xaui_ctl_s cn68xx;
4183 struct cvmx_gmxx_rx_xaui_ctl_s cn68xxp1;
4184 struct cvmx_gmxx_rx_xaui_ctl_s cn70xx;
4185 struct cvmx_gmxx_rx_xaui_ctl_s cn70xxp1;
4186 struct cvmx_gmxx_rx_xaui_ctl_s cnf71xx;
4187};
4188
4189typedef union cvmx_gmxx_rx_xaui_ctl cvmx_gmxx_rx_xaui_ctl_t;
4190
4191/**
4192 * cvmx_gmx#_rxaui_ctl
4193 */
4194union cvmx_gmxx_rxaui_ctl {
4195 u64 u64;
4196 struct cvmx_gmxx_rxaui_ctl_s {
4197 u64 reserved_1_63 : 63;
4198 u64 disparity : 1;
4199 } s;
4200 struct cvmx_gmxx_rxaui_ctl_s cn68xx;
4201 struct cvmx_gmxx_rxaui_ctl_s cn68xxp1;
4202 struct cvmx_gmxx_rxaui_ctl_s cn70xx;
4203 struct cvmx_gmxx_rxaui_ctl_s cn70xxp1;
4204};
4205
4206typedef union cvmx_gmxx_rxaui_ctl cvmx_gmxx_rxaui_ctl_t;
4207
4208/**
4209 * cvmx_gmx#_smac#
4210 *
4211 * GMX_SMAC = Packet SMAC
4212 *
4213 */
4214union cvmx_gmxx_smacx {
4215 u64 u64;
4216 struct cvmx_gmxx_smacx_s {
4217 u64 reserved_48_63 : 16;
4218 u64 smac : 48;
4219 } s;
4220 struct cvmx_gmxx_smacx_s cn30xx;
4221 struct cvmx_gmxx_smacx_s cn31xx;
4222 struct cvmx_gmxx_smacx_s cn38xx;
4223 struct cvmx_gmxx_smacx_s cn38xxp2;
4224 struct cvmx_gmxx_smacx_s cn50xx;
4225 struct cvmx_gmxx_smacx_s cn52xx;
4226 struct cvmx_gmxx_smacx_s cn52xxp1;
4227 struct cvmx_gmxx_smacx_s cn56xx;
4228 struct cvmx_gmxx_smacx_s cn56xxp1;
4229 struct cvmx_gmxx_smacx_s cn58xx;
4230 struct cvmx_gmxx_smacx_s cn58xxp1;
4231 struct cvmx_gmxx_smacx_s cn61xx;
4232 struct cvmx_gmxx_smacx_s cn63xx;
4233 struct cvmx_gmxx_smacx_s cn63xxp1;
4234 struct cvmx_gmxx_smacx_s cn66xx;
4235 struct cvmx_gmxx_smacx_s cn68xx;
4236 struct cvmx_gmxx_smacx_s cn68xxp1;
4237 struct cvmx_gmxx_smacx_s cn70xx;
4238 struct cvmx_gmxx_smacx_s cn70xxp1;
4239 struct cvmx_gmxx_smacx_s cnf71xx;
4240};
4241
4242typedef union cvmx_gmxx_smacx cvmx_gmxx_smacx_t;
4243
4244/**
4245 * cvmx_gmx#_soft_bist
4246 *
4247 * GMX_SOFT_BIST = Software BIST Control
4248 *
4249 */
4250union cvmx_gmxx_soft_bist {
4251 u64 u64;
4252 struct cvmx_gmxx_soft_bist_s {
4253 u64 reserved_2_63 : 62;
4254 u64 start_bist : 1;
4255 u64 clear_bist : 1;
4256 } s;
4257 struct cvmx_gmxx_soft_bist_s cn63xx;
4258 struct cvmx_gmxx_soft_bist_s cn63xxp1;
4259 struct cvmx_gmxx_soft_bist_s cn66xx;
4260 struct cvmx_gmxx_soft_bist_s cn68xx;
4261 struct cvmx_gmxx_soft_bist_s cn68xxp1;
4262};
4263
4264typedef union cvmx_gmxx_soft_bist cvmx_gmxx_soft_bist_t;
4265
4266/**
4267 * cvmx_gmx#_stat_bp
4268 *
4269 * GMX_STAT_BP = Number of cycles that the TX/Stats block has help up operation
4270 *
4271 *
4272 * Notes:
4273 * It has no relationship with the TX FIFO per se. The TX engine sends packets
4274 * from PKO and upon completion, sends a command to the TX stats block for an
4275 * update based on the packet size. The stats operation can take a few cycles -
4276 * normally not enough to be visible considering the 64B min packet size that is
4277 * ethernet convention.
4278 *
4279 * In the rare case in which SW attempted to schedule really, really, small packets
4280 * or the sclk (6xxx) is running ass-slow, then the stats updates may not happen in
4281 * real time and can back up the TX engine.
4282 *
4283 * This counter is the number of cycles in which the TX engine was stalled. In
4284 * normal operation, it should always be zeros.
4285 */
4286union cvmx_gmxx_stat_bp {
4287 u64 u64;
4288 struct cvmx_gmxx_stat_bp_s {
4289 u64 reserved_17_63 : 47;
4290 u64 bp : 1;
4291 u64 cnt : 16;
4292 } s;
4293 struct cvmx_gmxx_stat_bp_s cn30xx;
4294 struct cvmx_gmxx_stat_bp_s cn31xx;
4295 struct cvmx_gmxx_stat_bp_s cn38xx;
4296 struct cvmx_gmxx_stat_bp_s cn38xxp2;
4297 struct cvmx_gmxx_stat_bp_s cn50xx;
4298 struct cvmx_gmxx_stat_bp_s cn52xx;
4299 struct cvmx_gmxx_stat_bp_s cn52xxp1;
4300 struct cvmx_gmxx_stat_bp_s cn56xx;
4301 struct cvmx_gmxx_stat_bp_s cn56xxp1;
4302 struct cvmx_gmxx_stat_bp_s cn58xx;
4303 struct cvmx_gmxx_stat_bp_s cn58xxp1;
4304 struct cvmx_gmxx_stat_bp_s cn61xx;
4305 struct cvmx_gmxx_stat_bp_s cn63xx;
4306 struct cvmx_gmxx_stat_bp_s cn63xxp1;
4307 struct cvmx_gmxx_stat_bp_s cn66xx;
4308 struct cvmx_gmxx_stat_bp_s cn68xx;
4309 struct cvmx_gmxx_stat_bp_s cn68xxp1;
4310 struct cvmx_gmxx_stat_bp_s cn70xx;
4311 struct cvmx_gmxx_stat_bp_s cn70xxp1;
4312 struct cvmx_gmxx_stat_bp_s cnf71xx;
4313};
4314
4315typedef union cvmx_gmxx_stat_bp cvmx_gmxx_stat_bp_t;
4316
4317/**
4318 * cvmx_gmx#_tb_reg
4319 *
4320 * DON'T PUT IN HRM*
4321 *
4322 */
4323union cvmx_gmxx_tb_reg {
4324 u64 u64;
4325 struct cvmx_gmxx_tb_reg_s {
4326 u64 reserved_1_63 : 63;
4327 u64 wr_magic : 1;
4328 } s;
4329 struct cvmx_gmxx_tb_reg_s cn61xx;
4330 struct cvmx_gmxx_tb_reg_s cn66xx;
4331 struct cvmx_gmxx_tb_reg_s cn68xx;
4332 struct cvmx_gmxx_tb_reg_s cn70xx;
4333 struct cvmx_gmxx_tb_reg_s cn70xxp1;
4334 struct cvmx_gmxx_tb_reg_s cnf71xx;
4335};
4336
4337typedef union cvmx_gmxx_tb_reg cvmx_gmxx_tb_reg_t;
4338
4339/**
4340 * cvmx_gmx#_tx#_append
4341 *
4342 * GMX_TX_APPEND = Packet TX Append Control
4343 *
4344 */
4345union cvmx_gmxx_txx_append {
4346 u64 u64;
4347 struct cvmx_gmxx_txx_append_s {
4348 u64 reserved_4_63 : 60;
4349 u64 force_fcs : 1;
4350 u64 fcs : 1;
4351 u64 pad : 1;
4352 u64 preamble : 1;
4353 } s;
4354 struct cvmx_gmxx_txx_append_s cn30xx;
4355 struct cvmx_gmxx_txx_append_s cn31xx;
4356 struct cvmx_gmxx_txx_append_s cn38xx;
4357 struct cvmx_gmxx_txx_append_s cn38xxp2;
4358 struct cvmx_gmxx_txx_append_s cn50xx;
4359 struct cvmx_gmxx_txx_append_s cn52xx;
4360 struct cvmx_gmxx_txx_append_s cn52xxp1;
4361 struct cvmx_gmxx_txx_append_s cn56xx;
4362 struct cvmx_gmxx_txx_append_s cn56xxp1;
4363 struct cvmx_gmxx_txx_append_s cn58xx;
4364 struct cvmx_gmxx_txx_append_s cn58xxp1;
4365 struct cvmx_gmxx_txx_append_s cn61xx;
4366 struct cvmx_gmxx_txx_append_s cn63xx;
4367 struct cvmx_gmxx_txx_append_s cn63xxp1;
4368 struct cvmx_gmxx_txx_append_s cn66xx;
4369 struct cvmx_gmxx_txx_append_s cn68xx;
4370 struct cvmx_gmxx_txx_append_s cn68xxp1;
4371 struct cvmx_gmxx_txx_append_s cn70xx;
4372 struct cvmx_gmxx_txx_append_s cn70xxp1;
4373 struct cvmx_gmxx_txx_append_s cnf71xx;
4374};
4375
4376typedef union cvmx_gmxx_txx_append cvmx_gmxx_txx_append_t;
4377
4378/**
4379 * cvmx_gmx#_tx#_bck_crdt
4380 *
4381 * gmi_tx_bck to gmi_tx_out credit count register
4382 *
4383 */
4384union cvmx_gmxx_txx_bck_crdt {
4385 u64 u64;
4386 struct cvmx_gmxx_txx_bck_crdt_s {
4387 u64 reserved_4_63 : 60;
4388 u64 cnt : 4;
4389 } s;
4390 struct cvmx_gmxx_txx_bck_crdt_s cn70xx;
4391 struct cvmx_gmxx_txx_bck_crdt_s cn70xxp1;
4392};
4393
4394typedef union cvmx_gmxx_txx_bck_crdt cvmx_gmxx_txx_bck_crdt_t;
4395
4396/**
4397 * cvmx_gmx#_tx#_burst
4398 *
4399 * GMX_TX_BURST = Packet TX Burst Counter
4400 *
4401 */
4402union cvmx_gmxx_txx_burst {
4403 u64 u64;
4404 struct cvmx_gmxx_txx_burst_s {
4405 u64 reserved_16_63 : 48;
4406 u64 burst : 16;
4407 } s;
4408 struct cvmx_gmxx_txx_burst_s cn30xx;
4409 struct cvmx_gmxx_txx_burst_s cn31xx;
4410 struct cvmx_gmxx_txx_burst_s cn38xx;
4411 struct cvmx_gmxx_txx_burst_s cn38xxp2;
4412 struct cvmx_gmxx_txx_burst_s cn50xx;
4413 struct cvmx_gmxx_txx_burst_s cn52xx;
4414 struct cvmx_gmxx_txx_burst_s cn52xxp1;
4415 struct cvmx_gmxx_txx_burst_s cn56xx;
4416 struct cvmx_gmxx_txx_burst_s cn56xxp1;
4417 struct cvmx_gmxx_txx_burst_s cn58xx;
4418 struct cvmx_gmxx_txx_burst_s cn58xxp1;
4419 struct cvmx_gmxx_txx_burst_s cn61xx;
4420 struct cvmx_gmxx_txx_burst_s cn63xx;
4421 struct cvmx_gmxx_txx_burst_s cn63xxp1;
4422 struct cvmx_gmxx_txx_burst_s cn66xx;
4423 struct cvmx_gmxx_txx_burst_s cn68xx;
4424 struct cvmx_gmxx_txx_burst_s cn68xxp1;
4425 struct cvmx_gmxx_txx_burst_s cn70xx;
4426 struct cvmx_gmxx_txx_burst_s cn70xxp1;
4427 struct cvmx_gmxx_txx_burst_s cnf71xx;
4428};
4429
4430typedef union cvmx_gmxx_txx_burst cvmx_gmxx_txx_burst_t;
4431
4432/**
4433 * cvmx_gmx#_tx#_cbfc_xoff
4434 */
4435union cvmx_gmxx_txx_cbfc_xoff {
4436 u64 u64;
4437 struct cvmx_gmxx_txx_cbfc_xoff_s {
4438 u64 reserved_16_63 : 48;
4439 u64 xoff : 16;
4440 } s;
4441 struct cvmx_gmxx_txx_cbfc_xoff_s cn52xx;
4442 struct cvmx_gmxx_txx_cbfc_xoff_s cn56xx;
4443 struct cvmx_gmxx_txx_cbfc_xoff_s cn61xx;
4444 struct cvmx_gmxx_txx_cbfc_xoff_s cn63xx;
4445 struct cvmx_gmxx_txx_cbfc_xoff_s cn63xxp1;
4446 struct cvmx_gmxx_txx_cbfc_xoff_s cn66xx;
4447 struct cvmx_gmxx_txx_cbfc_xoff_s cn68xx;
4448 struct cvmx_gmxx_txx_cbfc_xoff_s cn68xxp1;
4449 struct cvmx_gmxx_txx_cbfc_xoff_s cn70xx;
4450 struct cvmx_gmxx_txx_cbfc_xoff_s cn70xxp1;
4451 struct cvmx_gmxx_txx_cbfc_xoff_s cnf71xx;
4452};
4453
4454typedef union cvmx_gmxx_txx_cbfc_xoff cvmx_gmxx_txx_cbfc_xoff_t;
4455
4456/**
4457 * cvmx_gmx#_tx#_cbfc_xon
4458 */
4459union cvmx_gmxx_txx_cbfc_xon {
4460 u64 u64;
4461 struct cvmx_gmxx_txx_cbfc_xon_s {
4462 u64 reserved_16_63 : 48;
4463 u64 xon : 16;
4464 } s;
4465 struct cvmx_gmxx_txx_cbfc_xon_s cn52xx;
4466 struct cvmx_gmxx_txx_cbfc_xon_s cn56xx;
4467 struct cvmx_gmxx_txx_cbfc_xon_s cn61xx;
4468 struct cvmx_gmxx_txx_cbfc_xon_s cn63xx;
4469 struct cvmx_gmxx_txx_cbfc_xon_s cn63xxp1;
4470 struct cvmx_gmxx_txx_cbfc_xon_s cn66xx;
4471 struct cvmx_gmxx_txx_cbfc_xon_s cn68xx;
4472 struct cvmx_gmxx_txx_cbfc_xon_s cn68xxp1;
4473 struct cvmx_gmxx_txx_cbfc_xon_s cn70xx;
4474 struct cvmx_gmxx_txx_cbfc_xon_s cn70xxp1;
4475 struct cvmx_gmxx_txx_cbfc_xon_s cnf71xx;
4476};
4477
4478typedef union cvmx_gmxx_txx_cbfc_xon cvmx_gmxx_txx_cbfc_xon_t;
4479
4480/**
4481 * cvmx_gmx#_tx#_clk
4482 *
4483 * Per Port
4484 *
4485 *
4486 * GMX_TX_CLK = RGMII TX Clock Generation Register
4487 *
4488 * Notes:
4489 * Programming Restrictions:
4490 * (1) In RGMII mode, if GMX_PRT_CFG[SPEED]==0, then CLK_CNT must be > 1.
4491 * (2) In MII mode, CLK_CNT == 1
4492 * (3) In RGMII or GMII mode, if CLK_CNT==0, Octeon will not generate a tx clock.
4493 *
4494 * RGMII Example:
4495 * Given a 125MHz PLL reference clock...
4496 * CLK_CNT == 1 ==> 125.0MHz TXC clock period (8ns* 1)
4497 * CLK_CNT == 5 ==> 25.0MHz TXC clock period (8ns* 5)
4498 * CLK_CNT == 50 ==> 2.5MHz TXC clock period (8ns*50)
4499 */
4500union cvmx_gmxx_txx_clk {
4501 u64 u64;
4502 struct cvmx_gmxx_txx_clk_s {
4503 u64 reserved_6_63 : 58;
4504 u64 clk_cnt : 6;
4505 } s;
4506 struct cvmx_gmxx_txx_clk_s cn30xx;
4507 struct cvmx_gmxx_txx_clk_s cn31xx;
4508 struct cvmx_gmxx_txx_clk_s cn38xx;
4509 struct cvmx_gmxx_txx_clk_s cn38xxp2;
4510 struct cvmx_gmxx_txx_clk_s cn50xx;
4511 struct cvmx_gmxx_txx_clk_s cn58xx;
4512 struct cvmx_gmxx_txx_clk_s cn58xxp1;
4513};
4514
4515typedef union cvmx_gmxx_txx_clk cvmx_gmxx_txx_clk_t;
4516
4517/**
4518 * cvmx_gmx#_tx#_ctl
4519 *
4520 * GMX_TX_CTL = TX Control register
4521 *
4522 */
4523union cvmx_gmxx_txx_ctl {
4524 u64 u64;
4525 struct cvmx_gmxx_txx_ctl_s {
4526 u64 reserved_2_63 : 62;
4527 u64 xsdef_en : 1;
4528 u64 xscol_en : 1;
4529 } s;
4530 struct cvmx_gmxx_txx_ctl_s cn30xx;
4531 struct cvmx_gmxx_txx_ctl_s cn31xx;
4532 struct cvmx_gmxx_txx_ctl_s cn38xx;
4533 struct cvmx_gmxx_txx_ctl_s cn38xxp2;
4534 struct cvmx_gmxx_txx_ctl_s cn50xx;
4535 struct cvmx_gmxx_txx_ctl_s cn52xx;
4536 struct cvmx_gmxx_txx_ctl_s cn52xxp1;
4537 struct cvmx_gmxx_txx_ctl_s cn56xx;
4538 struct cvmx_gmxx_txx_ctl_s cn56xxp1;
4539 struct cvmx_gmxx_txx_ctl_s cn58xx;
4540 struct cvmx_gmxx_txx_ctl_s cn58xxp1;
4541 struct cvmx_gmxx_txx_ctl_s cn61xx;
4542 struct cvmx_gmxx_txx_ctl_s cn63xx;
4543 struct cvmx_gmxx_txx_ctl_s cn63xxp1;
4544 struct cvmx_gmxx_txx_ctl_s cn66xx;
4545 struct cvmx_gmxx_txx_ctl_s cn68xx;
4546 struct cvmx_gmxx_txx_ctl_s cn68xxp1;
4547 struct cvmx_gmxx_txx_ctl_s cn70xx;
4548 struct cvmx_gmxx_txx_ctl_s cn70xxp1;
4549 struct cvmx_gmxx_txx_ctl_s cnf71xx;
4550};
4551
4552typedef union cvmx_gmxx_txx_ctl cvmx_gmxx_txx_ctl_t;
4553
4554/**
4555 * cvmx_gmx#_tx#_jam_mode
4556 */
4557union cvmx_gmxx_txx_jam_mode {
4558 u64 u64;
4559 struct cvmx_gmxx_txx_jam_mode_s {
4560 u64 reserved_1_63 : 63;
4561 u64 mode : 1;
4562 } s;
4563 struct cvmx_gmxx_txx_jam_mode_s cn70xx;
4564 struct cvmx_gmxx_txx_jam_mode_s cn70xxp1;
4565};
4566
4567typedef union cvmx_gmxx_txx_jam_mode cvmx_gmxx_txx_jam_mode_t;
4568
4569/**
4570 * cvmx_gmx#_tx#_min_pkt
4571 *
4572 * GMX_TX_MIN_PKT = Packet TX Min Size Packet (PAD upto min size)
4573 *
4574 */
4575union cvmx_gmxx_txx_min_pkt {
4576 u64 u64;
4577 struct cvmx_gmxx_txx_min_pkt_s {
4578 u64 reserved_8_63 : 56;
4579 u64 min_size : 8;
4580 } s;
4581 struct cvmx_gmxx_txx_min_pkt_s cn30xx;
4582 struct cvmx_gmxx_txx_min_pkt_s cn31xx;
4583 struct cvmx_gmxx_txx_min_pkt_s cn38xx;
4584 struct cvmx_gmxx_txx_min_pkt_s cn38xxp2;
4585 struct cvmx_gmxx_txx_min_pkt_s cn50xx;
4586 struct cvmx_gmxx_txx_min_pkt_s cn52xx;
4587 struct cvmx_gmxx_txx_min_pkt_s cn52xxp1;
4588 struct cvmx_gmxx_txx_min_pkt_s cn56xx;
4589 struct cvmx_gmxx_txx_min_pkt_s cn56xxp1;
4590 struct cvmx_gmxx_txx_min_pkt_s cn58xx;
4591 struct cvmx_gmxx_txx_min_pkt_s cn58xxp1;
4592 struct cvmx_gmxx_txx_min_pkt_s cn61xx;
4593 struct cvmx_gmxx_txx_min_pkt_s cn63xx;
4594 struct cvmx_gmxx_txx_min_pkt_s cn63xxp1;
4595 struct cvmx_gmxx_txx_min_pkt_s cn66xx;
4596 struct cvmx_gmxx_txx_min_pkt_s cn68xx;
4597 struct cvmx_gmxx_txx_min_pkt_s cn68xxp1;
4598 struct cvmx_gmxx_txx_min_pkt_s cn70xx;
4599 struct cvmx_gmxx_txx_min_pkt_s cn70xxp1;
4600 struct cvmx_gmxx_txx_min_pkt_s cnf71xx;
4601};
4602
4603typedef union cvmx_gmxx_txx_min_pkt cvmx_gmxx_txx_min_pkt_t;
4604
4605/**
4606 * cvmx_gmx#_tx#_pause_pkt_interval
4607 *
4608 * GMX_TX_PAUSE_PKT_INTERVAL = Packet TX Pause Packet transmission interval - how often PAUSE packets will be sent
4609 *
4610 *
4611 * Notes:
4612 * Choosing proper values of GMX_TX_PAUSE_PKT_TIME[TIME] and
4613 * GMX_TX_PAUSE_PKT_INTERVAL[INTERVAL] can be challenging to the system
4614 * designer. It is suggested that TIME be much greater than INTERVAL and
4615 * GMX_TX_PAUSE_ZERO[SEND] be set. This allows a periodic refresh of the PAUSE
4616 * count and then when the backpressure condition is lifted, a PAUSE packet
4617 * with TIME==0 will be sent indicating that Octane is ready for additional
4618 * data.
4619 *
4620 * If the system chooses to not set GMX_TX_PAUSE_ZERO[SEND], then it is
4621 * suggested that TIME and INTERVAL are programmed such that they satisify the
4622 * following rule...
4623 *
4624 * INTERVAL <= TIME - (largest_pkt_size + IFG + pause_pkt_size)
4625 *
4626 * where largest_pkt_size is that largest packet that the system can send
4627 * (normally 1518B), IFG is the interframe gap and pause_pkt_size is the size
4628 * of the PAUSE packet (normally 64B).
4629 */
4630union cvmx_gmxx_txx_pause_pkt_interval {
4631 u64 u64;
4632 struct cvmx_gmxx_txx_pause_pkt_interval_s {
4633 u64 reserved_16_63 : 48;
4634 u64 interval : 16;
4635 } s;
4636 struct cvmx_gmxx_txx_pause_pkt_interval_s cn30xx;
4637 struct cvmx_gmxx_txx_pause_pkt_interval_s cn31xx;
4638 struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xx;
4639 struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xxp2;
4640 struct cvmx_gmxx_txx_pause_pkt_interval_s cn50xx;
4641 struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xx;
4642 struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xxp1;
4643 struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xx;
4644 struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xxp1;
4645 struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xx;
4646 struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xxp1;
4647 struct cvmx_gmxx_txx_pause_pkt_interval_s cn61xx;
4648 struct cvmx_gmxx_txx_pause_pkt_interval_s cn63xx;
4649 struct cvmx_gmxx_txx_pause_pkt_interval_s cn63xxp1;
4650 struct cvmx_gmxx_txx_pause_pkt_interval_s cn66xx;
4651 struct cvmx_gmxx_txx_pause_pkt_interval_s cn68xx;
4652 struct cvmx_gmxx_txx_pause_pkt_interval_s cn68xxp1;
4653 struct cvmx_gmxx_txx_pause_pkt_interval_s cn70xx;
4654 struct cvmx_gmxx_txx_pause_pkt_interval_s cn70xxp1;
4655 struct cvmx_gmxx_txx_pause_pkt_interval_s cnf71xx;
4656};
4657
4658typedef union cvmx_gmxx_txx_pause_pkt_interval cvmx_gmxx_txx_pause_pkt_interval_t;
4659
4660/**
4661 * cvmx_gmx#_tx#_pause_pkt_time
4662 *
4663 * GMX_TX_PAUSE_PKT_TIME = Packet TX Pause Packet pause_time field
4664 *
4665 *
4666 * Notes:
4667 * Choosing proper values of GMX_TX_PAUSE_PKT_TIME[TIME] and
4668 * GMX_TX_PAUSE_PKT_INTERVAL[INTERVAL] can be challenging to the system
4669 * designer. It is suggested that TIME be much greater than INTERVAL and
4670 * GMX_TX_PAUSE_ZERO[SEND] be set. This allows a periodic refresh of the PAUSE
4671 * count and then when the backpressure condition is lifted, a PAUSE packet
4672 * with TIME==0 will be sent indicating that Octane is ready for additional
4673 * data.
4674 *
4675 * If the system chooses to not set GMX_TX_PAUSE_ZERO[SEND], then it is
4676 * suggested that TIME and INTERVAL are programmed such that they satisify the
4677 * following rule...
4678 *
4679 * INTERVAL <= TIME - (largest_pkt_size + IFG + pause_pkt_size)
4680 *
4681 * where largest_pkt_size is that largest packet that the system can send
4682 * (normally 1518B), IFG is the interframe gap and pause_pkt_size is the size
4683 * of the PAUSE packet (normally 64B).
4684 */
4685union cvmx_gmxx_txx_pause_pkt_time {
4686 u64 u64;
4687 struct cvmx_gmxx_txx_pause_pkt_time_s {
4688 u64 reserved_16_63 : 48;
4689 u64 time : 16;
4690 } s;
4691 struct cvmx_gmxx_txx_pause_pkt_time_s cn30xx;
4692 struct cvmx_gmxx_txx_pause_pkt_time_s cn31xx;
4693 struct cvmx_gmxx_txx_pause_pkt_time_s cn38xx;
4694 struct cvmx_gmxx_txx_pause_pkt_time_s cn38xxp2;
4695 struct cvmx_gmxx_txx_pause_pkt_time_s cn50xx;
4696 struct cvmx_gmxx_txx_pause_pkt_time_s cn52xx;
4697 struct cvmx_gmxx_txx_pause_pkt_time_s cn52xxp1;
4698 struct cvmx_gmxx_txx_pause_pkt_time_s cn56xx;
4699 struct cvmx_gmxx_txx_pause_pkt_time_s cn56xxp1;
4700 struct cvmx_gmxx_txx_pause_pkt_time_s cn58xx;
4701 struct cvmx_gmxx_txx_pause_pkt_time_s cn58xxp1;
4702 struct cvmx_gmxx_txx_pause_pkt_time_s cn61xx;
4703 struct cvmx_gmxx_txx_pause_pkt_time_s cn63xx;
4704 struct cvmx_gmxx_txx_pause_pkt_time_s cn63xxp1;
4705 struct cvmx_gmxx_txx_pause_pkt_time_s cn66xx;
4706 struct cvmx_gmxx_txx_pause_pkt_time_s cn68xx;
4707 struct cvmx_gmxx_txx_pause_pkt_time_s cn68xxp1;
4708 struct cvmx_gmxx_txx_pause_pkt_time_s cn70xx;
4709 struct cvmx_gmxx_txx_pause_pkt_time_s cn70xxp1;
4710 struct cvmx_gmxx_txx_pause_pkt_time_s cnf71xx;
4711};
4712
4713typedef union cvmx_gmxx_txx_pause_pkt_time cvmx_gmxx_txx_pause_pkt_time_t;
4714
4715/**
4716 * cvmx_gmx#_tx#_pause_togo
4717 *
4718 * GMX_TX_PAUSE_TOGO = Packet TX Amount of time remaining to backpressure
4719 *
4720 */
4721union cvmx_gmxx_txx_pause_togo {
4722 u64 u64;
4723 struct cvmx_gmxx_txx_pause_togo_s {
4724 u64 reserved_32_63 : 32;
4725 u64 msg_time : 16;
4726 u64 time : 16;
4727 } s;
4728 struct cvmx_gmxx_txx_pause_togo_cn30xx {
4729 u64 reserved_16_63 : 48;
4730 u64 time : 16;
4731 } cn30xx;
4732 struct cvmx_gmxx_txx_pause_togo_cn30xx cn31xx;
4733 struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xx;
4734 struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xxp2;
4735 struct cvmx_gmxx_txx_pause_togo_cn30xx cn50xx;
4736 struct cvmx_gmxx_txx_pause_togo_s cn52xx;
4737 struct cvmx_gmxx_txx_pause_togo_s cn52xxp1;
4738 struct cvmx_gmxx_txx_pause_togo_s cn56xx;
4739 struct cvmx_gmxx_txx_pause_togo_cn30xx cn56xxp1;
4740 struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xx;
4741 struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xxp1;
4742 struct cvmx_gmxx_txx_pause_togo_s cn61xx;
4743 struct cvmx_gmxx_txx_pause_togo_s cn63xx;
4744 struct cvmx_gmxx_txx_pause_togo_s cn63xxp1;
4745 struct cvmx_gmxx_txx_pause_togo_s cn66xx;
4746 struct cvmx_gmxx_txx_pause_togo_s cn68xx;
4747 struct cvmx_gmxx_txx_pause_togo_s cn68xxp1;
4748 struct cvmx_gmxx_txx_pause_togo_s cn70xx;
4749 struct cvmx_gmxx_txx_pause_togo_s cn70xxp1;
4750 struct cvmx_gmxx_txx_pause_togo_s cnf71xx;
4751};
4752
4753typedef union cvmx_gmxx_txx_pause_togo cvmx_gmxx_txx_pause_togo_t;
4754
4755/**
4756 * cvmx_gmx#_tx#_pause_zero
4757 *
4758 * GMX_TX_PAUSE_ZERO = Packet TX Amount of time remaining to backpressure
4759 *
4760 */
4761union cvmx_gmxx_txx_pause_zero {
4762 u64 u64;
4763 struct cvmx_gmxx_txx_pause_zero_s {
4764 u64 reserved_1_63 : 63;
4765 u64 send : 1;
4766 } s;
4767 struct cvmx_gmxx_txx_pause_zero_s cn30xx;
4768 struct cvmx_gmxx_txx_pause_zero_s cn31xx;
4769 struct cvmx_gmxx_txx_pause_zero_s cn38xx;
4770 struct cvmx_gmxx_txx_pause_zero_s cn38xxp2;
4771 struct cvmx_gmxx_txx_pause_zero_s cn50xx;
4772 struct cvmx_gmxx_txx_pause_zero_s cn52xx;
4773 struct cvmx_gmxx_txx_pause_zero_s cn52xxp1;
4774 struct cvmx_gmxx_txx_pause_zero_s cn56xx;
4775 struct cvmx_gmxx_txx_pause_zero_s cn56xxp1;
4776 struct cvmx_gmxx_txx_pause_zero_s cn58xx;
4777 struct cvmx_gmxx_txx_pause_zero_s cn58xxp1;
4778 struct cvmx_gmxx_txx_pause_zero_s cn61xx;
4779 struct cvmx_gmxx_txx_pause_zero_s cn63xx;
4780 struct cvmx_gmxx_txx_pause_zero_s cn63xxp1;
4781 struct cvmx_gmxx_txx_pause_zero_s cn66xx;
4782 struct cvmx_gmxx_txx_pause_zero_s cn68xx;
4783 struct cvmx_gmxx_txx_pause_zero_s cn68xxp1;
4784 struct cvmx_gmxx_txx_pause_zero_s cn70xx;
4785 struct cvmx_gmxx_txx_pause_zero_s cn70xxp1;
4786 struct cvmx_gmxx_txx_pause_zero_s cnf71xx;
4787};
4788
4789typedef union cvmx_gmxx_txx_pause_zero cvmx_gmxx_txx_pause_zero_t;
4790
4791/**
4792 * cvmx_gmx#_tx#_pipe
4793 */
4794union cvmx_gmxx_txx_pipe {
4795 u64 u64;
4796 struct cvmx_gmxx_txx_pipe_s {
4797 u64 reserved_33_63 : 31;
4798 u64 ign_bp : 1;
4799 u64 reserved_21_31 : 11;
4800 u64 nump : 5;
4801 u64 reserved_7_15 : 9;
4802 u64 base : 7;
4803 } s;
4804 struct cvmx_gmxx_txx_pipe_s cn68xx;
4805 struct cvmx_gmxx_txx_pipe_s cn68xxp1;
4806};
4807
4808typedef union cvmx_gmxx_txx_pipe cvmx_gmxx_txx_pipe_t;
4809
4810/**
4811 * cvmx_gmx#_tx#_sgmii_ctl
4812 */
4813union cvmx_gmxx_txx_sgmii_ctl {
4814 u64 u64;
4815 struct cvmx_gmxx_txx_sgmii_ctl_s {
4816 u64 reserved_1_63 : 63;
4817 u64 align : 1;
4818 } s;
4819 struct cvmx_gmxx_txx_sgmii_ctl_s cn52xx;
4820 struct cvmx_gmxx_txx_sgmii_ctl_s cn52xxp1;
4821 struct cvmx_gmxx_txx_sgmii_ctl_s cn56xx;
4822 struct cvmx_gmxx_txx_sgmii_ctl_s cn56xxp1;
4823 struct cvmx_gmxx_txx_sgmii_ctl_s cn61xx;
4824 struct cvmx_gmxx_txx_sgmii_ctl_s cn63xx;
4825 struct cvmx_gmxx_txx_sgmii_ctl_s cn63xxp1;
4826 struct cvmx_gmxx_txx_sgmii_ctl_s cn66xx;
4827 struct cvmx_gmxx_txx_sgmii_ctl_s cn68xx;
4828 struct cvmx_gmxx_txx_sgmii_ctl_s cn68xxp1;
4829 struct cvmx_gmxx_txx_sgmii_ctl_s cn70xx;
4830 struct cvmx_gmxx_txx_sgmii_ctl_s cn70xxp1;
4831 struct cvmx_gmxx_txx_sgmii_ctl_s cnf71xx;
4832};
4833
4834typedef union cvmx_gmxx_txx_sgmii_ctl cvmx_gmxx_txx_sgmii_ctl_t;
4835
4836/**
4837 * cvmx_gmx#_tx#_slot
4838 *
4839 * GMX_TX_SLOT = Packet TX Slottime Counter
4840 *
4841 */
4842union cvmx_gmxx_txx_slot {
4843 u64 u64;
4844 struct cvmx_gmxx_txx_slot_s {
4845 u64 reserved_10_63 : 54;
4846 u64 slot : 10;
4847 } s;
4848 struct cvmx_gmxx_txx_slot_s cn30xx;
4849 struct cvmx_gmxx_txx_slot_s cn31xx;
4850 struct cvmx_gmxx_txx_slot_s cn38xx;
4851 struct cvmx_gmxx_txx_slot_s cn38xxp2;
4852 struct cvmx_gmxx_txx_slot_s cn50xx;
4853 struct cvmx_gmxx_txx_slot_s cn52xx;
4854 struct cvmx_gmxx_txx_slot_s cn52xxp1;
4855 struct cvmx_gmxx_txx_slot_s cn56xx;
4856 struct cvmx_gmxx_txx_slot_s cn56xxp1;
4857 struct cvmx_gmxx_txx_slot_s cn58xx;
4858 struct cvmx_gmxx_txx_slot_s cn58xxp1;
4859 struct cvmx_gmxx_txx_slot_s cn61xx;
4860 struct cvmx_gmxx_txx_slot_s cn63xx;
4861 struct cvmx_gmxx_txx_slot_s cn63xxp1;
4862 struct cvmx_gmxx_txx_slot_s cn66xx;
4863 struct cvmx_gmxx_txx_slot_s cn68xx;
4864 struct cvmx_gmxx_txx_slot_s cn68xxp1;
4865 struct cvmx_gmxx_txx_slot_s cn70xx;
4866 struct cvmx_gmxx_txx_slot_s cn70xxp1;
4867 struct cvmx_gmxx_txx_slot_s cnf71xx;
4868};
4869
4870typedef union cvmx_gmxx_txx_slot cvmx_gmxx_txx_slot_t;
4871
4872/**
4873 * cvmx_gmx#_tx#_soft_pause
4874 *
4875 * GMX_TX_SOFT_PAUSE = Packet TX Software Pause
4876 *
4877 */
4878union cvmx_gmxx_txx_soft_pause {
4879 u64 u64;
4880 struct cvmx_gmxx_txx_soft_pause_s {
4881 u64 reserved_16_63 : 48;
4882 u64 time : 16;
4883 } s;
4884 struct cvmx_gmxx_txx_soft_pause_s cn30xx;
4885 struct cvmx_gmxx_txx_soft_pause_s cn31xx;
4886 struct cvmx_gmxx_txx_soft_pause_s cn38xx;
4887 struct cvmx_gmxx_txx_soft_pause_s cn38xxp2;
4888 struct cvmx_gmxx_txx_soft_pause_s cn50xx;
4889 struct cvmx_gmxx_txx_soft_pause_s cn52xx;
4890 struct cvmx_gmxx_txx_soft_pause_s cn52xxp1;
4891 struct cvmx_gmxx_txx_soft_pause_s cn56xx;
4892 struct cvmx_gmxx_txx_soft_pause_s cn56xxp1;
4893 struct cvmx_gmxx_txx_soft_pause_s cn58xx;
4894 struct cvmx_gmxx_txx_soft_pause_s cn58xxp1;
4895 struct cvmx_gmxx_txx_soft_pause_s cn61xx;
4896 struct cvmx_gmxx_txx_soft_pause_s cn63xx;
4897 struct cvmx_gmxx_txx_soft_pause_s cn63xxp1;
4898 struct cvmx_gmxx_txx_soft_pause_s cn66xx;
4899 struct cvmx_gmxx_txx_soft_pause_s cn68xx;
4900 struct cvmx_gmxx_txx_soft_pause_s cn68xxp1;
4901 struct cvmx_gmxx_txx_soft_pause_s cn70xx;
4902 struct cvmx_gmxx_txx_soft_pause_s cn70xxp1;
4903 struct cvmx_gmxx_txx_soft_pause_s cnf71xx;
4904};
4905
4906typedef union cvmx_gmxx_txx_soft_pause cvmx_gmxx_txx_soft_pause_t;
4907
4908/**
4909 * cvmx_gmx#_tx#_stat0
4910 *
4911 * GMX_TX_STAT0 = GMX_TX_STATS_XSDEF / GMX_TX_STATS_XSCOL
4912 *
4913 *
4914 * Notes:
4915 * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
4916 * - Counters will wrap
4917 */
4918union cvmx_gmxx_txx_stat0 {
4919 u64 u64;
4920 struct cvmx_gmxx_txx_stat0_s {
4921 u64 xsdef : 32;
4922 u64 xscol : 32;
4923 } s;
4924 struct cvmx_gmxx_txx_stat0_s cn30xx;
4925 struct cvmx_gmxx_txx_stat0_s cn31xx;
4926 struct cvmx_gmxx_txx_stat0_s cn38xx;
4927 struct cvmx_gmxx_txx_stat0_s cn38xxp2;
4928 struct cvmx_gmxx_txx_stat0_s cn50xx;
4929 struct cvmx_gmxx_txx_stat0_s cn52xx;
4930 struct cvmx_gmxx_txx_stat0_s cn52xxp1;
4931 struct cvmx_gmxx_txx_stat0_s cn56xx;
4932 struct cvmx_gmxx_txx_stat0_s cn56xxp1;
4933 struct cvmx_gmxx_txx_stat0_s cn58xx;
4934 struct cvmx_gmxx_txx_stat0_s cn58xxp1;
4935 struct cvmx_gmxx_txx_stat0_s cn61xx;
4936 struct cvmx_gmxx_txx_stat0_s cn63xx;
4937 struct cvmx_gmxx_txx_stat0_s cn63xxp1;
4938 struct cvmx_gmxx_txx_stat0_s cn66xx;
4939 struct cvmx_gmxx_txx_stat0_s cn68xx;
4940 struct cvmx_gmxx_txx_stat0_s cn68xxp1;
4941 struct cvmx_gmxx_txx_stat0_s cn70xx;
4942 struct cvmx_gmxx_txx_stat0_s cn70xxp1;
4943 struct cvmx_gmxx_txx_stat0_s cnf71xx;
4944};
4945
4946typedef union cvmx_gmxx_txx_stat0 cvmx_gmxx_txx_stat0_t;
4947
4948/**
4949 * cvmx_gmx#_tx#_stat1
4950 *
4951 * GMX_TX_STAT1 = GMX_TX_STATS_SCOL / GMX_TX_STATS_MCOL
4952 *
4953 *
4954 * Notes:
4955 * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
4956 * - Counters will wrap
4957 */
4958union cvmx_gmxx_txx_stat1 {
4959 u64 u64;
4960 struct cvmx_gmxx_txx_stat1_s {
4961 u64 scol : 32;
4962 u64 mcol : 32;
4963 } s;
4964 struct cvmx_gmxx_txx_stat1_s cn30xx;
4965 struct cvmx_gmxx_txx_stat1_s cn31xx;
4966 struct cvmx_gmxx_txx_stat1_s cn38xx;
4967 struct cvmx_gmxx_txx_stat1_s cn38xxp2;
4968 struct cvmx_gmxx_txx_stat1_s cn50xx;
4969 struct cvmx_gmxx_txx_stat1_s cn52xx;
4970 struct cvmx_gmxx_txx_stat1_s cn52xxp1;
4971 struct cvmx_gmxx_txx_stat1_s cn56xx;
4972 struct cvmx_gmxx_txx_stat1_s cn56xxp1;
4973 struct cvmx_gmxx_txx_stat1_s cn58xx;
4974 struct cvmx_gmxx_txx_stat1_s cn58xxp1;
4975 struct cvmx_gmxx_txx_stat1_s cn61xx;
4976 struct cvmx_gmxx_txx_stat1_s cn63xx;
4977 struct cvmx_gmxx_txx_stat1_s cn63xxp1;
4978 struct cvmx_gmxx_txx_stat1_s cn66xx;
4979 struct cvmx_gmxx_txx_stat1_s cn68xx;
4980 struct cvmx_gmxx_txx_stat1_s cn68xxp1;
4981 struct cvmx_gmxx_txx_stat1_s cn70xx;
4982 struct cvmx_gmxx_txx_stat1_s cn70xxp1;
4983 struct cvmx_gmxx_txx_stat1_s cnf71xx;
4984};
4985
4986typedef union cvmx_gmxx_txx_stat1 cvmx_gmxx_txx_stat1_t;
4987
4988/**
4989 * cvmx_gmx#_tx#_stat2
4990 *
4991 * GMX_TX_STAT2 = GMX_TX_STATS_OCTS
4992 *
4993 *
4994 * Notes:
4995 * - Octect counts are the sum of all data transmitted on the wire including
4996 * packet data, pad bytes, fcs bytes, pause bytes, and jam bytes. The octect
4997 * counts do not include PREAMBLE byte or EXTEND cycles.
4998 * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
4999 * - Counters will wrap
5000 */
5001union cvmx_gmxx_txx_stat2 {
5002 u64 u64;
5003 struct cvmx_gmxx_txx_stat2_s {
5004 u64 reserved_48_63 : 16;
5005 u64 octs : 48;
5006 } s;
5007 struct cvmx_gmxx_txx_stat2_s cn30xx;
5008 struct cvmx_gmxx_txx_stat2_s cn31xx;
5009 struct cvmx_gmxx_txx_stat2_s cn38xx;
5010 struct cvmx_gmxx_txx_stat2_s cn38xxp2;
5011 struct cvmx_gmxx_txx_stat2_s cn50xx;
5012 struct cvmx_gmxx_txx_stat2_s cn52xx;
5013 struct cvmx_gmxx_txx_stat2_s cn52xxp1;
5014 struct cvmx_gmxx_txx_stat2_s cn56xx;
5015 struct cvmx_gmxx_txx_stat2_s cn56xxp1;
5016 struct cvmx_gmxx_txx_stat2_s cn58xx;
5017 struct cvmx_gmxx_txx_stat2_s cn58xxp1;
5018 struct cvmx_gmxx_txx_stat2_s cn61xx;
5019 struct cvmx_gmxx_txx_stat2_s cn63xx;
5020 struct cvmx_gmxx_txx_stat2_s cn63xxp1;
5021 struct cvmx_gmxx_txx_stat2_s cn66xx;
5022 struct cvmx_gmxx_txx_stat2_s cn68xx;
5023 struct cvmx_gmxx_txx_stat2_s cn68xxp1;
5024 struct cvmx_gmxx_txx_stat2_s cn70xx;
5025 struct cvmx_gmxx_txx_stat2_s cn70xxp1;
5026 struct cvmx_gmxx_txx_stat2_s cnf71xx;
5027};
5028
5029typedef union cvmx_gmxx_txx_stat2 cvmx_gmxx_txx_stat2_t;
5030
5031/**
5032 * cvmx_gmx#_tx#_stat3
5033 *
5034 * GMX_TX_STAT3 = GMX_TX_STATS_PKTS
5035 *
5036 *
5037 * Notes:
5038 * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
5039 * - Counters will wrap
5040 */
5041union cvmx_gmxx_txx_stat3 {
5042 u64 u64;
5043 struct cvmx_gmxx_txx_stat3_s {
5044 u64 reserved_32_63 : 32;
5045 u64 pkts : 32;
5046 } s;
5047 struct cvmx_gmxx_txx_stat3_s cn30xx;
5048 struct cvmx_gmxx_txx_stat3_s cn31xx;
5049 struct cvmx_gmxx_txx_stat3_s cn38xx;
5050 struct cvmx_gmxx_txx_stat3_s cn38xxp2;
5051 struct cvmx_gmxx_txx_stat3_s cn50xx;
5052 struct cvmx_gmxx_txx_stat3_s cn52xx;
5053 struct cvmx_gmxx_txx_stat3_s cn52xxp1;
5054 struct cvmx_gmxx_txx_stat3_s cn56xx;
5055 struct cvmx_gmxx_txx_stat3_s cn56xxp1;
5056 struct cvmx_gmxx_txx_stat3_s cn58xx;
5057 struct cvmx_gmxx_txx_stat3_s cn58xxp1;
5058 struct cvmx_gmxx_txx_stat3_s cn61xx;
5059 struct cvmx_gmxx_txx_stat3_s cn63xx;
5060 struct cvmx_gmxx_txx_stat3_s cn63xxp1;
5061 struct cvmx_gmxx_txx_stat3_s cn66xx;
5062 struct cvmx_gmxx_txx_stat3_s cn68xx;
5063 struct cvmx_gmxx_txx_stat3_s cn68xxp1;
5064 struct cvmx_gmxx_txx_stat3_s cn70xx;
5065 struct cvmx_gmxx_txx_stat3_s cn70xxp1;
5066 struct cvmx_gmxx_txx_stat3_s cnf71xx;
5067};
5068
5069typedef union cvmx_gmxx_txx_stat3 cvmx_gmxx_txx_stat3_t;
5070
5071/**
5072 * cvmx_gmx#_tx#_stat4
5073 *
5074 * GMX_TX_STAT4 = GMX_TX_STATS_HIST1 (64) / GMX_TX_STATS_HIST0 (<64)
5075 *
5076 *
5077 * Notes:
5078 * - Packet length is the sum of all data transmitted on the wire for the given
5079 * packet including packet data, pad bytes, fcs bytes, pause bytes, and jam
5080 * bytes. The octect counts do not include PREAMBLE byte or EXTEND cycles.
5081 * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
5082 * - Counters will wrap
5083 */
5084union cvmx_gmxx_txx_stat4 {
5085 u64 u64;
5086 struct cvmx_gmxx_txx_stat4_s {
5087 u64 hist1 : 32;
5088 u64 hist0 : 32;
5089 } s;
5090 struct cvmx_gmxx_txx_stat4_s cn30xx;
5091 struct cvmx_gmxx_txx_stat4_s cn31xx;
5092 struct cvmx_gmxx_txx_stat4_s cn38xx;
5093 struct cvmx_gmxx_txx_stat4_s cn38xxp2;
5094 struct cvmx_gmxx_txx_stat4_s cn50xx;
5095 struct cvmx_gmxx_txx_stat4_s cn52xx;
5096 struct cvmx_gmxx_txx_stat4_s cn52xxp1;
5097 struct cvmx_gmxx_txx_stat4_s cn56xx;
5098 struct cvmx_gmxx_txx_stat4_s cn56xxp1;
5099 struct cvmx_gmxx_txx_stat4_s cn58xx;
5100 struct cvmx_gmxx_txx_stat4_s cn58xxp1;
5101 struct cvmx_gmxx_txx_stat4_s cn61xx;
5102 struct cvmx_gmxx_txx_stat4_s cn63xx;
5103 struct cvmx_gmxx_txx_stat4_s cn63xxp1;
5104 struct cvmx_gmxx_txx_stat4_s cn66xx;
5105 struct cvmx_gmxx_txx_stat4_s cn68xx;
5106 struct cvmx_gmxx_txx_stat4_s cn68xxp1;
5107 struct cvmx_gmxx_txx_stat4_s cn70xx;
5108 struct cvmx_gmxx_txx_stat4_s cn70xxp1;
5109 struct cvmx_gmxx_txx_stat4_s cnf71xx;
5110};
5111
5112typedef union cvmx_gmxx_txx_stat4 cvmx_gmxx_txx_stat4_t;
5113
5114/**
5115 * cvmx_gmx#_tx#_stat5
5116 *
5117 * GMX_TX_STAT5 = GMX_TX_STATS_HIST3 (128- 255) / GMX_TX_STATS_HIST2 (65- 127)
5118 *
5119 *
5120 * Notes:
5121 * - Packet length is the sum of all data transmitted on the wire for the given
5122 * packet including packet data, pad bytes, fcs bytes, pause bytes, and jam
5123 * bytes. The octect counts do not include PREAMBLE byte or EXTEND cycles.
5124 * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
5125 * - Counters will wrap
5126 */
5127union cvmx_gmxx_txx_stat5 {
5128 u64 u64;
5129 struct cvmx_gmxx_txx_stat5_s {
5130 u64 hist3 : 32;
5131 u64 hist2 : 32;
5132 } s;
5133 struct cvmx_gmxx_txx_stat5_s cn30xx;
5134 struct cvmx_gmxx_txx_stat5_s cn31xx;
5135 struct cvmx_gmxx_txx_stat5_s cn38xx;
5136 struct cvmx_gmxx_txx_stat5_s cn38xxp2;
5137 struct cvmx_gmxx_txx_stat5_s cn50xx;
5138 struct cvmx_gmxx_txx_stat5_s cn52xx;
5139 struct cvmx_gmxx_txx_stat5_s cn52xxp1;
5140 struct cvmx_gmxx_txx_stat5_s cn56xx;
5141 struct cvmx_gmxx_txx_stat5_s cn56xxp1;
5142 struct cvmx_gmxx_txx_stat5_s cn58xx;
5143 struct cvmx_gmxx_txx_stat5_s cn58xxp1;
5144 struct cvmx_gmxx_txx_stat5_s cn61xx;
5145 struct cvmx_gmxx_txx_stat5_s cn63xx;
5146 struct cvmx_gmxx_txx_stat5_s cn63xxp1;
5147 struct cvmx_gmxx_txx_stat5_s cn66xx;
5148 struct cvmx_gmxx_txx_stat5_s cn68xx;
5149 struct cvmx_gmxx_txx_stat5_s cn68xxp1;
5150 struct cvmx_gmxx_txx_stat5_s cn70xx;
5151 struct cvmx_gmxx_txx_stat5_s cn70xxp1;
5152 struct cvmx_gmxx_txx_stat5_s cnf71xx;
5153};
5154
5155typedef union cvmx_gmxx_txx_stat5 cvmx_gmxx_txx_stat5_t;
5156
5157/**
5158 * cvmx_gmx#_tx#_stat6
5159 *
5160 * GMX_TX_STAT6 = GMX_TX_STATS_HIST5 (512-1023) / GMX_TX_STATS_HIST4 (256-511)
5161 *
5162 *
5163 * Notes:
5164 * - Packet length is the sum of all data transmitted on the wire for the given
5165 * packet including packet data, pad bytes, fcs bytes, pause bytes, and jam
5166 * bytes. The octect counts do not include PREAMBLE byte or EXTEND cycles.
5167 * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
5168 * - Counters will wrap
5169 */
5170union cvmx_gmxx_txx_stat6 {
5171 u64 u64;
5172 struct cvmx_gmxx_txx_stat6_s {
5173 u64 hist5 : 32;
5174 u64 hist4 : 32;
5175 } s;
5176 struct cvmx_gmxx_txx_stat6_s cn30xx;
5177 struct cvmx_gmxx_txx_stat6_s cn31xx;
5178 struct cvmx_gmxx_txx_stat6_s cn38xx;
5179 struct cvmx_gmxx_txx_stat6_s cn38xxp2;
5180 struct cvmx_gmxx_txx_stat6_s cn50xx;
5181 struct cvmx_gmxx_txx_stat6_s cn52xx;
5182 struct cvmx_gmxx_txx_stat6_s cn52xxp1;
5183 struct cvmx_gmxx_txx_stat6_s cn56xx;
5184 struct cvmx_gmxx_txx_stat6_s cn56xxp1;
5185 struct cvmx_gmxx_txx_stat6_s cn58xx;
5186 struct cvmx_gmxx_txx_stat6_s cn58xxp1;
5187 struct cvmx_gmxx_txx_stat6_s cn61xx;
5188 struct cvmx_gmxx_txx_stat6_s cn63xx;
5189 struct cvmx_gmxx_txx_stat6_s cn63xxp1;
5190 struct cvmx_gmxx_txx_stat6_s cn66xx;
5191 struct cvmx_gmxx_txx_stat6_s cn68xx;
5192 struct cvmx_gmxx_txx_stat6_s cn68xxp1;
5193 struct cvmx_gmxx_txx_stat6_s cn70xx;
5194 struct cvmx_gmxx_txx_stat6_s cn70xxp1;
5195 struct cvmx_gmxx_txx_stat6_s cnf71xx;
5196};
5197
5198typedef union cvmx_gmxx_txx_stat6 cvmx_gmxx_txx_stat6_t;
5199
5200/**
5201 * cvmx_gmx#_tx#_stat7
5202 *
5203 * GMX_TX_STAT7 = GMX_TX_STATS_HIST7 (1024-1518) / GMX_TX_STATS_HIST6 (>1518)
5204 *
5205 *
5206 * Notes:
5207 * - Packet length is the sum of all data transmitted on the wire for the given
5208 * packet including packet data, pad bytes, fcs bytes, pause bytes, and jam
5209 * bytes. The octect counts do not include PREAMBLE byte or EXTEND cycles.
5210 * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
5211 * - Counters will wrap
5212 */
5213union cvmx_gmxx_txx_stat7 {
5214 u64 u64;
5215 struct cvmx_gmxx_txx_stat7_s {
5216 u64 hist7 : 32;
5217 u64 hist6 : 32;
5218 } s;
5219 struct cvmx_gmxx_txx_stat7_s cn30xx;
5220 struct cvmx_gmxx_txx_stat7_s cn31xx;
5221 struct cvmx_gmxx_txx_stat7_s cn38xx;
5222 struct cvmx_gmxx_txx_stat7_s cn38xxp2;
5223 struct cvmx_gmxx_txx_stat7_s cn50xx;
5224 struct cvmx_gmxx_txx_stat7_s cn52xx;
5225 struct cvmx_gmxx_txx_stat7_s cn52xxp1;
5226 struct cvmx_gmxx_txx_stat7_s cn56xx;
5227 struct cvmx_gmxx_txx_stat7_s cn56xxp1;
5228 struct cvmx_gmxx_txx_stat7_s cn58xx;
5229 struct cvmx_gmxx_txx_stat7_s cn58xxp1;
5230 struct cvmx_gmxx_txx_stat7_s cn61xx;
5231 struct cvmx_gmxx_txx_stat7_s cn63xx;
5232 struct cvmx_gmxx_txx_stat7_s cn63xxp1;
5233 struct cvmx_gmxx_txx_stat7_s cn66xx;
5234 struct cvmx_gmxx_txx_stat7_s cn68xx;
5235 struct cvmx_gmxx_txx_stat7_s cn68xxp1;
5236 struct cvmx_gmxx_txx_stat7_s cn70xx;
5237 struct cvmx_gmxx_txx_stat7_s cn70xxp1;
5238 struct cvmx_gmxx_txx_stat7_s cnf71xx;
5239};
5240
5241typedef union cvmx_gmxx_txx_stat7 cvmx_gmxx_txx_stat7_t;
5242
5243/**
5244 * cvmx_gmx#_tx#_stat8
5245 *
5246 * GMX_TX_STAT8 = GMX_TX_STATS_MCST / GMX_TX_STATS_BCST
5247 *
5248 *
5249 * Notes:
5250 * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
5251 * - Counters will wrap
5252 * - Note, GMX determines if the packet is MCST or BCST from the DMAC of the
5253 * packet. GMX assumes that the DMAC lies in the first 6 bytes of the packet
5254 * as per the 802.3 frame definition. If the system requires additional data
5255 * before the L2 header, then the MCST and BCST counters may not reflect
5256 * reality and should be ignored by software.
5257 */
5258union cvmx_gmxx_txx_stat8 {
5259 u64 u64;
5260 struct cvmx_gmxx_txx_stat8_s {
5261 u64 mcst : 32;
5262 u64 bcst : 32;
5263 } s;
5264 struct cvmx_gmxx_txx_stat8_s cn30xx;
5265 struct cvmx_gmxx_txx_stat8_s cn31xx;
5266 struct cvmx_gmxx_txx_stat8_s cn38xx;
5267 struct cvmx_gmxx_txx_stat8_s cn38xxp2;
5268 struct cvmx_gmxx_txx_stat8_s cn50xx;
5269 struct cvmx_gmxx_txx_stat8_s cn52xx;
5270 struct cvmx_gmxx_txx_stat8_s cn52xxp1;
5271 struct cvmx_gmxx_txx_stat8_s cn56xx;
5272 struct cvmx_gmxx_txx_stat8_s cn56xxp1;
5273 struct cvmx_gmxx_txx_stat8_s cn58xx;
5274 struct cvmx_gmxx_txx_stat8_s cn58xxp1;
5275 struct cvmx_gmxx_txx_stat8_s cn61xx;
5276 struct cvmx_gmxx_txx_stat8_s cn63xx;
5277 struct cvmx_gmxx_txx_stat8_s cn63xxp1;
5278 struct cvmx_gmxx_txx_stat8_s cn66xx;
5279 struct cvmx_gmxx_txx_stat8_s cn68xx;
5280 struct cvmx_gmxx_txx_stat8_s cn68xxp1;
5281 struct cvmx_gmxx_txx_stat8_s cn70xx;
5282 struct cvmx_gmxx_txx_stat8_s cn70xxp1;
5283 struct cvmx_gmxx_txx_stat8_s cnf71xx;
5284};
5285
5286typedef union cvmx_gmxx_txx_stat8 cvmx_gmxx_txx_stat8_t;
5287
5288/**
5289 * cvmx_gmx#_tx#_stat9
5290 *
5291 * GMX_TX_STAT9 = GMX_TX_STATS_UNDFLW / GMX_TX_STATS_CTL
5292 *
5293 *
5294 * Notes:
5295 * - Cleared either by a write (of any value) or a read when GMX_TX_STATS_CTL[RD_CLR] is set
5296 * - Counters will wrap
5297 */
5298union cvmx_gmxx_txx_stat9 {
5299 u64 u64;
5300 struct cvmx_gmxx_txx_stat9_s {
5301 u64 undflw : 32;
5302 u64 ctl : 32;
5303 } s;
5304 struct cvmx_gmxx_txx_stat9_s cn30xx;
5305 struct cvmx_gmxx_txx_stat9_s cn31xx;
5306 struct cvmx_gmxx_txx_stat9_s cn38xx;
5307 struct cvmx_gmxx_txx_stat9_s cn38xxp2;
5308 struct cvmx_gmxx_txx_stat9_s cn50xx;
5309 struct cvmx_gmxx_txx_stat9_s cn52xx;
5310 struct cvmx_gmxx_txx_stat9_s cn52xxp1;
5311 struct cvmx_gmxx_txx_stat9_s cn56xx;
5312 struct cvmx_gmxx_txx_stat9_s cn56xxp1;
5313 struct cvmx_gmxx_txx_stat9_s cn58xx;
5314 struct cvmx_gmxx_txx_stat9_s cn58xxp1;
5315 struct cvmx_gmxx_txx_stat9_s cn61xx;
5316 struct cvmx_gmxx_txx_stat9_s cn63xx;
5317 struct cvmx_gmxx_txx_stat9_s cn63xxp1;
5318 struct cvmx_gmxx_txx_stat9_s cn66xx;
5319 struct cvmx_gmxx_txx_stat9_s cn68xx;
5320 struct cvmx_gmxx_txx_stat9_s cn68xxp1;
5321 struct cvmx_gmxx_txx_stat9_s cn70xx;
5322 struct cvmx_gmxx_txx_stat9_s cn70xxp1;
5323 struct cvmx_gmxx_txx_stat9_s cnf71xx;
5324};
5325
5326typedef union cvmx_gmxx_txx_stat9 cvmx_gmxx_txx_stat9_t;
5327
5328/**
5329 * cvmx_gmx#_tx#_stats_ctl
5330 *
5331 * GMX_TX_STATS_CTL = TX Stats Control register
5332 *
5333 */
5334union cvmx_gmxx_txx_stats_ctl {
5335 u64 u64;
5336 struct cvmx_gmxx_txx_stats_ctl_s {
5337 u64 reserved_1_63 : 63;
5338 u64 rd_clr : 1;
5339 } s;
5340 struct cvmx_gmxx_txx_stats_ctl_s cn30xx;
5341 struct cvmx_gmxx_txx_stats_ctl_s cn31xx;
5342 struct cvmx_gmxx_txx_stats_ctl_s cn38xx;
5343 struct cvmx_gmxx_txx_stats_ctl_s cn38xxp2;
5344 struct cvmx_gmxx_txx_stats_ctl_s cn50xx;
5345 struct cvmx_gmxx_txx_stats_ctl_s cn52xx;
5346 struct cvmx_gmxx_txx_stats_ctl_s cn52xxp1;
5347 struct cvmx_gmxx_txx_stats_ctl_s cn56xx;
5348 struct cvmx_gmxx_txx_stats_ctl_s cn56xxp1;
5349 struct cvmx_gmxx_txx_stats_ctl_s cn58xx;
5350 struct cvmx_gmxx_txx_stats_ctl_s cn58xxp1;
5351 struct cvmx_gmxx_txx_stats_ctl_s cn61xx;
5352 struct cvmx_gmxx_txx_stats_ctl_s cn63xx;
5353 struct cvmx_gmxx_txx_stats_ctl_s cn63xxp1;
5354 struct cvmx_gmxx_txx_stats_ctl_s cn66xx;
5355 struct cvmx_gmxx_txx_stats_ctl_s cn68xx;
5356 struct cvmx_gmxx_txx_stats_ctl_s cn68xxp1;
5357 struct cvmx_gmxx_txx_stats_ctl_s cn70xx;
5358 struct cvmx_gmxx_txx_stats_ctl_s cn70xxp1;
5359 struct cvmx_gmxx_txx_stats_ctl_s cnf71xx;
5360};
5361
5362typedef union cvmx_gmxx_txx_stats_ctl cvmx_gmxx_txx_stats_ctl_t;
5363
5364/**
5365 * cvmx_gmx#_tx#_thresh
5366 *
5367 * Per Port
5368 * GMX_TX_THRESH = Packet TX Threshold
5369 */
5370union cvmx_gmxx_txx_thresh {
5371 u64 u64;
5372 struct cvmx_gmxx_txx_thresh_s {
5373 u64 reserved_10_63 : 54;
5374 u64 cnt : 10;
5375 } s;
5376 struct cvmx_gmxx_txx_thresh_cn30xx {
5377 u64 reserved_7_63 : 57;
5378 u64 cnt : 7;
5379 } cn30xx;
5380 struct cvmx_gmxx_txx_thresh_cn30xx cn31xx;
5381 struct cvmx_gmxx_txx_thresh_cn38xx {
5382 u64 reserved_9_63 : 55;
5383 u64 cnt : 9;
5384 } cn38xx;
5385 struct cvmx_gmxx_txx_thresh_cn38xx cn38xxp2;
5386 struct cvmx_gmxx_txx_thresh_cn30xx cn50xx;
5387 struct cvmx_gmxx_txx_thresh_cn38xx cn52xx;
5388 struct cvmx_gmxx_txx_thresh_cn38xx cn52xxp1;
5389 struct cvmx_gmxx_txx_thresh_cn38xx cn56xx;
5390 struct cvmx_gmxx_txx_thresh_cn38xx cn56xxp1;
5391 struct cvmx_gmxx_txx_thresh_cn38xx cn58xx;
5392 struct cvmx_gmxx_txx_thresh_cn38xx cn58xxp1;
5393 struct cvmx_gmxx_txx_thresh_cn38xx cn61xx;
5394 struct cvmx_gmxx_txx_thresh_cn38xx cn63xx;
5395 struct cvmx_gmxx_txx_thresh_cn38xx cn63xxp1;
5396 struct cvmx_gmxx_txx_thresh_cn38xx cn66xx;
5397 struct cvmx_gmxx_txx_thresh_s cn68xx;
5398 struct cvmx_gmxx_txx_thresh_s cn68xxp1;
5399 struct cvmx_gmxx_txx_thresh_cn38xx cn70xx;
5400 struct cvmx_gmxx_txx_thresh_cn38xx cn70xxp1;
5401 struct cvmx_gmxx_txx_thresh_cn38xx cnf71xx;
5402};
5403
5404typedef union cvmx_gmxx_txx_thresh cvmx_gmxx_txx_thresh_t;
5405
5406/**
5407 * cvmx_gmx#_tx_bp
5408 *
5409 * GMX_TX_BP = Packet Interface TX BackPressure Register
5410 *
5411 *
5412 * Notes:
5413 * In XAUI mode, only the lsb (corresponding to port0) of BP is used.
5414 *
5415 */
5416union cvmx_gmxx_tx_bp {
5417 u64 u64;
5418 struct cvmx_gmxx_tx_bp_s {
5419 u64 reserved_4_63 : 60;
5420 u64 bp : 4;
5421 } s;
5422 struct cvmx_gmxx_tx_bp_cn30xx {
5423 u64 reserved_3_63 : 61;
5424 u64 bp : 3;
5425 } cn30xx;
5426 struct cvmx_gmxx_tx_bp_cn30xx cn31xx;
5427 struct cvmx_gmxx_tx_bp_s cn38xx;
5428 struct cvmx_gmxx_tx_bp_s cn38xxp2;
5429 struct cvmx_gmxx_tx_bp_cn30xx cn50xx;
5430 struct cvmx_gmxx_tx_bp_s cn52xx;
5431 struct cvmx_gmxx_tx_bp_s cn52xxp1;
5432 struct cvmx_gmxx_tx_bp_s cn56xx;
5433 struct cvmx_gmxx_tx_bp_s cn56xxp1;
5434 struct cvmx_gmxx_tx_bp_s cn58xx;
5435 struct cvmx_gmxx_tx_bp_s cn58xxp1;
5436 struct cvmx_gmxx_tx_bp_s cn61xx;
5437 struct cvmx_gmxx_tx_bp_s cn63xx;
5438 struct cvmx_gmxx_tx_bp_s cn63xxp1;
5439 struct cvmx_gmxx_tx_bp_s cn66xx;
5440 struct cvmx_gmxx_tx_bp_s cn68xx;
5441 struct cvmx_gmxx_tx_bp_s cn68xxp1;
5442 struct cvmx_gmxx_tx_bp_s cn70xx;
5443 struct cvmx_gmxx_tx_bp_s cn70xxp1;
5444 struct cvmx_gmxx_tx_bp_cnf71xx {
5445 u64 reserved_2_63 : 62;
5446 u64 bp : 2;
5447 } cnf71xx;
5448};
5449
5450typedef union cvmx_gmxx_tx_bp cvmx_gmxx_tx_bp_t;
5451
5452/**
5453 * cvmx_gmx#_tx_clk_msk#
5454 *
5455 * GMX_TX_CLK_MSK = GMX Clock Select
5456 *
5457 */
5458union cvmx_gmxx_tx_clk_mskx {
5459 u64 u64;
5460 struct cvmx_gmxx_tx_clk_mskx_s {
5461 u64 reserved_1_63 : 63;
5462 u64 msk : 1;
5463 } s;
5464 struct cvmx_gmxx_tx_clk_mskx_s cn30xx;
5465 struct cvmx_gmxx_tx_clk_mskx_s cn50xx;
5466};
5467
5468typedef union cvmx_gmxx_tx_clk_mskx cvmx_gmxx_tx_clk_mskx_t;
5469
5470/**
5471 * cvmx_gmx#_tx_col_attempt
5472 *
5473 * GMX_TX_COL_ATTEMPT = Packet TX collision attempts before dropping frame
5474 *
5475 */
5476union cvmx_gmxx_tx_col_attempt {
5477 u64 u64;
5478 struct cvmx_gmxx_tx_col_attempt_s {
5479 u64 reserved_5_63 : 59;
5480 u64 limit : 5;
5481 } s;
5482 struct cvmx_gmxx_tx_col_attempt_s cn30xx;
5483 struct cvmx_gmxx_tx_col_attempt_s cn31xx;
5484 struct cvmx_gmxx_tx_col_attempt_s cn38xx;
5485 struct cvmx_gmxx_tx_col_attempt_s cn38xxp2;
5486 struct cvmx_gmxx_tx_col_attempt_s cn50xx;
5487 struct cvmx_gmxx_tx_col_attempt_s cn52xx;
5488 struct cvmx_gmxx_tx_col_attempt_s cn52xxp1;
5489 struct cvmx_gmxx_tx_col_attempt_s cn56xx;
5490 struct cvmx_gmxx_tx_col_attempt_s cn56xxp1;
5491 struct cvmx_gmxx_tx_col_attempt_s cn58xx;
5492 struct cvmx_gmxx_tx_col_attempt_s cn58xxp1;
5493 struct cvmx_gmxx_tx_col_attempt_s cn61xx;
5494 struct cvmx_gmxx_tx_col_attempt_s cn63xx;
5495 struct cvmx_gmxx_tx_col_attempt_s cn63xxp1;
5496 struct cvmx_gmxx_tx_col_attempt_s cn66xx;
5497 struct cvmx_gmxx_tx_col_attempt_s cn68xx;
5498 struct cvmx_gmxx_tx_col_attempt_s cn68xxp1;
5499 struct cvmx_gmxx_tx_col_attempt_s cn70xx;
5500 struct cvmx_gmxx_tx_col_attempt_s cn70xxp1;
5501 struct cvmx_gmxx_tx_col_attempt_s cnf71xx;
5502};
5503
5504typedef union cvmx_gmxx_tx_col_attempt cvmx_gmxx_tx_col_attempt_t;
5505
5506/**
5507 * cvmx_gmx#_tx_corrupt
5508 *
5509 * GMX_TX_CORRUPT = TX - Corrupt TX packets with the ERR bit set
5510 *
5511 *
5512 * Notes:
5513 * Packets sent from PKO with the ERR wire asserted will be corrupted by
5514 * the transmitter if CORRUPT[prt] is set (XAUI uses prt==0).
5515 *
5516 * Corruption means that GMX will send a bad FCS value. If GMX_TX_APPEND[FCS]
5517 * is clear then no FCS is sent and the GMX cannot corrupt it. The corrupt FCS
5518 * value is 0xeeeeeeee for SGMII/1000Base-X and 4 bytes of the error
5519 * propagation code in XAUI mode.
5520 */
5521union cvmx_gmxx_tx_corrupt {
5522 u64 u64;
5523 struct cvmx_gmxx_tx_corrupt_s {
5524 u64 reserved_4_63 : 60;
5525 u64 corrupt : 4;
5526 } s;
5527 struct cvmx_gmxx_tx_corrupt_cn30xx {
5528 u64 reserved_3_63 : 61;
5529 u64 corrupt : 3;
5530 } cn30xx;
5531 struct cvmx_gmxx_tx_corrupt_cn30xx cn31xx;
5532 struct cvmx_gmxx_tx_corrupt_s cn38xx;
5533 struct cvmx_gmxx_tx_corrupt_s cn38xxp2;
5534 struct cvmx_gmxx_tx_corrupt_cn30xx cn50xx;
5535 struct cvmx_gmxx_tx_corrupt_s cn52xx;
5536 struct cvmx_gmxx_tx_corrupt_s cn52xxp1;
5537 struct cvmx_gmxx_tx_corrupt_s cn56xx;
5538 struct cvmx_gmxx_tx_corrupt_s cn56xxp1;
5539 struct cvmx_gmxx_tx_corrupt_s cn58xx;
5540 struct cvmx_gmxx_tx_corrupt_s cn58xxp1;
5541 struct cvmx_gmxx_tx_corrupt_s cn61xx;
5542 struct cvmx_gmxx_tx_corrupt_s cn63xx;
5543 struct cvmx_gmxx_tx_corrupt_s cn63xxp1;
5544 struct cvmx_gmxx_tx_corrupt_s cn66xx;
5545 struct cvmx_gmxx_tx_corrupt_s cn68xx;
5546 struct cvmx_gmxx_tx_corrupt_s cn68xxp1;
5547 struct cvmx_gmxx_tx_corrupt_s cn70xx;
5548 struct cvmx_gmxx_tx_corrupt_s cn70xxp1;
5549 struct cvmx_gmxx_tx_corrupt_cnf71xx {
5550 u64 reserved_2_63 : 62;
5551 u64 corrupt : 2;
5552 } cnf71xx;
5553};
5554
5555typedef union cvmx_gmxx_tx_corrupt cvmx_gmxx_tx_corrupt_t;
5556
5557/**
5558 * cvmx_gmx#_tx_hg2_reg1
5559 *
5560 * Notes:
5561 * The TX_XOF[15:0] field in GMX(0)_TX_HG2_REG1 and the TX_XON[15:0] field in
5562 * GMX(0)_TX_HG2_REG2 register map to the same 16 physical flops. When written with address of
5563 * GMX(0)_TX_HG2_REG1, it will exhibit write 1 to set behavior and when written with address of
5564 * GMX(0)_TX_HG2_REG2, it will exhibit write 1 to clear behavior.
5565 * For reads, either address will return the $GMX(0)_TX_HG2_REG1 values.
5566 */
5567union cvmx_gmxx_tx_hg2_reg1 {
5568 u64 u64;
5569 struct cvmx_gmxx_tx_hg2_reg1_s {
5570 u64 reserved_16_63 : 48;
5571 u64 tx_xof : 16;
5572 } s;
5573 struct cvmx_gmxx_tx_hg2_reg1_s cn52xx;
5574 struct cvmx_gmxx_tx_hg2_reg1_s cn52xxp1;
5575 struct cvmx_gmxx_tx_hg2_reg1_s cn56xx;
5576 struct cvmx_gmxx_tx_hg2_reg1_s cn61xx;
5577 struct cvmx_gmxx_tx_hg2_reg1_s cn63xx;
5578 struct cvmx_gmxx_tx_hg2_reg1_s cn63xxp1;
5579 struct cvmx_gmxx_tx_hg2_reg1_s cn66xx;
5580 struct cvmx_gmxx_tx_hg2_reg1_s cn68xx;
5581 struct cvmx_gmxx_tx_hg2_reg1_s cn68xxp1;
5582 struct cvmx_gmxx_tx_hg2_reg1_s cn70xx;
5583 struct cvmx_gmxx_tx_hg2_reg1_s cn70xxp1;
5584 struct cvmx_gmxx_tx_hg2_reg1_s cnf71xx;
5585};
5586
5587typedef union cvmx_gmxx_tx_hg2_reg1 cvmx_gmxx_tx_hg2_reg1_t;
5588
5589/**
5590 * cvmx_gmx#_tx_hg2_reg2
5591 *
5592 * Notes:
5593 * The TX_XOF[15:0] field in GMX(0)_TX_HG2_REG1 and the TX_XON[15:0] field in
5594 * GMX(0)_TX_HG2_REG2 register map to the same 16 physical flops. When written with address of
5595 * GMX(0)_TX_HG2_REG1, it will exhibit write 1 to set behavior and when written with address of
5596 * GMX(0)_TX_HG2_REG2, it will exhibit write 1 to clear behavior.
5597 * For reads, either address will return the $GMX(0)_TX_HG2_REG1 values.
5598 */
5599union cvmx_gmxx_tx_hg2_reg2 {
5600 u64 u64;
5601 struct cvmx_gmxx_tx_hg2_reg2_s {
5602 u64 reserved_16_63 : 48;
5603 u64 tx_xon : 16;
5604 } s;
5605 struct cvmx_gmxx_tx_hg2_reg2_s cn52xx;
5606 struct cvmx_gmxx_tx_hg2_reg2_s cn52xxp1;
5607 struct cvmx_gmxx_tx_hg2_reg2_s cn56xx;
5608 struct cvmx_gmxx_tx_hg2_reg2_s cn61xx;
5609 struct cvmx_gmxx_tx_hg2_reg2_s cn63xx;
5610 struct cvmx_gmxx_tx_hg2_reg2_s cn63xxp1;
5611 struct cvmx_gmxx_tx_hg2_reg2_s cn66xx;
5612 struct cvmx_gmxx_tx_hg2_reg2_s cn68xx;
5613 struct cvmx_gmxx_tx_hg2_reg2_s cn68xxp1;
5614 struct cvmx_gmxx_tx_hg2_reg2_s cn70xx;
5615 struct cvmx_gmxx_tx_hg2_reg2_s cn70xxp1;
5616 struct cvmx_gmxx_tx_hg2_reg2_s cnf71xx;
5617};
5618
5619typedef union cvmx_gmxx_tx_hg2_reg2 cvmx_gmxx_tx_hg2_reg2_t;
5620
5621/**
5622 * cvmx_gmx#_tx_ifg
5623 *
5624 * GMX_TX_IFG = Packet TX Interframe Gap
5625 *
5626 *
5627 * Notes:
5628 * * Programming IFG1 and IFG2.
5629 *
5630 * For 10/100/1000Mbs half-duplex systems that require IEEE 802.3
5631 * compatibility, IFG1 must be in the range of 1-8, IFG2 must be in the range
5632 * of 4-12, and the IFG1+IFG2 sum must be 12.
5633 *
5634 * For 10/100/1000Mbs full-duplex systems that require IEEE 802.3
5635 * compatibility, IFG1 must be in the range of 1-11, IFG2 must be in the range
5636 * of 1-11, and the IFG1+IFG2 sum must be 12.
5637 *
5638 * For XAUI/10Gbs systems that require IEEE 802.3 compatibility, the
5639 * IFG1+IFG2 sum must be 12. IFG1[1:0] and IFG2[1:0] must be zero.
5640 *
5641 * For all other systems, IFG1 and IFG2 can be any value in the range of
5642 * 1-15. Allowing for a total possible IFG sum of 2-30.
5643 */
5644union cvmx_gmxx_tx_ifg {
5645 u64 u64;
5646 struct cvmx_gmxx_tx_ifg_s {
5647 u64 reserved_8_63 : 56;
5648 u64 ifg2 : 4;
5649 u64 ifg1 : 4;
5650 } s;
5651 struct cvmx_gmxx_tx_ifg_s cn30xx;
5652 struct cvmx_gmxx_tx_ifg_s cn31xx;
5653 struct cvmx_gmxx_tx_ifg_s cn38xx;
5654 struct cvmx_gmxx_tx_ifg_s cn38xxp2;
5655 struct cvmx_gmxx_tx_ifg_s cn50xx;
5656 struct cvmx_gmxx_tx_ifg_s cn52xx;
5657 struct cvmx_gmxx_tx_ifg_s cn52xxp1;
5658 struct cvmx_gmxx_tx_ifg_s cn56xx;
5659 struct cvmx_gmxx_tx_ifg_s cn56xxp1;
5660 struct cvmx_gmxx_tx_ifg_s cn58xx;
5661 struct cvmx_gmxx_tx_ifg_s cn58xxp1;
5662 struct cvmx_gmxx_tx_ifg_s cn61xx;
5663 struct cvmx_gmxx_tx_ifg_s cn63xx;
5664 struct cvmx_gmxx_tx_ifg_s cn63xxp1;
5665 struct cvmx_gmxx_tx_ifg_s cn66xx;
5666 struct cvmx_gmxx_tx_ifg_s cn68xx;
5667 struct cvmx_gmxx_tx_ifg_s cn68xxp1;
5668 struct cvmx_gmxx_tx_ifg_s cn70xx;
5669 struct cvmx_gmxx_tx_ifg_s cn70xxp1;
5670 struct cvmx_gmxx_tx_ifg_s cnf71xx;
5671};
5672
5673typedef union cvmx_gmxx_tx_ifg cvmx_gmxx_tx_ifg_t;
5674
5675/**
5676 * cvmx_gmx#_tx_int_en
5677 *
5678 * GMX_TX_INT_EN = Interrupt Enable
5679 *
5680 *
5681 * Notes:
5682 * In XAUI mode, only the lsb (corresponding to port0) of UNDFLW is used.
5683 *
5684 */
5685union cvmx_gmxx_tx_int_en {
5686 u64 u64;
5687 struct cvmx_gmxx_tx_int_en_s {
5688 u64 reserved_25_63 : 39;
5689 u64 xchange : 1;
5690 u64 ptp_lost : 4;
5691 u64 late_col : 4;
5692 u64 xsdef : 4;
5693 u64 xscol : 4;
5694 u64 reserved_6_7 : 2;
5695 u64 undflw : 4;
5696 u64 reserved_1_1 : 1;
5697 u64 pko_nxa : 1;
5698 } s;
5699 struct cvmx_gmxx_tx_int_en_cn30xx {
5700 u64 reserved_19_63 : 45;
5701 u64 late_col : 3;
5702 u64 reserved_15_15 : 1;
5703 u64 xsdef : 3;
5704 u64 reserved_11_11 : 1;
5705 u64 xscol : 3;
5706 u64 reserved_5_7 : 3;
5707 u64 undflw : 3;
5708 u64 reserved_1_1 : 1;
5709 u64 pko_nxa : 1;
5710 } cn30xx;
5711 struct cvmx_gmxx_tx_int_en_cn31xx {
5712 u64 reserved_15_63 : 49;
5713 u64 xsdef : 3;
5714 u64 reserved_11_11 : 1;
5715 u64 xscol : 3;
5716 u64 reserved_5_7 : 3;
5717 u64 undflw : 3;
5718 u64 reserved_1_1 : 1;
5719 u64 pko_nxa : 1;
5720 } cn31xx;
5721 struct cvmx_gmxx_tx_int_en_cn38xx {
5722 u64 reserved_20_63 : 44;
5723 u64 late_col : 4;
5724 u64 xsdef : 4;
5725 u64 xscol : 4;
5726 u64 reserved_6_7 : 2;
5727 u64 undflw : 4;
5728 u64 ncb_nxa : 1;
5729 u64 pko_nxa : 1;
5730 } cn38xx;
5731 struct cvmx_gmxx_tx_int_en_cn38xxp2 {
5732 u64 reserved_16_63 : 48;
5733 u64 xsdef : 4;
5734 u64 xscol : 4;
5735 u64 reserved_6_7 : 2;
5736 u64 undflw : 4;
5737 u64 ncb_nxa : 1;
5738 u64 pko_nxa : 1;
5739 } cn38xxp2;
5740 struct cvmx_gmxx_tx_int_en_cn30xx cn50xx;
5741 struct cvmx_gmxx_tx_int_en_cn52xx {
5742 u64 reserved_20_63 : 44;
5743 u64 late_col : 4;
5744 u64 xsdef : 4;
5745 u64 xscol : 4;
5746 u64 reserved_6_7 : 2;
5747 u64 undflw : 4;
5748 u64 reserved_1_1 : 1;
5749 u64 pko_nxa : 1;
5750 } cn52xx;
5751 struct cvmx_gmxx_tx_int_en_cn52xx cn52xxp1;
5752 struct cvmx_gmxx_tx_int_en_cn52xx cn56xx;
5753 struct cvmx_gmxx_tx_int_en_cn52xx cn56xxp1;
5754 struct cvmx_gmxx_tx_int_en_cn38xx cn58xx;
5755 struct cvmx_gmxx_tx_int_en_cn38xx cn58xxp1;
5756 struct cvmx_gmxx_tx_int_en_s cn61xx;
5757 struct cvmx_gmxx_tx_int_en_cn63xx {
5758 u64 reserved_24_63 : 40;
5759 u64 ptp_lost : 4;
5760 u64 late_col : 4;
5761 u64 xsdef : 4;
5762 u64 xscol : 4;
5763 u64 reserved_6_7 : 2;
5764 u64 undflw : 4;
5765 u64 reserved_1_1 : 1;
5766 u64 pko_nxa : 1;
5767 } cn63xx;
5768 struct cvmx_gmxx_tx_int_en_cn63xx cn63xxp1;
5769 struct cvmx_gmxx_tx_int_en_s cn66xx;
5770 struct cvmx_gmxx_tx_int_en_cn68xx {
5771 u64 reserved_25_63 : 39;
5772 u64 xchange : 1;
5773 u64 ptp_lost : 4;
5774 u64 late_col : 4;
5775 u64 xsdef : 4;
5776 u64 xscol : 4;
5777 u64 reserved_6_7 : 2;
5778 u64 undflw : 4;
5779 u64 pko_nxp : 1;
5780 u64 pko_nxa : 1;
5781 } cn68xx;
5782 struct cvmx_gmxx_tx_int_en_cn68xx cn68xxp1;
5783 struct cvmx_gmxx_tx_int_en_s cn70xx;
5784 struct cvmx_gmxx_tx_int_en_s cn70xxp1;
5785 struct cvmx_gmxx_tx_int_en_cnf71xx {
5786 u64 reserved_25_63 : 39;
5787 u64 xchange : 1;
5788 u64 reserved_22_23 : 2;
5789 u64 ptp_lost : 2;
5790 u64 reserved_18_19 : 2;
5791 u64 late_col : 2;
5792 u64 reserved_14_15 : 2;
5793 u64 xsdef : 2;
5794 u64 reserved_10_11 : 2;
5795 u64 xscol : 2;
5796 u64 reserved_4_7 : 4;
5797 u64 undflw : 2;
5798 u64 reserved_1_1 : 1;
5799 u64 pko_nxa : 1;
5800 } cnf71xx;
5801};
5802
5803typedef union cvmx_gmxx_tx_int_en cvmx_gmxx_tx_int_en_t;
5804
5805/**
5806 * cvmx_gmx#_tx_int_reg
5807 *
5808 * GMX_TX_INT_REG = Interrupt Register
5809 *
5810 *
5811 * Notes:
5812 * In XAUI mode, only the lsb (corresponding to port0) of UNDFLW is used.
5813 *
5814 */
5815union cvmx_gmxx_tx_int_reg {
5816 u64 u64;
5817 struct cvmx_gmxx_tx_int_reg_s {
5818 u64 reserved_25_63 : 39;
5819 u64 xchange : 1;
5820 u64 ptp_lost : 4;
5821 u64 late_col : 4;
5822 u64 xsdef : 4;
5823 u64 xscol : 4;
5824 u64 reserved_6_7 : 2;
5825 u64 undflw : 4;
5826 u64 reserved_1_1 : 1;
5827 u64 pko_nxa : 1;
5828 } s;
5829 struct cvmx_gmxx_tx_int_reg_cn30xx {
5830 u64 reserved_19_63 : 45;
5831 u64 late_col : 3;
5832 u64 reserved_15_15 : 1;
5833 u64 xsdef : 3;
5834 u64 reserved_11_11 : 1;
5835 u64 xscol : 3;
5836 u64 reserved_5_7 : 3;
5837 u64 undflw : 3;
5838 u64 reserved_1_1 : 1;
5839 u64 pko_nxa : 1;
5840 } cn30xx;
5841 struct cvmx_gmxx_tx_int_reg_cn31xx {
5842 u64 reserved_15_63 : 49;
5843 u64 xsdef : 3;
5844 u64 reserved_11_11 : 1;
5845 u64 xscol : 3;
5846 u64 reserved_5_7 : 3;
5847 u64 undflw : 3;
5848 u64 reserved_1_1 : 1;
5849 u64 pko_nxa : 1;
5850 } cn31xx;
5851 struct cvmx_gmxx_tx_int_reg_cn38xx {
5852 u64 reserved_20_63 : 44;
5853 u64 late_col : 4;
5854 u64 xsdef : 4;
5855 u64 xscol : 4;
5856 u64 reserved_6_7 : 2;
5857 u64 undflw : 4;
5858 u64 ncb_nxa : 1;
5859 u64 pko_nxa : 1;
5860 } cn38xx;
5861 struct cvmx_gmxx_tx_int_reg_cn38xxp2 {
5862 u64 reserved_16_63 : 48;
5863 u64 xsdef : 4;
5864 u64 xscol : 4;
5865 u64 reserved_6_7 : 2;
5866 u64 undflw : 4;
5867 u64 ncb_nxa : 1;
5868 u64 pko_nxa : 1;
5869 } cn38xxp2;
5870 struct cvmx_gmxx_tx_int_reg_cn30xx cn50xx;
5871 struct cvmx_gmxx_tx_int_reg_cn52xx {
5872 u64 reserved_20_63 : 44;
5873 u64 late_col : 4;
5874 u64 xsdef : 4;
5875 u64 xscol : 4;
5876 u64 reserved_6_7 : 2;
5877 u64 undflw : 4;
5878 u64 reserved_1_1 : 1;
5879 u64 pko_nxa : 1;
5880 } cn52xx;
5881 struct cvmx_gmxx_tx_int_reg_cn52xx cn52xxp1;
5882 struct cvmx_gmxx_tx_int_reg_cn52xx cn56xx;
5883 struct cvmx_gmxx_tx_int_reg_cn52xx cn56xxp1;
5884 struct cvmx_gmxx_tx_int_reg_cn38xx cn58xx;
5885 struct cvmx_gmxx_tx_int_reg_cn38xx cn58xxp1;
5886 struct cvmx_gmxx_tx_int_reg_s cn61xx;
5887 struct cvmx_gmxx_tx_int_reg_cn63xx {
5888 u64 reserved_24_63 : 40;
5889 u64 ptp_lost : 4;
5890 u64 late_col : 4;
5891 u64 xsdef : 4;
5892 u64 xscol : 4;
5893 u64 reserved_6_7 : 2;
5894 u64 undflw : 4;
5895 u64 reserved_1_1 : 1;
5896 u64 pko_nxa : 1;
5897 } cn63xx;
5898 struct cvmx_gmxx_tx_int_reg_cn63xx cn63xxp1;
5899 struct cvmx_gmxx_tx_int_reg_s cn66xx;
5900 struct cvmx_gmxx_tx_int_reg_cn68xx {
5901 u64 reserved_25_63 : 39;
5902 u64 xchange : 1;
5903 u64 ptp_lost : 4;
5904 u64 late_col : 4;
5905 u64 xsdef : 4;
5906 u64 xscol : 4;
5907 u64 reserved_6_7 : 2;
5908 u64 undflw : 4;
5909 u64 pko_nxp : 1;
5910 u64 pko_nxa : 1;
5911 } cn68xx;
5912 struct cvmx_gmxx_tx_int_reg_cn68xx cn68xxp1;
5913 struct cvmx_gmxx_tx_int_reg_s cn70xx;
5914 struct cvmx_gmxx_tx_int_reg_s cn70xxp1;
5915 struct cvmx_gmxx_tx_int_reg_cnf71xx {
5916 u64 reserved_25_63 : 39;
5917 u64 xchange : 1;
5918 u64 reserved_22_23 : 2;
5919 u64 ptp_lost : 2;
5920 u64 reserved_18_19 : 2;
5921 u64 late_col : 2;
5922 u64 reserved_14_15 : 2;
5923 u64 xsdef : 2;
5924 u64 reserved_10_11 : 2;
5925 u64 xscol : 2;
5926 u64 reserved_4_7 : 4;
5927 u64 undflw : 2;
5928 u64 reserved_1_1 : 1;
5929 u64 pko_nxa : 1;
5930 } cnf71xx;
5931};
5932
5933typedef union cvmx_gmxx_tx_int_reg cvmx_gmxx_tx_int_reg_t;
5934
5935/**
5936 * cvmx_gmx#_tx_jam
5937 *
5938 * GMX_TX_JAM = Packet TX Jam Pattern
5939 *
5940 */
5941union cvmx_gmxx_tx_jam {
5942 u64 u64;
5943 struct cvmx_gmxx_tx_jam_s {
5944 u64 reserved_8_63 : 56;
5945 u64 jam : 8;
5946 } s;
5947 struct cvmx_gmxx_tx_jam_s cn30xx;
5948 struct cvmx_gmxx_tx_jam_s cn31xx;
5949 struct cvmx_gmxx_tx_jam_s cn38xx;
5950 struct cvmx_gmxx_tx_jam_s cn38xxp2;
5951 struct cvmx_gmxx_tx_jam_s cn50xx;
5952 struct cvmx_gmxx_tx_jam_s cn52xx;
5953 struct cvmx_gmxx_tx_jam_s cn52xxp1;
5954 struct cvmx_gmxx_tx_jam_s cn56xx;
5955 struct cvmx_gmxx_tx_jam_s cn56xxp1;
5956 struct cvmx_gmxx_tx_jam_s cn58xx;
5957 struct cvmx_gmxx_tx_jam_s cn58xxp1;
5958 struct cvmx_gmxx_tx_jam_s cn61xx;
5959 struct cvmx_gmxx_tx_jam_s cn63xx;
5960 struct cvmx_gmxx_tx_jam_s cn63xxp1;
5961 struct cvmx_gmxx_tx_jam_s cn66xx;
5962 struct cvmx_gmxx_tx_jam_s cn68xx;
5963 struct cvmx_gmxx_tx_jam_s cn68xxp1;
5964 struct cvmx_gmxx_tx_jam_s cn70xx;
5965 struct cvmx_gmxx_tx_jam_s cn70xxp1;
5966 struct cvmx_gmxx_tx_jam_s cnf71xx;
5967};
5968
5969typedef union cvmx_gmxx_tx_jam cvmx_gmxx_tx_jam_t;
5970
5971/**
5972 * cvmx_gmx#_tx_lfsr
5973 *
5974 * GMX_TX_LFSR = LFSR used to implement truncated binary exponential backoff
5975 *
5976 */
5977union cvmx_gmxx_tx_lfsr {
5978 u64 u64;
5979 struct cvmx_gmxx_tx_lfsr_s {
5980 u64 reserved_16_63 : 48;
5981 u64 lfsr : 16;
5982 } s;
5983 struct cvmx_gmxx_tx_lfsr_s cn30xx;
5984 struct cvmx_gmxx_tx_lfsr_s cn31xx;
5985 struct cvmx_gmxx_tx_lfsr_s cn38xx;
5986 struct cvmx_gmxx_tx_lfsr_s cn38xxp2;
5987 struct cvmx_gmxx_tx_lfsr_s cn50xx;
5988 struct cvmx_gmxx_tx_lfsr_s cn52xx;
5989 struct cvmx_gmxx_tx_lfsr_s cn52xxp1;
5990 struct cvmx_gmxx_tx_lfsr_s cn56xx;
5991 struct cvmx_gmxx_tx_lfsr_s cn56xxp1;
5992 struct cvmx_gmxx_tx_lfsr_s cn58xx;
5993 struct cvmx_gmxx_tx_lfsr_s cn58xxp1;
5994 struct cvmx_gmxx_tx_lfsr_s cn61xx;
5995 struct cvmx_gmxx_tx_lfsr_s cn63xx;
5996 struct cvmx_gmxx_tx_lfsr_s cn63xxp1;
5997 struct cvmx_gmxx_tx_lfsr_s cn66xx;
5998 struct cvmx_gmxx_tx_lfsr_s cn68xx;
5999 struct cvmx_gmxx_tx_lfsr_s cn68xxp1;
6000 struct cvmx_gmxx_tx_lfsr_s cn70xx;
6001 struct cvmx_gmxx_tx_lfsr_s cn70xxp1;
6002 struct cvmx_gmxx_tx_lfsr_s cnf71xx;
6003};
6004
6005typedef union cvmx_gmxx_tx_lfsr cvmx_gmxx_tx_lfsr_t;
6006
6007/**
6008 * cvmx_gmx#_tx_ovr_bp
6009 *
6010 * GMX_TX_OVR_BP = Packet Interface TX Override BackPressure
6011 *
6012 *
6013 * Notes:
6014 * In XAUI mode, only the lsb (corresponding to port0) of EN, BP, and IGN_FULL are used.
6015 *
6016 * GMX*_TX_OVR_BP[EN<0>] must be set to one and GMX*_TX_OVR_BP[BP<0>] must be cleared to zero
6017 * (to forcibly disable HW-automatic 802.3 pause packet generation) with the HiGig2 Protocol
6018 * when GMX*_HG2_CONTROL[HG2TX_EN]=0. (The HiGig2 protocol is indicated by
6019 * GMX*_TX_XAUI_CTL[HG_EN]=1 and GMX*_RX0_UDD_SKP[LEN]=16.) HW can only auto-generate backpressure
6020 * through HiGig2 messages (optionally, when GMX*_HG2_CONTROL[HG2TX_EN]=1) with the HiGig2
6021 * protocol.
6022 */
6023union cvmx_gmxx_tx_ovr_bp {
6024 u64 u64;
6025 struct cvmx_gmxx_tx_ovr_bp_s {
6026 u64 reserved_48_63 : 16;
6027 u64 tx_prt_bp : 16;
6028 u64 reserved_12_31 : 20;
6029 u64 en : 4;
6030 u64 bp : 4;
6031 u64 ign_full : 4;
6032 } s;
6033 struct cvmx_gmxx_tx_ovr_bp_cn30xx {
6034 u64 reserved_11_63 : 53;
6035 u64 en : 3;
6036 u64 reserved_7_7 : 1;
6037 u64 bp : 3;
6038 u64 reserved_3_3 : 1;
6039 u64 ign_full : 3;
6040 } cn30xx;
6041 struct cvmx_gmxx_tx_ovr_bp_cn30xx cn31xx;
6042 struct cvmx_gmxx_tx_ovr_bp_cn38xx {
6043 u64 reserved_12_63 : 52;
6044 u64 en : 4;
6045 u64 bp : 4;
6046 u64 ign_full : 4;
6047 } cn38xx;
6048 struct cvmx_gmxx_tx_ovr_bp_cn38xx cn38xxp2;
6049 struct cvmx_gmxx_tx_ovr_bp_cn30xx cn50xx;
6050 struct cvmx_gmxx_tx_ovr_bp_s cn52xx;
6051 struct cvmx_gmxx_tx_ovr_bp_s cn52xxp1;
6052 struct cvmx_gmxx_tx_ovr_bp_s cn56xx;
6053 struct cvmx_gmxx_tx_ovr_bp_s cn56xxp1;
6054 struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xx;
6055 struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xxp1;
6056 struct cvmx_gmxx_tx_ovr_bp_s cn61xx;
6057 struct cvmx_gmxx_tx_ovr_bp_s cn63xx;
6058 struct cvmx_gmxx_tx_ovr_bp_s cn63xxp1;
6059 struct cvmx_gmxx_tx_ovr_bp_s cn66xx;
6060 struct cvmx_gmxx_tx_ovr_bp_s cn68xx;
6061 struct cvmx_gmxx_tx_ovr_bp_s cn68xxp1;
6062 struct cvmx_gmxx_tx_ovr_bp_s cn70xx;
6063 struct cvmx_gmxx_tx_ovr_bp_s cn70xxp1;
6064 struct cvmx_gmxx_tx_ovr_bp_cnf71xx {
6065 u64 reserved_48_63 : 16;
6066 u64 tx_prt_bp : 16;
6067 u64 reserved_10_31 : 22;
6068 u64 en : 2;
6069 u64 reserved_6_7 : 2;
6070 u64 bp : 2;
6071 u64 reserved_2_3 : 2;
6072 u64 ign_full : 2;
6073 } cnf71xx;
6074};
6075
6076typedef union cvmx_gmxx_tx_ovr_bp cvmx_gmxx_tx_ovr_bp_t;
6077
6078/**
6079 * cvmx_gmx#_tx_pause_pkt_dmac
6080 *
6081 * GMX_TX_PAUSE_PKT_DMAC = Packet TX Pause Packet DMAC field
6082 *
6083 */
6084union cvmx_gmxx_tx_pause_pkt_dmac {
6085 u64 u64;
6086 struct cvmx_gmxx_tx_pause_pkt_dmac_s {
6087 u64 reserved_48_63 : 16;
6088 u64 dmac : 48;
6089 } s;
6090 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn30xx;
6091 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn31xx;
6092 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xx;
6093 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xxp2;
6094 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn50xx;
6095 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xx;
6096 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xxp1;
6097 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xx;
6098 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xxp1;
6099 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xx;
6100 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xxp1;
6101 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn61xx;
6102 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn63xx;
6103 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn63xxp1;
6104 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn66xx;
6105 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn68xx;
6106 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn68xxp1;
6107 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn70xx;
6108 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn70xxp1;
6109 struct cvmx_gmxx_tx_pause_pkt_dmac_s cnf71xx;
6110};
6111
6112typedef union cvmx_gmxx_tx_pause_pkt_dmac cvmx_gmxx_tx_pause_pkt_dmac_t;
6113
6114/**
6115 * cvmx_gmx#_tx_pause_pkt_type
6116 *
6117 * GMX_TX_PAUSE_PKT_TYPE = Packet Interface TX Pause Packet TYPE field
6118 *
6119 */
6120union cvmx_gmxx_tx_pause_pkt_type {
6121 u64 u64;
6122 struct cvmx_gmxx_tx_pause_pkt_type_s {
6123 u64 reserved_16_63 : 48;
6124 u64 type : 16;
6125 } s;
6126 struct cvmx_gmxx_tx_pause_pkt_type_s cn30xx;
6127 struct cvmx_gmxx_tx_pause_pkt_type_s cn31xx;
6128 struct cvmx_gmxx_tx_pause_pkt_type_s cn38xx;
6129 struct cvmx_gmxx_tx_pause_pkt_type_s cn38xxp2;
6130 struct cvmx_gmxx_tx_pause_pkt_type_s cn50xx;
6131 struct cvmx_gmxx_tx_pause_pkt_type_s cn52xx;
6132 struct cvmx_gmxx_tx_pause_pkt_type_s cn52xxp1;
6133 struct cvmx_gmxx_tx_pause_pkt_type_s cn56xx;
6134 struct cvmx_gmxx_tx_pause_pkt_type_s cn56xxp1;
6135 struct cvmx_gmxx_tx_pause_pkt_type_s cn58xx;
6136 struct cvmx_gmxx_tx_pause_pkt_type_s cn58xxp1;
6137 struct cvmx_gmxx_tx_pause_pkt_type_s cn61xx;
6138 struct cvmx_gmxx_tx_pause_pkt_type_s cn63xx;
6139 struct cvmx_gmxx_tx_pause_pkt_type_s cn63xxp1;
6140 struct cvmx_gmxx_tx_pause_pkt_type_s cn66xx;
6141 struct cvmx_gmxx_tx_pause_pkt_type_s cn68xx;
6142 struct cvmx_gmxx_tx_pause_pkt_type_s cn68xxp1;
6143 struct cvmx_gmxx_tx_pause_pkt_type_s cn70xx;
6144 struct cvmx_gmxx_tx_pause_pkt_type_s cn70xxp1;
6145 struct cvmx_gmxx_tx_pause_pkt_type_s cnf71xx;
6146};
6147
6148typedef union cvmx_gmxx_tx_pause_pkt_type cvmx_gmxx_tx_pause_pkt_type_t;
6149
6150/**
6151 * cvmx_gmx#_tx_prts
6152 *
6153 * Common
6154 * GMX_TX_PRTS = TX Ports
6155 */
6156union cvmx_gmxx_tx_prts {
6157 u64 u64;
6158 struct cvmx_gmxx_tx_prts_s {
6159 u64 reserved_5_63 : 59;
6160 u64 prts : 5;
6161 } s;
6162 struct cvmx_gmxx_tx_prts_s cn30xx;
6163 struct cvmx_gmxx_tx_prts_s cn31xx;
6164 struct cvmx_gmxx_tx_prts_s cn38xx;
6165 struct cvmx_gmxx_tx_prts_s cn38xxp2;
6166 struct cvmx_gmxx_tx_prts_s cn50xx;
6167 struct cvmx_gmxx_tx_prts_s cn52xx;
6168 struct cvmx_gmxx_tx_prts_s cn52xxp1;
6169 struct cvmx_gmxx_tx_prts_s cn56xx;
6170 struct cvmx_gmxx_tx_prts_s cn56xxp1;
6171 struct cvmx_gmxx_tx_prts_s cn58xx;
6172 struct cvmx_gmxx_tx_prts_s cn58xxp1;
6173 struct cvmx_gmxx_tx_prts_s cn61xx;
6174 struct cvmx_gmxx_tx_prts_s cn63xx;
6175 struct cvmx_gmxx_tx_prts_s cn63xxp1;
6176 struct cvmx_gmxx_tx_prts_s cn66xx;
6177 struct cvmx_gmxx_tx_prts_s cn68xx;
6178 struct cvmx_gmxx_tx_prts_s cn68xxp1;
6179 struct cvmx_gmxx_tx_prts_s cn70xx;
6180 struct cvmx_gmxx_tx_prts_s cn70xxp1;
6181 struct cvmx_gmxx_tx_prts_s cnf71xx;
6182};
6183
6184typedef union cvmx_gmxx_tx_prts cvmx_gmxx_tx_prts_t;
6185
6186/**
6187 * cvmx_gmx#_tx_spi_ctl
6188 *
6189 * GMX_TX_SPI_CTL = Spi4 TX ModesSpi4
6190 *
6191 */
6192union cvmx_gmxx_tx_spi_ctl {
6193 u64 u64;
6194 struct cvmx_gmxx_tx_spi_ctl_s {
6195 u64 reserved_2_63 : 62;
6196 u64 tpa_clr : 1;
6197 u64 cont_pkt : 1;
6198 } s;
6199 struct cvmx_gmxx_tx_spi_ctl_s cn38xx;
6200 struct cvmx_gmxx_tx_spi_ctl_s cn38xxp2;
6201 struct cvmx_gmxx_tx_spi_ctl_s cn58xx;
6202 struct cvmx_gmxx_tx_spi_ctl_s cn58xxp1;
6203};
6204
6205typedef union cvmx_gmxx_tx_spi_ctl cvmx_gmxx_tx_spi_ctl_t;
6206
6207/**
6208 * cvmx_gmx#_tx_spi_drain
6209 *
6210 * GMX_TX_SPI_DRAIN = Drain out Spi TX FIFO
6211 *
6212 */
6213union cvmx_gmxx_tx_spi_drain {
6214 u64 u64;
6215 struct cvmx_gmxx_tx_spi_drain_s {
6216 u64 reserved_16_63 : 48;
6217 u64 drain : 16;
6218 } s;
6219 struct cvmx_gmxx_tx_spi_drain_s cn38xx;
6220 struct cvmx_gmxx_tx_spi_drain_s cn58xx;
6221 struct cvmx_gmxx_tx_spi_drain_s cn58xxp1;
6222};
6223
6224typedef union cvmx_gmxx_tx_spi_drain cvmx_gmxx_tx_spi_drain_t;
6225
6226/**
6227 * cvmx_gmx#_tx_spi_max
6228 *
6229 * GMX_TX_SPI_MAX = RGMII TX Spi4 MAX
6230 *
6231 */
6232union cvmx_gmxx_tx_spi_max {
6233 u64 u64;
6234 struct cvmx_gmxx_tx_spi_max_s {
6235 u64 reserved_23_63 : 41;
6236 u64 slice : 7;
6237 u64 max2 : 8;
6238 u64 max1 : 8;
6239 } s;
6240 struct cvmx_gmxx_tx_spi_max_cn38xx {
6241 u64 reserved_16_63 : 48;
6242 u64 max2 : 8;
6243 u64 max1 : 8;
6244 } cn38xx;
6245 struct cvmx_gmxx_tx_spi_max_cn38xx cn38xxp2;
6246 struct cvmx_gmxx_tx_spi_max_s cn58xx;
6247 struct cvmx_gmxx_tx_spi_max_s cn58xxp1;
6248};
6249
6250typedef union cvmx_gmxx_tx_spi_max cvmx_gmxx_tx_spi_max_t;
6251
6252/**
6253 * cvmx_gmx#_tx_spi_round#
6254 *
6255 * GMX_TX_SPI_ROUND = Controls SPI4 TX Arbitration
6256 *
6257 */
6258union cvmx_gmxx_tx_spi_roundx {
6259 u64 u64;
6260 struct cvmx_gmxx_tx_spi_roundx_s {
6261 u64 reserved_16_63 : 48;
6262 u64 round : 16;
6263 } s;
6264 struct cvmx_gmxx_tx_spi_roundx_s cn58xx;
6265 struct cvmx_gmxx_tx_spi_roundx_s cn58xxp1;
6266};
6267
6268typedef union cvmx_gmxx_tx_spi_roundx cvmx_gmxx_tx_spi_roundx_t;
6269
6270/**
6271 * cvmx_gmx#_tx_spi_thresh
6272 *
6273 * GMX_TX_SPI_THRESH = RGMII TX Spi4 Transmit Threshold
6274 *
6275 *
6276 * Notes:
6277 * Note: zero will map to 0x20
6278 *
6279 * This will normally creates Spi4 traffic bursts at least THRESH in length.
6280 * If dclk > eclk, then this rule may not always hold and Octeon may split
6281 * transfers into smaller bursts - some of which could be as short as 16B.
6282 * Octeon will never violate the Spi4.2 spec and send a non-EOP burst that is
6283 * not a multiple of 16B.
6284 */
6285union cvmx_gmxx_tx_spi_thresh {
6286 u64 u64;
6287 struct cvmx_gmxx_tx_spi_thresh_s {
6288 u64 reserved_6_63 : 58;
6289 u64 thresh : 6;
6290 } s;
6291 struct cvmx_gmxx_tx_spi_thresh_s cn38xx;
6292 struct cvmx_gmxx_tx_spi_thresh_s cn38xxp2;
6293 struct cvmx_gmxx_tx_spi_thresh_s cn58xx;
6294 struct cvmx_gmxx_tx_spi_thresh_s cn58xxp1;
6295};
6296
6297typedef union cvmx_gmxx_tx_spi_thresh cvmx_gmxx_tx_spi_thresh_t;
6298
6299/**
6300 * cvmx_gmx#_tx_xaui_ctl
6301 */
6302union cvmx_gmxx_tx_xaui_ctl {
6303 u64 u64;
6304 struct cvmx_gmxx_tx_xaui_ctl_s {
6305 u64 reserved_11_63 : 53;
6306 u64 hg_pause_hgi : 2;
6307 u64 hg_en : 1;
6308 u64 reserved_7_7 : 1;
6309 u64 ls_byp : 1;
6310 u64 ls : 2;
6311 u64 reserved_2_3 : 2;
6312 u64 uni_en : 1;
6313 u64 dic_en : 1;
6314 } s;
6315 struct cvmx_gmxx_tx_xaui_ctl_s cn52xx;
6316 struct cvmx_gmxx_tx_xaui_ctl_s cn52xxp1;
6317 struct cvmx_gmxx_tx_xaui_ctl_s cn56xx;
6318 struct cvmx_gmxx_tx_xaui_ctl_s cn56xxp1;
6319 struct cvmx_gmxx_tx_xaui_ctl_s cn61xx;
6320 struct cvmx_gmxx_tx_xaui_ctl_s cn63xx;
6321 struct cvmx_gmxx_tx_xaui_ctl_s cn63xxp1;
6322 struct cvmx_gmxx_tx_xaui_ctl_s cn66xx;
6323 struct cvmx_gmxx_tx_xaui_ctl_s cn68xx;
6324 struct cvmx_gmxx_tx_xaui_ctl_s cn68xxp1;
6325 struct cvmx_gmxx_tx_xaui_ctl_s cn70xx;
6326 struct cvmx_gmxx_tx_xaui_ctl_s cn70xxp1;
6327 struct cvmx_gmxx_tx_xaui_ctl_s cnf71xx;
6328};
6329
6330typedef union cvmx_gmxx_tx_xaui_ctl cvmx_gmxx_tx_xaui_ctl_t;
6331
6332/**
6333 * cvmx_gmx#_wol_ctl
6334 */
6335union cvmx_gmxx_wol_ctl {
6336 u64 u64;
6337 struct cvmx_gmxx_wol_ctl_s {
6338 u64 reserved_36_63 : 28;
6339 u64 magic_en : 4;
6340 u64 reserved_20_31 : 12;
6341 u64 direct_en : 4;
6342 u64 reserved_1_15 : 15;
6343 u64 en : 1;
6344 } s;
6345 struct cvmx_gmxx_wol_ctl_s cn70xx;
6346 struct cvmx_gmxx_wol_ctl_s cn70xxp1;
6347};
6348
6349typedef union cvmx_gmxx_wol_ctl cvmx_gmxx_wol_ctl_t;
6350
6351/**
6352 * cvmx_gmx#_xaui_ext_loopback
6353 */
6354union cvmx_gmxx_xaui_ext_loopback {
6355 u64 u64;
6356 struct cvmx_gmxx_xaui_ext_loopback_s {
6357 u64 reserved_5_63 : 59;
6358 u64 en : 1;
6359 u64 thresh : 4;
6360 } s;
6361 struct cvmx_gmxx_xaui_ext_loopback_s cn52xx;
6362 struct cvmx_gmxx_xaui_ext_loopback_s cn52xxp1;
6363 struct cvmx_gmxx_xaui_ext_loopback_s cn56xx;
6364 struct cvmx_gmxx_xaui_ext_loopback_s cn56xxp1;
6365 struct cvmx_gmxx_xaui_ext_loopback_s cn61xx;
6366 struct cvmx_gmxx_xaui_ext_loopback_s cn63xx;
6367 struct cvmx_gmxx_xaui_ext_loopback_s cn63xxp1;
6368 struct cvmx_gmxx_xaui_ext_loopback_s cn66xx;
6369 struct cvmx_gmxx_xaui_ext_loopback_s cn68xx;
6370 struct cvmx_gmxx_xaui_ext_loopback_s cn68xxp1;
6371 struct cvmx_gmxx_xaui_ext_loopback_s cn70xx;
6372 struct cvmx_gmxx_xaui_ext_loopback_s cn70xxp1;
6373 struct cvmx_gmxx_xaui_ext_loopback_s cnf71xx;
6374};
6375
6376typedef union cvmx_gmxx_xaui_ext_loopback cvmx_gmxx_xaui_ext_loopback_t;
6377
6378#endif