Marcel Ziswiler | 2712c78 | 2022-07-21 15:41:23 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later OR MIT |
| 2 | /* |
| 3 | * Copyright 2020-2022 Toradex |
| 4 | */ |
| 5 | |
| 6 | #include "imx8mm-u-boot.dtsi" |
| 7 | |
| 8 | / { |
Marcel Ziswiler | 2712c78 | 2022-07-21 15:41:23 +0200 | [diff] [blame] | 9 | wdt-reboot { |
| 10 | compatible = "wdt-reboot"; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 11 | bootph-pre-ram; |
Marcel Ziswiler | 2712c78 | 2022-07-21 15:41:23 +0200 | [diff] [blame] | 12 | wdt = <&wdog1>; |
| 13 | }; |
| 14 | }; |
| 15 | |
| 16 | &{/aliases} { |
| 17 | eeprom0 = &eeprom_module; |
| 18 | eeprom1 = &eeprom_carrier_board; |
| 19 | eeprom2 = &eeprom_display_adapter; |
| 20 | }; |
| 21 | |
| 22 | &{/soc@0/bus@30800000/i2c@30a20000/pmic@25} { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 23 | bootph-pre-ram; |
Marcel Ziswiler | 2712c78 | 2022-07-21 15:41:23 +0200 | [diff] [blame] | 24 | }; |
| 25 | |
| 26 | &{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 27 | bootph-pre-ram; |
Marcel Ziswiler | 2712c78 | 2022-07-21 15:41:23 +0200 | [diff] [blame] | 28 | }; |
| 29 | |
Marcel Ziswiler | 8d32283 | 2023-08-23 00:17:25 +0200 | [diff] [blame] | 30 | &aips4 { |
| 31 | bootph-pre-ram; |
| 32 | }; |
| 33 | |
Marcel Ziswiler | 2712c78 | 2022-07-21 15:41:23 +0200 | [diff] [blame] | 34 | &binman_uboot { |
| 35 | offset = <0x5fc00>; |
| 36 | }; |
| 37 | |
| 38 | &gpio1 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 39 | bootph-pre-ram; |
Marcel Ziswiler | 2712c78 | 2022-07-21 15:41:23 +0200 | [diff] [blame] | 40 | }; |
| 41 | |
| 42 | &gpio2 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 43 | bootph-pre-ram; |
Marcel Ziswiler | 2712c78 | 2022-07-21 15:41:23 +0200 | [diff] [blame] | 44 | }; |
| 45 | |
| 46 | &gpio3 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 47 | bootph-pre-ram; |
Marcel Ziswiler | 2712c78 | 2022-07-21 15:41:23 +0200 | [diff] [blame] | 48 | }; |
| 49 | |
| 50 | &gpio4 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 51 | bootph-pre-ram; |
Marcel Ziswiler | 2712c78 | 2022-07-21 15:41:23 +0200 | [diff] [blame] | 52 | }; |
| 53 | |
| 54 | &gpio5 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 55 | bootph-pre-ram; |
Andrejs Cainikovs | 5ab25a1 | 2023-07-11 11:09:16 +0200 | [diff] [blame] | 56 | |
| 57 | ctrl-sleep-moci-hog { |
| 58 | bootph-pre-ram; |
| 59 | }; |
Marcel Ziswiler | 2712c78 | 2022-07-21 15:41:23 +0200 | [diff] [blame] | 60 | }; |
| 61 | |
| 62 | &i2c1 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 63 | bootph-pre-ram; |
Marcel Ziswiler | 2712c78 | 2022-07-21 15:41:23 +0200 | [diff] [blame] | 64 | |
| 65 | eeprom_module: eeprom@50 { |
| 66 | compatible = "i2c-eeprom"; |
| 67 | pagesize = <16>; |
| 68 | reg = <0x50>; |
| 69 | }; |
| 70 | }; |
| 71 | |
| 72 | &i2c2 { |
| 73 | status = "okay"; |
| 74 | }; |
| 75 | |
| 76 | &i2c4 { |
| 77 | /* EEPROM on display adapter (MIPI DSI Display Adapter) */ |
| 78 | eeprom_display_adapter: eeprom@50 { |
| 79 | compatible = "i2c-eeprom"; |
| 80 | pagesize = <16>; |
| 81 | reg = <0x50>; |
| 82 | }; |
| 83 | |
| 84 | /* EEPROM on carrier board */ |
| 85 | eeprom_carrier_board: eeprom@57 { |
| 86 | compatible = "i2c-eeprom"; |
| 87 | pagesize = <16>; |
| 88 | reg = <0x57>; |
| 89 | }; |
| 90 | }; |
| 91 | |
Andrejs Cainikovs | 5ab25a1 | 2023-07-11 11:09:16 +0200 | [diff] [blame] | 92 | &pinctrl_ctrl_sleep_moci { |
| 93 | bootph-pre-ram; |
| 94 | }; |
| 95 | |
Marcel Ziswiler | 2712c78 | 2022-07-21 15:41:23 +0200 | [diff] [blame] | 96 | &pinctrl_i2c1 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 97 | bootph-pre-ram; |
Marcel Ziswiler | 2712c78 | 2022-07-21 15:41:23 +0200 | [diff] [blame] | 98 | }; |
| 99 | |
| 100 | &pinctrl_pmic { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 101 | bootph-pre-ram; |
Marcel Ziswiler | 2712c78 | 2022-07-21 15:41:23 +0200 | [diff] [blame] | 102 | }; |
| 103 | |
| 104 | &pinctrl_uart1 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 105 | bootph-pre-ram; |
Marcel Ziswiler | 2712c78 | 2022-07-21 15:41:23 +0200 | [diff] [blame] | 106 | }; |
| 107 | |
| 108 | &pinctrl_usdhc1 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 109 | bootph-pre-ram; |
Marcel Ziswiler | 2712c78 | 2022-07-21 15:41:23 +0200 | [diff] [blame] | 110 | }; |
| 111 | |
| 112 | &pinctrl_usdhc2 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 113 | bootph-pre-ram; |
Marcel Ziswiler | 2712c78 | 2022-07-21 15:41:23 +0200 | [diff] [blame] | 114 | }; |
| 115 | |
| 116 | &pinctrl_wdog { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 117 | bootph-pre-ram; |
Marcel Ziswiler | 2712c78 | 2022-07-21 15:41:23 +0200 | [diff] [blame] | 118 | }; |
| 119 | |
| 120 | &uart1 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 121 | bootph-pre-ram; |
Marcel Ziswiler | 2712c78 | 2022-07-21 15:41:23 +0200 | [diff] [blame] | 122 | }; |
| 123 | |
Marcel Ziswiler | 8d32283 | 2023-08-23 00:17:25 +0200 | [diff] [blame] | 124 | &usbmisc1 { |
| 125 | bootph-pre-ram; |
| 126 | }; |
| 127 | |
| 128 | /* Verdin USB_1 */ |
| 129 | &usbotg1 { |
| 130 | bootph-pre-ram; |
| 131 | }; |
| 132 | |
| 133 | &usbphynop1 { |
| 134 | bootph-pre-ram; |
| 135 | }; |
| 136 | |
Marcel Ziswiler | 2712c78 | 2022-07-21 15:41:23 +0200 | [diff] [blame] | 137 | &usdhc1 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 138 | bootph-pre-ram; |
Marcel Ziswiler | 2712c78 | 2022-07-21 15:41:23 +0200 | [diff] [blame] | 139 | }; |
| 140 | |
| 141 | &usdhc2 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 142 | bootph-pre-ram; |
Marcel Ziswiler | 2712c78 | 2022-07-21 15:41:23 +0200 | [diff] [blame] | 143 | }; |
| 144 | |
| 145 | &usdhc3 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 146 | bootph-pre-ram; |
Marcel Ziswiler | 2712c78 | 2022-07-21 15:41:23 +0200 | [diff] [blame] | 147 | }; |
| 148 | |
| 149 | &wdog1 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 150 | bootph-pre-ram; |
Marcel Ziswiler | 2712c78 | 2022-07-21 15:41:23 +0200 | [diff] [blame] | 151 | }; |